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    Searched defs:RegSize (Results 1 - 7 of 7) sorted by null

  /external/llvm/lib/CodeGen/AsmPrinter/
AsmPrinterDwarf.cpp 294 unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize() * 8;
297 SmallBitVector Coverage(RegSize, false);
306 SmallBitVector Intersection(RegSize, false);
  /external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 709 unsigned RegSize = RegisterVT.getSizeInBits();
713 if (NumZeroBits == RegSize) {
725 if (NumSignBits == RegSize)
727 else if (NumZeroBits >= RegSize-1)
729 else if (NumSignBits > RegSize-8)
731 else if (NumZeroBits >= RegSize-8)
733 else if (NumSignBits > RegSize-16)
735 else if (NumZeroBits >= RegSize-16)
737 else if (NumSignBits > RegSize-32)
739 else if (NumZeroBits >= RegSize-32
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64LoadStoreOptimizer.cpp 704 unsigned RegSize = TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize();
732 if (isMatchingUpdateInsn(MI, BaseReg, RegSize))
    [all...]
  /external/llvm/include/llvm/MC/
MCRegisterInfo.h 41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
86 unsigned getSize() const { return RegSize; }
  /external/llvm/lib/Target/SystemZ/
SystemZInstrInfo.cpp 632 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
633 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
634 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
636 operator bool() const { return RegSize; }
638 unsigned RegSize, ImmLSB, ImmSize;
722 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
724 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
726 if (And.RegSize == 64)
    [all...]
  /external/clang/lib/CodeGen/
TargetInfo.cpp     [all...]
  /external/llvm/lib/Target/Mips/
MipsISelLowering.cpp     [all...]

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