| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 45 unsigned Opc = MI->getOpcode();
47 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
48 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
68 unsigned Opc = MI->getOpcode();
70 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
71 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164))
[all...] |
| Mips16InstrInfo.cpp | 68 unsigned Opc = 0;
72 Opc = Mips::MoveR3216;
75 Opc = Mips::Move32R16;
78 Opc = Mips::Mfhi16, SrcReg = 0;
82 Opc = Mips::Mflo16, SrcReg = 0;
85 assert(Opc && "Cannot copy registers");
87 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
104 unsigned Opc = 0;
106 Opc = Mips::SwRxSpImmX16;
107 assert(Opc && "Register class not handled!")
[all...] |
| MipsFastISel.cpp | 97 MachineInstrBuilder EmitInst(unsigned Opc) {
98 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
101 MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
102 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
106 MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
108 return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
111 MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg,
113 return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
160 unsigned Opc;
164 Opc = Mips::LW
[all...] |
| MipsAnalyzeImmediate.h | 20 unsigned Opc, ImmOpnd;
21 Inst(unsigned Opc, unsigned ImmOpnd);
|
| MipsSEInstrInfo.h | 68 unsigned getOppositeBranchOpc(unsigned Opc) const override;
82 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
86 std::pair<bool, bool> compareOpndSize(unsigned Opc,
|
| Mips16InstrInfo.h | 67 unsigned getOppositeBranchOpc(unsigned Opc) const override;
109 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
112 unsigned Opc) const;
|
| MipsInstrInfo.h | 85 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
132 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
134 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
|
| Mips16ISelDAGToDAG.h | 26 std::pair<SDNode*, SDNode*> selectMULT(SDNode *N, unsigned Opc, SDLoc DL,
|
| MipsAnalyzeImmediate.cpp | 15 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {}
88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) ||
89 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16))
100 Seq[0].Opc = LUi;
|
| Mips16ISelDAGToDAG.cpp | 46 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty,
49 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
259 unsigned Opc = InFlag.getOpcode(); (void)Opc;
260 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
261 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 41 // Return the non-pre/post incrementing version of 'Opc'. Return 0
43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
348 bool isUncondBranchOpcode(int Opc) {
349 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
353 bool isCondBranchOpcode(int Opc) {
354 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc
[all...] |
| ARMInstrInfo.h | 31 // Return the non-pre/post incrementing version of 'Opc'. Return 0
33 unsigned getUnindexedOpcode(unsigned Opc) const override;
|
| ARMInstrInfo.cpp | 53 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
54 switch (Opc) {
125 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ?
129 TII.get(Opc), TempReg)
131 if (Opc == ARM::LDRcp)
137 Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? ARM::tPICADD
139 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
142 if (Opc == ARM::PICADD)
|
| Thumb1InstrInfo.h | 31 // Return the non-pre/post incrementing version of 'Opc'. Return 0
33 unsigned getUnindexedOpcode(unsigned Opc) const override;
|
| /external/llvm/include/llvm/IR/ |
| AutoUpgrade.h | 55 Instruction *UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy,
61 Value *UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy);
|
| InstrTypes.h | 175 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
176 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
178 return Create(Instruction::OPC, V1, V2, Name);\
181 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
182 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
184 return Create(Instruction::OPC, V1, V2, Name, BB);\
187 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
188 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
190 return Create(Instruction::OPC, V1, V2, Name, I);\
194 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCFGOptimizer.cpp | 61 static bool IsConditionalBranch(int Opc) {
62 return (Opc == Hexagon::JMP_t) || (Opc == Hexagon::JMP_f)
63 || (Opc == Hexagon::JMP_tnew_t) || (Opc == Hexagon::JMP_fnew_t);
67 static bool IsUnconditionalJump(int Opc) {
68 return (Opc == Hexagon::JMP);
114 int Opc = MI->getOpcode();
115 if (IsConditionalBranch(Opc)) {
|
| HexagonSplitConst32AndConst64.cpp | 87 int Opc = MI->getOpcode();
88 if (Opc == Hexagon::CONST32_set) {
101 else if (Opc == Hexagon::CONST32_set_jt) {
114 else if (Opc == Hexagon::CONST32_Label) {
127 else if (Opc == Hexagon::CONST32_Int_Real) {
138 else if (Opc == Hexagon::CONST64_Int_Real) {
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 108 unsigned Opc = MBBI->getOpcode();
109 switch (Opc) {
155 unsigned Opc;
157 Opc = getLEArOpcode(IsLP64);
159 Opc = isSub
174 Opc = isSub
177 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
189 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
192 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
212 unsigned Opc = PI->getOpcode()
[all...] |
| X86FastISel.cpp | 92 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
367 unsigned Opc = 0;
373 Opc = X86::MOV8rm;
377 Opc = X86::MOV16rm;
381 Opc = X86::MOV32rm;
386 Opc = X86::MOV64rm;
391 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
394 Opc = X86::LD_Fp32m;
400 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
403 Opc = X86::LD_Fp64m
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 110 unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
430 unsigned Opc;
454 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
457 Opc = (IsZExt ?
462 Opc = (IsZExt ?
465 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
469 Opc = PPC::LD;
475 Opc = PPC::LFS;
478 Opc = FP64LoadOpc
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 344 unsigned Opc;
348 Opc = Subtarget.is64Bit() ? NVPTX::cvta_global_yes_64
352 Opc = Subtarget.is64Bit() ? NVPTX::cvta_shared_yes_64
356 Opc = Subtarget.is64Bit() ? NVPTX::cvta_const_yes_64
360 Opc = Subtarget.is64Bit() ? NVPTX::cvta_local_yes_64
364 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
369 unsigned Opc;
373 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_global_yes_64
377 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_shared_yes_64
381 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_const_yes_6
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ConditionalCompares.cpp | 580 unsigned Opc = 0;
584 Opc = AArch64::SUBSWri;
588 Opc = AArch64::SUBSXri;
593 const MCInstrDesc &MCID = TII->get(Opc);
612 unsigned Opc = 0;
618 case AArch64::SUBSWri: Opc = AArch64::CCMPWi; break;
619 case AArch64::SUBSWrr: Opc = AArch64::CCMPWr; break;
620 case AArch64::SUBSXri: Opc = AArch64::CCMPXi; break;
621 case AArch64::SUBSXrr: Opc = AArch64::CCMPXr; break;
622 case AArch64::ADDSWri: Opc = AArch64::CCMNWi; break
[all...] |
| AArch64InstrInfo.h | 208 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
210 static inline bool isCondBranchOpcode(int Opc) {
211 switch (Opc) {
227 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; }
|
| /external/llvm/utils/TableGen/ |
| FixedLenDecoderEmitter.cpp | 420 void SingletonExists(unsigned Opc) const;
438 unsigned Opc) const;
440 bool doesOpcodeNeedPredicate(unsigned Opc) const;
443 unsigned Opc) const;
446 unsigned Opc) const;
450 unsigned Opc) const;
459 void emitDecoder(raw_ostream &OS, unsigned Indentation, unsigned Opc) const;
460 unsigned getDecoderIndex(DecoderSet &Decoders, unsigned Opc) const;
818 unsigned Opc = decodeULEB128(Buffer);
830 << NumberedInstructions->at(Opc)->TheDef->getName() << "\n"
[all...] |
