| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 408 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
425 Reg1 = getXRegFromWReg(Reg1);
428 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
431 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
434 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
437 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
440 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
444 Reg1 = getDRegFromBReg(Reg1);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.h | 67 void EmitInstrRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2);
69 void EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2,
72 void EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1, unsigned Reg2,
|
| MipsAsmPrinter.cpp | 731 void MipsAsmPrinter::EmitInstrRegReg(unsigned Opcode, unsigned Reg1,
740 unsigned Temp = Reg1;
741 Reg1 = Reg2;
745 I.addOperand(MCOperand::CreateReg(Reg1));
750 void MipsAsmPrinter::EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1,
754 I.addOperand(MCOperand::CreateReg(Reg1));
760 void MipsAsmPrinter::EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1,
764 unsigned temp = Reg1;
765 Reg1 = Reg2;
768 EmitInstrRegReg(MovOpc, Reg1, FPReg1)
[all...] |
| Mips16InstrInfo.h | 117 unsigned Reg1, unsigned Reg2) const;
|
| Mips16InstrInfo.cpp | 266 unsigned Reg1, unsigned Reg2) const {
269 // unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
272 // li reg1, constant
274 // add reg1, reg1, reg2
275 // move sp, reg1
278 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
282 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
283 MIB3.addReg(Reg1);
287 MIB4.addReg(Reg1, RegState::Kill)
[all...] |
| MipsSEFrameLowering.cpp | 331 unsigned Reg1 =
335 std::swap(Reg0, Reg1);
343 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
|
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 80 bool contains(unsigned Reg1, unsigned Reg2) const {
81 return contains(Reg1) && contains(Reg2);
525 uint16_t Reg1;
527 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
531 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
547 Reg0 = Reg1;
548 Reg1 = 0;
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 116 unsigned Reg1, bool isKill1,
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
|
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.h | 101 // UnionGroups - Union Reg1's and Reg2's groups to form a new
104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
|
| TargetInstrInfo.cpp | 137 unsigned Reg1 = MI->getOperand(Idx1).getReg();
146 if (HasDef && Reg0 == Reg1 &&
154 Reg0 = Reg1;
168 MI->getOperand(Idx2).setReg(Reg1);
|
| AggressiveAntiDepBreaker.cpp | 80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
86 unsigned Group1 = GetGroup(Reg1);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 630 unsigned Reg1 = CSI[idx].getReg();
652 if (AArch64::GPR64RegClass.contains(Reg1)) {
660 } else if (AArch64::FPR64RegClass.contains(Reg1)) {
670 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1) << ", "
683 .addReg(Reg1, getPrologueDeath(MF, Reg1))
705 unsigned Reg1 = CSI[i].getReg();
723 if (AArch64::GPR64RegClass.contains(Reg1)) {
730 } else if (AArch64::FPR64RegClass.contains(Reg1)) {
739 DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1) << ", "
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 81 bool contains(unsigned Reg1, unsigned Reg2) const {
82 return MC->contains(Reg1, Reg2);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 84 unsigned Reg1, unsigned Reg2);
464 unsigned Reg1, unsigned Reg2) {
470 .addReg(Reg1)
|
| Thumb2SizeReduction.cpp | 642 unsigned Reg1 = MI->getOperand(1).getReg();
647 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
653 if (Reg1 != Reg0)
660 } else if (Reg0 != Reg1) {
[all...] |
| ARMFastISel.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 415 unsigned Reg1 = Reg;
420 .addReg(Reg1, RegState::Kill)
459 unsigned Reg1 = Reg;
465 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
533 unsigned Reg1 = Reg;
538 .addReg(Reg1, RegState::Kill)
[all...] |
| PPCInstrInfo.cpp | 251 unsigned Reg1 = MI->getOperand(1).getReg();
260 if (Reg0 == Reg1) {
280 .addReg(Reg1, getKillRegState(Reg1IsKill))
289 MI->getOperand(2).setReg(Reg1);
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | [all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
