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    Searched refs:SchedWrites (Results 1 - 2 of 2) sorted by null

  /external/llvm/utils/TableGen/
CodeGenSchedule.h 40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
111 /// 2) An implied class with a list of SchedWrites and SchedReads that are
116 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
234 std::vector<CodeGenSchedRW> SchedWrites;
310 assert(Idx < SchedWrites.size() && "bad SchedWrite index");
311 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
312 return SchedWrites[Idx];
CodeGenSchedule.cpp 107 // defined, and populate SchedReads and SchedWrites vectors. Implicit
210 SchedWrites.resize(1);
286 SchedWrites.push_back(CodeGenSchedRW(SchedWrites.size(), *SWI));
294 for (std::vector<CodeGenSchedRW>::iterator WI = SchedWrites.begin(),
295 WE = SchedWrites.end(); WI != WE; ++WI) {
312 for (unsigned WIdx = 0, WEnd = SchedWrites.size(); WIdx != WEnd; ++WIdx) {
314 SchedWrites[WIdx].dump();
347 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
467 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
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