| /external/clang/test/CodeGen/ |
| mips-clobber-reg.c | 18 __asm__ __volatile__ (".set noat \n\t addi $7,$at,77":::"at");
19 __asm__ __volatile__ ("addi $7,$v0,77":::"v0");
20 __asm__ __volatile__ ("addi $7,$v1,77":::"v1");
21 __asm__ __volatile__ ("addi $7,$a0,77":::"a0");
22 __asm__ __volatile__ ("addi $7,$a1,77":::"a1");
23 __asm__ __volatile__ ("addi $7,$a2,77":::"a2");
24 __asm__ __volatile__ ("addi $7,$a3,77":::"a3");
25 __asm__ __volatile__ ("addi $7,$t0,77":::"t0");
26 __asm__ __volatile__ ("addi $7,$t1,77":::"t1");
27 __asm__ __volatile__ ("addi $7,$t2,77":::"t2")
[all...] |
| nvptx-inlineasm.c | 7 asm __volatile__ ("{ \n\t"
|
| 2008-12-23-AsmIntPointerTie.c | 7 __asm__ __volatile__ ("%0 %1 " : "=r" (a): "0" (b));
|
| mips-constraint-regs.c | 15 __asm__ __volatile__(
26 __asm__ __volatile__(
39 __asm__ __volatile__(
|
| /external/fio/arch/ |
| arch-generic.h | 7 #define read_barrier() __asm__ __volatile__("": : :"memory")
8 #define write_barrier() __asm__ __volatile__("": : :"memory")
|
| arch-alpha.h | 22 #define read_barrier() __asm__ __volatile__("mb": : :"memory")
23 #define write_barrier() __asm__ __volatile__("wmb": : :"memory")
|
| arch-hppa.h | 23 #define read_barrier() __asm__ __volatile__ ("" : : : "memory")
24 #define write_barrier() __asm__ __volatile__ ("" : : : "memory")
|
| arch-sparc.h | 23 #define read_barrier() __asm__ __volatile__ ("" : : : "memory")
24 #define write_barrier() __asm__ __volatile__ ("" : : : "memory")
|
| arch-arm.h | 24 #define nop __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t")
25 #define read_barrier() __asm__ __volatile__ ("" : : : "memory")
26 #define write_barrier() __asm__ __volatile__ ("" : : : "memory")
28 #define nop __asm__ __volatile__ ("nop")
|
| arch-mips.h | 21 #define read_barrier() __asm__ __volatile__("": : :"memory")
22 #define write_barrier() __asm__ __volatile__("": : :"memory")
23 #define nop __asm__ __volatile__("": : :"memory")
|
| arch-x86.h | 34 #define nop __asm__ __volatile__("rep;nop": : :"memory")
35 #define read_barrier() __asm__ __volatile__("": : :"memory")
36 #define write_barrier() __asm__ __volatile__("": : :"memory")
48 __asm__ __volatile__("rdtsc" : "=A" (ret));
|
| arch-x86_64.h | 41 #define nop __asm__ __volatile__("rep;nop": : :"memory")
42 #define read_barrier() __asm__ __volatile__("lfence":::"memory")
43 #define write_barrier() __asm__ __volatile__("sfence":::"memory")
55 __asm__ __volatile__("rdtsc" : "=a" (lo), "=d" (hi));
|
| /external/chromium_org/third_party/re2/util/ |
| atomicops.h | 12 __asm__ __volatile__("xchgl (%0),%0" // The lock prefix is implicit for xchg.
21 __asm__ __volatile__("sfence" : : : "memory");
27 __asm__ __volatile__("eieio" : : : "memory");
33 __asm__ __volatile__("wmb" : : : "memory");
70 __asm__ __volatile__("mb" : : : "memory");
|
| /bionic/libm/amd64/ |
| fenv.c | 83 __asm__ __volatile__ ("fnstenv %0" : "=m" (fenv));
89 __asm__ __volatile__ ("fldenv %0" : : "m" (fenv));
92 __asm__ __volatile__ ("stmxcsr %0" : "=m" (mxcsr));
94 __asm__ __volatile__ ("ldmxcsr %0" : : "m" (mxcsr));
113 __asm__ __volatile__ ("fnstsw %0" : "=am" (status));
116 __asm__ __volatile__ ("stmxcsr %0" : "=m" (mxcsr));
140 __asm__ __volatile__ ("fwait");
159 __asm__ __volatile__ ("fnstenv %0" : "=m" (fenv));
166 __asm__ __volatile__ ("fldenv %0" : : "m" (fenv));
169 __asm__ __volatile__ ("stmxcsr %0" : "=m" (mxcsr))
[all...] |
| /development/ndk/platforms/android-3/arch-arm/include/asm/ |
| locks.h | 17 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
19 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" "1: ldrex lr, [%1]\n" " sub lr, lr, %2\n" " strex ip, lr, [%1]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
21 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " cmp lr, #0\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
26 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
28 #define __up_op_write(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_write\n" "1: ldrex lr, [%0]\n" " adds lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); })
32 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [ (…)
[all...] |
| /bionic/libc/private/ |
| bionic_atomic_x86.h | 24 __asm__ __volatile__ ( "mfence" : : : "memory" );
27 __asm__ __volatile__ ( "" : : : "memory" );
37 __asm__ __volatile__ ("lock; cmpxchgl %1, %2"
46 __asm__ __volatile__ ("xchgl %1, %0"
56 __asm__ __volatile__ ("lock; xaddl %0, %1"
|
| bionic_atomic_arm.h | 21 __asm__ __volatile__ ( "dmb ish" : : : "memory" );
24 __asm__ __volatile__ ( "" : : : "memory" );
35 __asm__ __volatile__ (
54 __asm__ __volatile__ (
68 __asm__ __volatile__ (
|
| bionic_atomic_mips.h | 25 __asm__ __volatile__ ( "sync" : : : "memory" );
28 __asm__ __volatile__ ( "" : : : "memory" );
38 __asm__ __volatile__ ("1: move %[status], %[new_value] \n"
53 __asm__ __volatile__ ("1: move %[status], %[new_value] \n"
66 __asm__ __volatile__ ("1: ll %[prev], 0(%[ptr]) \n"
|
| bionic_atomic_arm64.h | 21 __asm__ __volatile__ ( "dmb ish" : : : "memory" );
30 __asm__ __volatile__ (
47 __asm__ __volatile__ (
61 __asm__ __volatile__ (
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| barrier.h | 25 #define __fast_iob() __asm__ __volatile__( ".set push\n\t" ".set noreorder\n\t" "lw $0,%0\n\t" "nop\n\t" ".set pop" : : "m" (*(int *)CKSEG1) : "memory")
39 #define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
40 #define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
41 #define smp_wmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
44 #define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
45 #define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
46 #define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
|
| /external/chromium_org/base/ |
| cpu_unittest.cc | 60 __asm__ __volatile__("emms\n" : : : "mm0");
64 __asm__ __volatile__("xorps %%xmm0, %%xmm0\n" : : : "xmm0");
69 __asm__ __volatile__("psrldq $0, %%xmm0\n" : : : "xmm0");
74 __asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n" : : : "xmm0");
79 __asm__ __volatile__("psignb %%xmm0, %%xmm0\n" : : : "xmm0");
84 __asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n" : : : "xmm0");
89 __asm__ __volatile__("crc32 %%eax, %%eax\n" : : : "eax");
|
| /external/compiler-rt/lib/sanitizer_common/ |
| sanitizer_atomic_clang_x86.h | 21 __asm__ __volatile__("" ::: "memory");
23 __asm__ __volatile__("pause");
24 __asm__ __volatile__("" ::: "memory");
42 __asm__ __volatile__("" ::: "memory");
44 __asm__ __volatile__("" ::: "memory");
46 __asm__ __volatile__("" ::: "memory");
49 __asm__ __volatile__("" ::: "memory");
52 __asm__ __volatile__("" ::: "memory");
54 __asm__ __volatile__("" ::: "memory");
58 __asm__ __volatile__(
[all...] |
| /external/clang/test/Sema/ |
| inline-asm-validate.c | 7 __asm__ __volatile__( "stxr %w[_t], %[_r], [%[_p]]" : [_t] "=&r" (t) : [_p] "p" (p), [_r] "r" (r) : "memory");
|
| /external/chromium_org/third_party/protobuf/src/google/protobuf/stubs/ |
| atomicops_internals_x86_gcc.h | 51 #define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
59 __asm__ __volatile__("lock; cmpxchgl %1,%2"
68 __asm__ __volatile__("xchgl %1,%0" // The lock prefix is implicit for xchg.
78 __asm__ __volatile__("lock; xaddl %0,%1"
88 __asm__ __volatile__("lock; xaddl %0,%1"
93 __asm__ __volatile__("lfence" : : : "memory");
103 __asm__ __volatile__("lfence" : : : "memory");
123 __asm__ __volatile__("mfence" : : : "memory");
135 __asm__ __volatile__("mfence" : : : "memory");
145 __asm__ __volatile__("mfence" : : : "memory")
[all...] |
| /external/clang/lib/Headers/ |
| ia32intrin.h | 36 __asm__ __volatile__ ("pushf\n\t"
48 __asm__ __volatile__ ("pushq %0\n\t"
61 __asm__ __volatile__ ("pushf\n\t"
73 __asm__ __volatile__ ("pushl %0\n\t"
|
