1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This tablegen backend emits a target specifier matcher for converting parsed 11 // assembly operands in the MCInst structures. It also emits a matcher for 12 // custom operand parsing. 13 // 14 // Converting assembly operands into MCInst structures 15 // --------------------------------------------------- 16 // 17 // The input to the target specific matcher is a list of literal tokens and 18 // operands. The target specific parser should generally eliminate any syntax 19 // which is not relevant for matching; for example, comma tokens should have 20 // already been consumed and eliminated by the parser. Most instructions will 21 // end up with a single literal token (the instruction name) and some number of 22 // operands. 23 // 24 // Some example inputs, for X86: 25 // 'addl' (immediate ...) (register ...) 26 // 'add' (immediate ...) (memory ...) 27 // 'call' '*' %epc 28 // 29 // The assembly matcher is responsible for converting this input into a precise 30 // machine instruction (i.e., an instruction with a well defined encoding). This 31 // mapping has several properties which complicate matching: 32 // 33 // - It may be ambiguous; many architectures can legally encode particular 34 // variants of an instruction in different ways (for example, using a smaller 35 // encoding for small immediates). Such ambiguities should never be 36 // arbitrarily resolved by the assembler, the assembler is always responsible 37 // for choosing the "best" available instruction. 38 // 39 // - It may depend on the subtarget or the assembler context. Instructions 40 // which are invalid for the current mode, but otherwise unambiguous (e.g., 41 // an SSE instruction in a file being assembled for i486) should be accepted 42 // and rejected by the assembler front end. However, if the proper encoding 43 // for an instruction is dependent on the assembler context then the matcher 44 // is responsible for selecting the correct machine instruction for the 45 // current mode. 46 // 47 // The core matching algorithm attempts to exploit the regularity in most 48 // instruction sets to quickly determine the set of possibly matching 49 // instructions, and the simplify the generated code. Additionally, this helps 50 // to ensure that the ambiguities are intentionally resolved by the user. 51 // 52 // The matching is divided into two distinct phases: 53 // 54 // 1. Classification: Each operand is mapped to the unique set which (a) 55 // contains it, and (b) is the largest such subset for which a single 56 // instruction could match all members. 57 // 58 // For register classes, we can generate these subgroups automatically. For 59 // arbitrary operands, we expect the user to define the classes and their 60 // relations to one another (for example, 8-bit signed immediates as a 61 // subset of 32-bit immediates). 62 // 63 // By partitioning the operands in this way, we guarantee that for any 64 // tuple of classes, any single instruction must match either all or none 65 // of the sets of operands which could classify to that tuple. 66 // 67 // In addition, the subset relation amongst classes induces a partial order 68 // on such tuples, which we use to resolve ambiguities. 69 // 70 // 2. The input can now be treated as a tuple of classes (static tokens are 71 // simple singleton sets). Each such tuple should generally map to a single 72 // instruction (we currently ignore cases where this isn't true, whee!!!), 73 // which we can emit a simple matcher for. 74 // 75 // Custom Operand Parsing 76 // ---------------------- 77 // 78 // Some targets need a custom way to parse operands, some specific instructions 79 // can contain arguments that can represent processor flags and other kinds of 80 // identifiers that need to be mapped to specific values in the final encoded 81 // instructions. The target specific custom operand parsing works in the 82 // following way: 83 // 84 // 1. A operand match table is built, each entry contains a mnemonic, an 85 // operand class, a mask for all operand positions for that same 86 // class/mnemonic and target features to be checked while trying to match. 87 // 88 // 2. The operand matcher will try every possible entry with the same 89 // mnemonic and will check if the target feature for this mnemonic also 90 // matches. After that, if the operand to be matched has its index 91 // present in the mask, a successful match occurs. Otherwise, fallback 92 // to the regular operand parsing. 93 // 94 // 3. For a match success, each operand class that has a 'ParserMethod' 95 // becomes part of a switch from where the custom method is called. 96 // 97 //===----------------------------------------------------------------------===// 98 99 #include "CodeGenTarget.h" 100 #include "llvm/ADT/PointerUnion.h" 101 #include "llvm/ADT/STLExtras.h" 102 #include "llvm/ADT/SmallPtrSet.h" 103 #include "llvm/ADT/SmallVector.h" 104 #include "llvm/ADT/StringExtras.h" 105 #include "llvm/Support/CommandLine.h" 106 #include "llvm/Support/Debug.h" 107 #include "llvm/Support/ErrorHandling.h" 108 #include "llvm/TableGen/Error.h" 109 #include "llvm/TableGen/Record.h" 110 #include "llvm/TableGen/StringMatcher.h" 111 #include "llvm/TableGen/StringToOffsetTable.h" 112 #include "llvm/TableGen/TableGenBackend.h" 113 #include <cassert> 114 #include <cctype> 115 #include <map> 116 #include <set> 117 #include <sstream> 118 using namespace llvm; 119 120 #define DEBUG_TYPE "asm-matcher-emitter" 121 122 static cl::opt<std::string> 123 MatchPrefix("match-prefix", cl::init(""), 124 cl::desc("Only match instructions with the given prefix")); 125 126 namespace { 127 class AsmMatcherInfo; 128 struct SubtargetFeatureInfo; 129 130 // Register sets are used as keys in some second-order sets TableGen creates 131 // when generating its data structures. This means that the order of two 132 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and 133 // can even affect compiler output (at least seen in diagnostics produced when 134 // all matches fail). So we use a type that sorts them consistently. 135 typedef std::set<Record*, LessRecordByID> RegisterSet; 136 137 class AsmMatcherEmitter { 138 RecordKeeper &Records; 139 public: 140 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {} 141 142 void run(raw_ostream &o); 143 }; 144 145 /// ClassInfo - Helper class for storing the information about a particular 146 /// class of operands which can be matched. 147 struct ClassInfo { 148 enum ClassInfoKind { 149 /// Invalid kind, for use as a sentinel value. 150 Invalid = 0, 151 152 /// The class for a particular token. 153 Token, 154 155 /// The (first) register class, subsequent register classes are 156 /// RegisterClass0+1, and so on. 157 RegisterClass0, 158 159 /// The (first) user defined class, subsequent user defined classes are 160 /// UserClass0+1, and so on. 161 UserClass0 = 1<<16 162 }; 163 164 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 + 165 /// N) for the Nth user defined class. 166 unsigned Kind; 167 168 /// SuperClasses - The super classes of this class. Note that for simplicities 169 /// sake user operands only record their immediate super class, while register 170 /// operands include all superclasses. 171 std::vector<ClassInfo*> SuperClasses; 172 173 /// Name - The full class name, suitable for use in an enum. 174 std::string Name; 175 176 /// ClassName - The unadorned generic name for this class (e.g., Token). 177 std::string ClassName; 178 179 /// ValueName - The name of the value this class represents; for a token this 180 /// is the literal token string, for an operand it is the TableGen class (or 181 /// empty if this is a derived class). 182 std::string ValueName; 183 184 /// PredicateMethod - The name of the operand method to test whether the 185 /// operand matches this class; this is not valid for Token or register kinds. 186 std::string PredicateMethod; 187 188 /// RenderMethod - The name of the operand method to add this operand to an 189 /// MCInst; this is not valid for Token or register kinds. 190 std::string RenderMethod; 191 192 /// ParserMethod - The name of the operand method to do a target specific 193 /// parsing on the operand. 194 std::string ParserMethod; 195 196 /// For register classes: the records for all the registers in this class. 197 RegisterSet Registers; 198 199 /// For custom match classes: the diagnostic kind for when the predicate fails. 200 std::string DiagnosticType; 201 public: 202 /// isRegisterClass() - Check if this is a register class. 203 bool isRegisterClass() const { 204 return Kind >= RegisterClass0 && Kind < UserClass0; 205 } 206 207 /// isUserClass() - Check if this is a user defined class. 208 bool isUserClass() const { 209 return Kind >= UserClass0; 210 } 211 212 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes 213 /// are related if they are in the same class hierarchy. 214 bool isRelatedTo(const ClassInfo &RHS) const { 215 // Tokens are only related to tokens. 216 if (Kind == Token || RHS.Kind == Token) 217 return Kind == Token && RHS.Kind == Token; 218 219 // Registers classes are only related to registers classes, and only if 220 // their intersection is non-empty. 221 if (isRegisterClass() || RHS.isRegisterClass()) { 222 if (!isRegisterClass() || !RHS.isRegisterClass()) 223 return false; 224 225 RegisterSet Tmp; 226 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin()); 227 std::set_intersection(Registers.begin(), Registers.end(), 228 RHS.Registers.begin(), RHS.Registers.end(), 229 II, LessRecordByID()); 230 231 return !Tmp.empty(); 232 } 233 234 // Otherwise we have two users operands; they are related if they are in the 235 // same class hierarchy. 236 // 237 // FIXME: This is an oversimplification, they should only be related if they 238 // intersect, however we don't have that information. 239 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!"); 240 const ClassInfo *Root = this; 241 while (!Root->SuperClasses.empty()) 242 Root = Root->SuperClasses.front(); 243 244 const ClassInfo *RHSRoot = &RHS; 245 while (!RHSRoot->SuperClasses.empty()) 246 RHSRoot = RHSRoot->SuperClasses.front(); 247 248 return Root == RHSRoot; 249 } 250 251 /// isSubsetOf - Test whether this class is a subset of \p RHS. 252 bool isSubsetOf(const ClassInfo &RHS) const { 253 // This is a subset of RHS if it is the same class... 254 if (this == &RHS) 255 return true; 256 257 // ... or if any of its super classes are a subset of RHS. 258 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(), 259 ie = SuperClasses.end(); it != ie; ++it) 260 if ((*it)->isSubsetOf(RHS)) 261 return true; 262 263 return false; 264 } 265 266 /// operator< - Compare two classes. 267 bool operator<(const ClassInfo &RHS) const { 268 if (this == &RHS) 269 return false; 270 271 // Unrelated classes can be ordered by kind. 272 if (!isRelatedTo(RHS)) 273 return Kind < RHS.Kind; 274 275 switch (Kind) { 276 case Invalid: 277 llvm_unreachable("Invalid kind!"); 278 279 default: 280 // This class precedes the RHS if it is a proper subset of the RHS. 281 if (isSubsetOf(RHS)) 282 return true; 283 if (RHS.isSubsetOf(*this)) 284 return false; 285 286 // Otherwise, order by name to ensure we have a total ordering. 287 return ValueName < RHS.ValueName; 288 } 289 } 290 }; 291 292 /// MatchableInfo - Helper class for storing the necessary information for an 293 /// instruction or alias which is capable of being matched. 294 struct MatchableInfo { 295 struct AsmOperand { 296 /// Token - This is the token that the operand came from. 297 StringRef Token; 298 299 /// The unique class instance this operand should match. 300 ClassInfo *Class; 301 302 /// The operand name this is, if anything. 303 StringRef SrcOpName; 304 305 /// The suboperand index within SrcOpName, or -1 for the entire operand. 306 int SubOpIdx; 307 308 /// Register record if this token is singleton register. 309 Record *SingletonReg; 310 311 explicit AsmOperand(StringRef T) : Token(T), Class(nullptr), SubOpIdx(-1), 312 SingletonReg(nullptr) {} 313 }; 314 315 /// ResOperand - This represents a single operand in the result instruction 316 /// generated by the match. In cases (like addressing modes) where a single 317 /// assembler operand expands to multiple MCOperands, this represents the 318 /// single assembler operand, not the MCOperand. 319 struct ResOperand { 320 enum { 321 /// RenderAsmOperand - This represents an operand result that is 322 /// generated by calling the render method on the assembly operand. The 323 /// corresponding AsmOperand is specified by AsmOperandNum. 324 RenderAsmOperand, 325 326 /// TiedOperand - This represents a result operand that is a duplicate of 327 /// a previous result operand. 328 TiedOperand, 329 330 /// ImmOperand - This represents an immediate value that is dumped into 331 /// the operand. 332 ImmOperand, 333 334 /// RegOperand - This represents a fixed register that is dumped in. 335 RegOperand 336 } Kind; 337 338 union { 339 /// This is the operand # in the AsmOperands list that this should be 340 /// copied from. 341 unsigned AsmOperandNum; 342 343 /// TiedOperandNum - This is the (earlier) result operand that should be 344 /// copied from. 345 unsigned TiedOperandNum; 346 347 /// ImmVal - This is the immediate value added to the instruction. 348 int64_t ImmVal; 349 350 /// Register - This is the register record. 351 Record *Register; 352 }; 353 354 /// MINumOperands - The number of MCInst operands populated by this 355 /// operand. 356 unsigned MINumOperands; 357 358 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) { 359 ResOperand X; 360 X.Kind = RenderAsmOperand; 361 X.AsmOperandNum = AsmOpNum; 362 X.MINumOperands = NumOperands; 363 return X; 364 } 365 366 static ResOperand getTiedOp(unsigned TiedOperandNum) { 367 ResOperand X; 368 X.Kind = TiedOperand; 369 X.TiedOperandNum = TiedOperandNum; 370 X.MINumOperands = 1; 371 return X; 372 } 373 374 static ResOperand getImmOp(int64_t Val) { 375 ResOperand X; 376 X.Kind = ImmOperand; 377 X.ImmVal = Val; 378 X.MINumOperands = 1; 379 return X; 380 } 381 382 static ResOperand getRegOp(Record *Reg) { 383 ResOperand X; 384 X.Kind = RegOperand; 385 X.Register = Reg; 386 X.MINumOperands = 1; 387 return X; 388 } 389 }; 390 391 /// AsmVariantID - Target's assembly syntax variant no. 392 int AsmVariantID; 393 394 /// TheDef - This is the definition of the instruction or InstAlias that this 395 /// matchable came from. 396 Record *const TheDef; 397 398 /// DefRec - This is the definition that it came from. 399 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec; 400 401 const CodeGenInstruction *getResultInst() const { 402 if (DefRec.is<const CodeGenInstruction*>()) 403 return DefRec.get<const CodeGenInstruction*>(); 404 return DefRec.get<const CodeGenInstAlias*>()->ResultInst; 405 } 406 407 /// ResOperands - This is the operand list that should be built for the result 408 /// MCInst. 409 SmallVector<ResOperand, 8> ResOperands; 410 411 /// AsmString - The assembly string for this instruction (with variants 412 /// removed), e.g. "movsx $src, $dst". 413 std::string AsmString; 414 415 /// Mnemonic - This is the first token of the matched instruction, its 416 /// mnemonic. 417 StringRef Mnemonic; 418 419 /// AsmOperands - The textual operands that this instruction matches, 420 /// annotated with a class and where in the OperandList they were defined. 421 /// This directly corresponds to the tokenized AsmString after the mnemonic is 422 /// removed. 423 SmallVector<AsmOperand, 8> AsmOperands; 424 425 /// Predicates - The required subtarget features to match this instruction. 426 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures; 427 428 /// ConversionFnKind - The enum value which is passed to the generated 429 /// convertToMCInst to convert parsed operands into an MCInst for this 430 /// function. 431 std::string ConversionFnKind; 432 433 /// If this instruction is deprecated in some form. 434 bool HasDeprecation; 435 436 MatchableInfo(const CodeGenInstruction &CGI) 437 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI), 438 AsmString(CGI.AsmString) { 439 } 440 441 MatchableInfo(const CodeGenInstAlias *Alias) 442 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias), 443 AsmString(Alias->AsmString) { 444 } 445 446 // Two-operand aliases clone from the main matchable, but mark the second 447 // operand as a tied operand of the first for purposes of the assembler. 448 void formTwoOperandAlias(StringRef Constraint); 449 450 void initialize(const AsmMatcherInfo &Info, 451 SmallPtrSet<Record*, 16> &SingletonRegisters, 452 int AsmVariantNo, std::string &RegisterPrefix); 453 454 /// validate - Return true if this matchable is a valid thing to match against 455 /// and perform a bunch of validity checking. 456 bool validate(StringRef CommentDelimiter, bool Hack) const; 457 458 /// extractSingletonRegisterForAsmOperand - Extract singleton register, 459 /// if present, from specified token. 460 void 461 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info, 462 std::string &RegisterPrefix); 463 464 /// findAsmOperand - Find the AsmOperand with the specified name and 465 /// suboperand index. 466 int findAsmOperand(StringRef N, int SubOpIdx) const { 467 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) 468 if (N == AsmOperands[i].SrcOpName && 469 SubOpIdx == AsmOperands[i].SubOpIdx) 470 return i; 471 return -1; 472 } 473 474 /// findAsmOperandNamed - Find the first AsmOperand with the specified name. 475 /// This does not check the suboperand index. 476 int findAsmOperandNamed(StringRef N) const { 477 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) 478 if (N == AsmOperands[i].SrcOpName) 479 return i; 480 return -1; 481 } 482 483 void buildInstructionResultOperands(); 484 void buildAliasResultOperands(); 485 486 /// operator< - Compare two matchables. 487 bool operator<(const MatchableInfo &RHS) const { 488 // The primary comparator is the instruction mnemonic. 489 if (Mnemonic != RHS.Mnemonic) 490 return Mnemonic < RHS.Mnemonic; 491 492 if (AsmOperands.size() != RHS.AsmOperands.size()) 493 return AsmOperands.size() < RHS.AsmOperands.size(); 494 495 // Compare lexicographically by operand. The matcher validates that other 496 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith(). 497 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 498 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) 499 return true; 500 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class) 501 return false; 502 } 503 504 // Give matches that require more features higher precedence. This is useful 505 // because we cannot define AssemblerPredicates with the negation of 506 // processor features. For example, ARM v6 "nop" may be either a HINT or 507 // MOV. With v6, we want to match HINT. The assembler has no way to 508 // predicate MOV under "NoV6", but HINT will always match first because it 509 // requires V6 while MOV does not. 510 if (RequiredFeatures.size() != RHS.RequiredFeatures.size()) 511 return RequiredFeatures.size() > RHS.RequiredFeatures.size(); 512 513 return false; 514 } 515 516 /// couldMatchAmbiguouslyWith - Check whether this matchable could 517 /// ambiguously match the same set of operands as \p RHS (without being a 518 /// strictly superior match). 519 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) { 520 // The primary comparator is the instruction mnemonic. 521 if (Mnemonic != RHS.Mnemonic) 522 return false; 523 524 // The number of operands is unambiguous. 525 if (AsmOperands.size() != RHS.AsmOperands.size()) 526 return false; 527 528 // Otherwise, make sure the ordering of the two instructions is unambiguous 529 // by checking that either (a) a token or operand kind discriminates them, 530 // or (b) the ordering among equivalent kinds is consistent. 531 532 // Tokens and operand kinds are unambiguous (assuming a correct target 533 // specific parser). 534 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) 535 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind || 536 AsmOperands[i].Class->Kind == ClassInfo::Token) 537 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class || 538 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class) 539 return false; 540 541 // Otherwise, this operand could commute if all operands are equivalent, or 542 // there is a pair of operands that compare less than and a pair that 543 // compare greater than. 544 bool HasLT = false, HasGT = false; 545 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 546 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) 547 HasLT = true; 548 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class) 549 HasGT = true; 550 } 551 552 return !(HasLT ^ HasGT); 553 } 554 555 void dump(); 556 557 private: 558 void tokenizeAsmString(const AsmMatcherInfo &Info); 559 }; 560 561 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget 562 /// feature which participates in instruction matching. 563 struct SubtargetFeatureInfo { 564 /// \brief The predicate record for this feature. 565 Record *TheDef; 566 567 /// \brief An unique index assigned to represent this feature. 568 unsigned Index; 569 570 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} 571 572 /// \brief The name of the enumerated constant identifying this feature. 573 std::string getEnumName() const { 574 return "Feature_" + TheDef->getName(); 575 } 576 577 void dump() { 578 errs() << getEnumName() << " " << Index << "\n"; 579 TheDef->dump(); 580 } 581 }; 582 583 struct OperandMatchEntry { 584 unsigned OperandMask; 585 MatchableInfo* MI; 586 ClassInfo *CI; 587 588 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci, 589 unsigned opMask) { 590 OperandMatchEntry X; 591 X.OperandMask = opMask; 592 X.CI = ci; 593 X.MI = mi; 594 return X; 595 } 596 }; 597 598 599 class AsmMatcherInfo { 600 public: 601 /// Tracked Records 602 RecordKeeper &Records; 603 604 /// The tablegen AsmParser record. 605 Record *AsmParser; 606 607 /// Target - The target information. 608 CodeGenTarget &Target; 609 610 /// The classes which are needed for matching. 611 std::vector<ClassInfo*> Classes; 612 613 /// The information on the matchables to match. 614 std::vector<MatchableInfo*> Matchables; 615 616 /// Info for custom matching operands by user defined methods. 617 std::vector<OperandMatchEntry> OperandMatchInfo; 618 619 /// Map of Register records to their class information. 620 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy; 621 RegisterClassesTy RegisterClasses; 622 623 /// Map of Predicate records to their subtarget information. 624 std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> SubtargetFeatures; 625 626 /// Map of AsmOperandClass records to their class information. 627 std::map<Record*, ClassInfo*> AsmOperandClasses; 628 629 private: 630 /// Map of token to class information which has already been constructed. 631 std::map<std::string, ClassInfo*> TokenClasses; 632 633 /// Map of RegisterClass records to their class information. 634 std::map<Record*, ClassInfo*> RegisterClassClasses; 635 636 private: 637 /// getTokenClass - Lookup or create the class for the given token. 638 ClassInfo *getTokenClass(StringRef Token); 639 640 /// getOperandClass - Lookup or create the class for the given operand. 641 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI, 642 int SubOpIdx); 643 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx); 644 645 /// buildRegisterClasses - Build the ClassInfo* instances for register 646 /// classes. 647 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters); 648 649 /// buildOperandClasses - Build the ClassInfo* instances for user defined 650 /// operand classes. 651 void buildOperandClasses(); 652 653 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName, 654 unsigned AsmOpIdx); 655 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName, 656 MatchableInfo::AsmOperand &Op); 657 658 public: 659 AsmMatcherInfo(Record *AsmParser, 660 CodeGenTarget &Target, 661 RecordKeeper &Records); 662 663 /// buildInfo - Construct the various tables used during matching. 664 void buildInfo(); 665 666 /// buildOperandMatchInfo - Build the necessary information to handle user 667 /// defined operand parsing methods. 668 void buildOperandMatchInfo(); 669 670 /// getSubtargetFeature - Lookup or create the subtarget feature info for the 671 /// given operand. 672 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const { 673 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!"); 674 std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator I = 675 SubtargetFeatures.find(Def); 676 return I == SubtargetFeatures.end() ? nullptr : I->second; 677 } 678 679 RecordKeeper &getRecords() const { 680 return Records; 681 } 682 }; 683 684 } // End anonymous namespace 685 686 void MatchableInfo::dump() { 687 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n"; 688 689 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 690 AsmOperand &Op = AsmOperands[i]; 691 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - "; 692 errs() << '\"' << Op.Token << "\"\n"; 693 } 694 } 695 696 static std::pair<StringRef, StringRef> 697 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) { 698 // Split via the '='. 699 std::pair<StringRef, StringRef> Ops = S.split('='); 700 if (Ops.second == "") 701 PrintFatalError(Loc, "missing '=' in two-operand alias constraint"); 702 // Trim whitespace and the leading '$' on the operand names. 703 size_t start = Ops.first.find_first_of('$'); 704 if (start == std::string::npos) 705 PrintFatalError(Loc, "expected '$' prefix on asm operand name"); 706 Ops.first = Ops.first.slice(start + 1, std::string::npos); 707 size_t end = Ops.first.find_last_of(" \t"); 708 Ops.first = Ops.first.slice(0, end); 709 // Now the second operand. 710 start = Ops.second.find_first_of('$'); 711 if (start == std::string::npos) 712 PrintFatalError(Loc, "expected '$' prefix on asm operand name"); 713 Ops.second = Ops.second.slice(start + 1, std::string::npos); 714 end = Ops.second.find_last_of(" \t"); 715 Ops.first = Ops.first.slice(0, end); 716 return Ops; 717 } 718 719 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) { 720 // Figure out which operands are aliased and mark them as tied. 721 std::pair<StringRef, StringRef> Ops = 722 parseTwoOperandConstraint(Constraint, TheDef->getLoc()); 723 724 // Find the AsmOperands that refer to the operands we're aliasing. 725 int SrcAsmOperand = findAsmOperandNamed(Ops.first); 726 int DstAsmOperand = findAsmOperandNamed(Ops.second); 727 if (SrcAsmOperand == -1) 728 PrintFatalError(TheDef->getLoc(), 729 "unknown source two-operand alias operand '" + Ops.first + 730 "'."); 731 if (DstAsmOperand == -1) 732 PrintFatalError(TheDef->getLoc(), 733 "unknown destination two-operand alias operand '" + 734 Ops.second + "'."); 735 736 // Find the ResOperand that refers to the operand we're aliasing away 737 // and update it to refer to the combined operand instead. 738 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) { 739 ResOperand &Op = ResOperands[i]; 740 if (Op.Kind == ResOperand::RenderAsmOperand && 741 Op.AsmOperandNum == (unsigned)SrcAsmOperand) { 742 Op.AsmOperandNum = DstAsmOperand; 743 break; 744 } 745 } 746 // Remove the AsmOperand for the alias operand. 747 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand); 748 // Adjust the ResOperand references to any AsmOperands that followed 749 // the one we just deleted. 750 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) { 751 ResOperand &Op = ResOperands[i]; 752 switch(Op.Kind) { 753 default: 754 // Nothing to do for operands that don't reference AsmOperands. 755 break; 756 case ResOperand::RenderAsmOperand: 757 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand) 758 --Op.AsmOperandNum; 759 break; 760 case ResOperand::TiedOperand: 761 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand) 762 --Op.TiedOperandNum; 763 break; 764 } 765 } 766 } 767 768 void MatchableInfo::initialize(const AsmMatcherInfo &Info, 769 SmallPtrSet<Record*, 16> &SingletonRegisters, 770 int AsmVariantNo, std::string &RegisterPrefix) { 771 AsmVariantID = AsmVariantNo; 772 AsmString = 773 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo); 774 775 tokenizeAsmString(Info); 776 777 // Compute the require features. 778 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates"); 779 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) 780 if (SubtargetFeatureInfo *Feature = 781 Info.getSubtargetFeature(Predicates[i])) 782 RequiredFeatures.push_back(Feature); 783 784 // Collect singleton registers, if used. 785 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 786 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix); 787 if (Record *Reg = AsmOperands[i].SingletonReg) 788 SingletonRegisters.insert(Reg); 789 } 790 791 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask"); 792 if (!DepMask) 793 DepMask = TheDef->getValue("ComplexDeprecationPredicate"); 794 795 HasDeprecation = 796 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false; 797 } 798 799 /// tokenizeAsmString - Tokenize a simplified assembly string. 800 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) { 801 StringRef String = AsmString; 802 unsigned Prev = 0; 803 bool InTok = true; 804 for (unsigned i = 0, e = String.size(); i != e; ++i) { 805 switch (String[i]) { 806 case '[': 807 case ']': 808 case '*': 809 case '!': 810 case ' ': 811 case '\t': 812 case ',': 813 if (InTok) { 814 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 815 InTok = false; 816 } 817 if (!isspace(String[i]) && String[i] != ',') 818 AsmOperands.push_back(AsmOperand(String.substr(i, 1))); 819 Prev = i + 1; 820 break; 821 822 case '\\': 823 if (InTok) { 824 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 825 InTok = false; 826 } 827 ++i; 828 assert(i != String.size() && "Invalid quoted character"); 829 AsmOperands.push_back(AsmOperand(String.substr(i, 1))); 830 Prev = i + 1; 831 break; 832 833 case '$': { 834 if (InTok) { 835 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 836 InTok = false; 837 } 838 839 // If this isn't "${", treat like a normal token. 840 if (i + 1 == String.size() || String[i + 1] != '{') { 841 Prev = i; 842 break; 843 } 844 845 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}'); 846 assert(End != String.end() && "Missing brace in operand reference!"); 847 size_t EndPos = End - String.begin(); 848 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1))); 849 Prev = EndPos + 1; 850 i = EndPos; 851 break; 852 } 853 854 case '.': 855 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) { 856 if (InTok) 857 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 858 Prev = i; 859 } 860 InTok = true; 861 break; 862 863 default: 864 InTok = true; 865 } 866 } 867 if (InTok && Prev != String.size()) 868 AsmOperands.push_back(AsmOperand(String.substr(Prev))); 869 870 // The first token of the instruction is the mnemonic, which must be a 871 // simple string, not a $foo variable or a singleton register. 872 if (AsmOperands.empty()) 873 PrintFatalError(TheDef->getLoc(), 874 "Instruction '" + TheDef->getName() + "' has no tokens"); 875 Mnemonic = AsmOperands[0].Token; 876 if (Mnemonic.empty()) 877 PrintFatalError(TheDef->getLoc(), 878 "Missing instruction mnemonic"); 879 // FIXME : Check and raise an error if it is a register. 880 if (Mnemonic[0] == '$') 881 PrintFatalError(TheDef->getLoc(), 882 "Invalid instruction mnemonic '" + Mnemonic + "'!"); 883 884 // Remove the first operand, it is tracked in the mnemonic field. 885 AsmOperands.erase(AsmOperands.begin()); 886 } 887 888 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const { 889 // Reject matchables with no .s string. 890 if (AsmString.empty()) 891 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string"); 892 893 // Reject any matchables with a newline in them, they should be marked 894 // isCodeGenOnly if they are pseudo instructions. 895 if (AsmString.find('\n') != std::string::npos) 896 PrintFatalError(TheDef->getLoc(), 897 "multiline instruction is not valid for the asmparser, " 898 "mark it isCodeGenOnly"); 899 900 // Remove comments from the asm string. We know that the asmstring only 901 // has one line. 902 if (!CommentDelimiter.empty() && 903 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos) 904 PrintFatalError(TheDef->getLoc(), 905 "asmstring for instruction has comment character in it, " 906 "mark it isCodeGenOnly"); 907 908 // Reject matchables with operand modifiers, these aren't something we can 909 // handle, the target should be refactored to use operands instead of 910 // modifiers. 911 // 912 // Also, check for instructions which reference the operand multiple times; 913 // this implies a constraint we would not honor. 914 std::set<std::string> OperandNames; 915 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 916 StringRef Tok = AsmOperands[i].Token; 917 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos) 918 PrintFatalError(TheDef->getLoc(), 919 "matchable with operand modifier '" + Tok + 920 "' not supported by asm matcher. Mark isCodeGenOnly!"); 921 922 // Verify that any operand is only mentioned once. 923 // We reject aliases and ignore instructions for now. 924 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) { 925 if (!Hack) 926 PrintFatalError(TheDef->getLoc(), 927 "ERROR: matchable with tied operand '" + Tok + 928 "' can never be matched!"); 929 // FIXME: Should reject these. The ARM backend hits this with $lane in a 930 // bunch of instructions. It is unclear what the right answer is. 931 DEBUG({ 932 errs() << "warning: '" << TheDef->getName() << "': " 933 << "ignoring instruction with tied operand '" 934 << Tok << "'\n"; 935 }); 936 return false; 937 } 938 } 939 940 return true; 941 } 942 943 /// extractSingletonRegisterForAsmOperand - Extract singleton register, 944 /// if present, from specified token. 945 void MatchableInfo:: 946 extractSingletonRegisterForAsmOperand(unsigned OperandNo, 947 const AsmMatcherInfo &Info, 948 std::string &RegisterPrefix) { 949 StringRef Tok = AsmOperands[OperandNo].Token; 950 if (RegisterPrefix.empty()) { 951 std::string LoweredTok = Tok.lower(); 952 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok)) 953 AsmOperands[OperandNo].SingletonReg = Reg->TheDef; 954 return; 955 } 956 957 if (!Tok.startswith(RegisterPrefix)) 958 return; 959 960 StringRef RegName = Tok.substr(RegisterPrefix.size()); 961 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName)) 962 AsmOperands[OperandNo].SingletonReg = Reg->TheDef; 963 964 // If there is no register prefix (i.e. "%" in "%eax"), then this may 965 // be some random non-register token, just ignore it. 966 return; 967 } 968 969 static std::string getEnumNameForToken(StringRef Str) { 970 std::string Res; 971 972 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) { 973 switch (*it) { 974 case '*': Res += "_STAR_"; break; 975 case '%': Res += "_PCT_"; break; 976 case ':': Res += "_COLON_"; break; 977 case '!': Res += "_EXCLAIM_"; break; 978 case '.': Res += "_DOT_"; break; 979 case '<': Res += "_LT_"; break; 980 case '>': Res += "_GT_"; break; 981 default: 982 if ((*it >= 'A' && *it <= 'Z') || 983 (*it >= 'a' && *it <= 'z') || 984 (*it >= '0' && *it <= '9')) 985 Res += *it; 986 else 987 Res += "_" + utostr((unsigned) *it) + "_"; 988 } 989 } 990 991 return Res; 992 } 993 994 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) { 995 ClassInfo *&Entry = TokenClasses[Token]; 996 997 if (!Entry) { 998 Entry = new ClassInfo(); 999 Entry->Kind = ClassInfo::Token; 1000 Entry->ClassName = "Token"; 1001 Entry->Name = "MCK_" + getEnumNameForToken(Token); 1002 Entry->ValueName = Token; 1003 Entry->PredicateMethod = "<invalid>"; 1004 Entry->RenderMethod = "<invalid>"; 1005 Entry->ParserMethod = ""; 1006 Entry->DiagnosticType = ""; 1007 Classes.push_back(Entry); 1008 } 1009 1010 return Entry; 1011 } 1012 1013 ClassInfo * 1014 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI, 1015 int SubOpIdx) { 1016 Record *Rec = OI.Rec; 1017 if (SubOpIdx != -1) 1018 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef(); 1019 return getOperandClass(Rec, SubOpIdx); 1020 } 1021 1022 ClassInfo * 1023 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) { 1024 if (Rec->isSubClassOf("RegisterOperand")) { 1025 // RegisterOperand may have an associated ParserMatchClass. If it does, 1026 // use it, else just fall back to the underlying register class. 1027 const RecordVal *R = Rec->getValue("ParserMatchClass"); 1028 if (!R || !R->getValue()) 1029 PrintFatalError("Record `" + Rec->getName() + 1030 "' does not have a ParserMatchClass!\n"); 1031 1032 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) { 1033 Record *MatchClass = DI->getDef(); 1034 if (ClassInfo *CI = AsmOperandClasses[MatchClass]) 1035 return CI; 1036 } 1037 1038 // No custom match class. Just use the register class. 1039 Record *ClassRec = Rec->getValueAsDef("RegClass"); 1040 if (!ClassRec) 1041 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() + 1042 "' has no associated register class!\n"); 1043 if (ClassInfo *CI = RegisterClassClasses[ClassRec]) 1044 return CI; 1045 PrintFatalError(Rec->getLoc(), "register class has no class info!"); 1046 } 1047 1048 1049 if (Rec->isSubClassOf("RegisterClass")) { 1050 if (ClassInfo *CI = RegisterClassClasses[Rec]) 1051 return CI; 1052 PrintFatalError(Rec->getLoc(), "register class has no class info!"); 1053 } 1054 1055 if (!Rec->isSubClassOf("Operand")) 1056 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() + 1057 "' does not derive from class Operand!\n"); 1058 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass"); 1059 if (ClassInfo *CI = AsmOperandClasses[MatchClass]) 1060 return CI; 1061 1062 PrintFatalError(Rec->getLoc(), "operand has no match class!"); 1063 } 1064 1065 struct LessRegisterSet { 1066 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const { 1067 // std::set<T> defines its own compariso "operator<", but it 1068 // performs a lexicographical comparison by T's innate comparison 1069 // for some reason. We don't want non-deterministic pointer 1070 // comparisons so use this instead. 1071 return std::lexicographical_compare(LHS.begin(), LHS.end(), 1072 RHS.begin(), RHS.end(), 1073 LessRecordByID()); 1074 } 1075 }; 1076 1077 void AsmMatcherInfo:: 1078 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) { 1079 const std::vector<CodeGenRegister*> &Registers = 1080 Target.getRegBank().getRegisters(); 1081 ArrayRef<CodeGenRegisterClass*> RegClassList = 1082 Target.getRegBank().getRegClasses(); 1083 1084 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet; 1085 1086 // The register sets used for matching. 1087 RegisterSetSet RegisterSets; 1088 1089 // Gather the defined sets. 1090 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it = 1091 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) 1092 RegisterSets.insert(RegisterSet( 1093 (*it)->getOrder().begin(), (*it)->getOrder().end())); 1094 1095 // Add any required singleton sets. 1096 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(), 1097 ie = SingletonRegisters.end(); it != ie; ++it) { 1098 Record *Rec = *it; 1099 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1)); 1100 } 1101 1102 // Introduce derived sets where necessary (when a register does not determine 1103 // a unique register set class), and build the mapping of registers to the set 1104 // they should classify to. 1105 std::map<Record*, RegisterSet> RegisterMap; 1106 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(), 1107 ie = Registers.end(); it != ie; ++it) { 1108 const CodeGenRegister &CGR = **it; 1109 // Compute the intersection of all sets containing this register. 1110 RegisterSet ContainingSet; 1111 1112 for (RegisterSetSet::iterator it = RegisterSets.begin(), 1113 ie = RegisterSets.end(); it != ie; ++it) { 1114 if (!it->count(CGR.TheDef)) 1115 continue; 1116 1117 if (ContainingSet.empty()) { 1118 ContainingSet = *it; 1119 continue; 1120 } 1121 1122 RegisterSet Tmp; 1123 std::swap(Tmp, ContainingSet); 1124 std::insert_iterator<RegisterSet> II(ContainingSet, 1125 ContainingSet.begin()); 1126 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II, 1127 LessRecordByID()); 1128 } 1129 1130 if (!ContainingSet.empty()) { 1131 RegisterSets.insert(ContainingSet); 1132 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet)); 1133 } 1134 } 1135 1136 // Construct the register classes. 1137 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses; 1138 unsigned Index = 0; 1139 for (RegisterSetSet::iterator it = RegisterSets.begin(), 1140 ie = RegisterSets.end(); it != ie; ++it, ++Index) { 1141 ClassInfo *CI = new ClassInfo(); 1142 CI->Kind = ClassInfo::RegisterClass0 + Index; 1143 CI->ClassName = "Reg" + utostr(Index); 1144 CI->Name = "MCK_Reg" + utostr(Index); 1145 CI->ValueName = ""; 1146 CI->PredicateMethod = ""; // unused 1147 CI->RenderMethod = "addRegOperands"; 1148 CI->Registers = *it; 1149 // FIXME: diagnostic type. 1150 CI->DiagnosticType = ""; 1151 Classes.push_back(CI); 1152 RegisterSetClasses.insert(std::make_pair(*it, CI)); 1153 } 1154 1155 // Find the superclasses; we could compute only the subgroup lattice edges, 1156 // but there isn't really a point. 1157 for (RegisterSetSet::iterator it = RegisterSets.begin(), 1158 ie = RegisterSets.end(); it != ie; ++it) { 1159 ClassInfo *CI = RegisterSetClasses[*it]; 1160 for (RegisterSetSet::iterator it2 = RegisterSets.begin(), 1161 ie2 = RegisterSets.end(); it2 != ie2; ++it2) 1162 if (*it != *it2 && 1163 std::includes(it2->begin(), it2->end(), it->begin(), it->end(), 1164 LessRecordByID())) 1165 CI->SuperClasses.push_back(RegisterSetClasses[*it2]); 1166 } 1167 1168 // Name the register classes which correspond to a user defined RegisterClass. 1169 for (ArrayRef<CodeGenRegisterClass*>::const_iterator 1170 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) { 1171 const CodeGenRegisterClass &RC = **it; 1172 // Def will be NULL for non-user defined register classes. 1173 Record *Def = RC.getDef(); 1174 if (!Def) 1175 continue; 1176 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(), 1177 RC.getOrder().end())]; 1178 if (CI->ValueName.empty()) { 1179 CI->ClassName = RC.getName(); 1180 CI->Name = "MCK_" + RC.getName(); 1181 CI->ValueName = RC.getName(); 1182 } else 1183 CI->ValueName = CI->ValueName + "," + RC.getName(); 1184 1185 RegisterClassClasses.insert(std::make_pair(Def, CI)); 1186 } 1187 1188 // Populate the map for individual registers. 1189 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(), 1190 ie = RegisterMap.end(); it != ie; ++it) 1191 RegisterClasses[it->first] = RegisterSetClasses[it->second]; 1192 1193 // Name the register classes which correspond to singleton registers. 1194 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(), 1195 ie = SingletonRegisters.end(); it != ie; ++it) { 1196 Record *Rec = *it; 1197 ClassInfo *CI = RegisterClasses[Rec]; 1198 assert(CI && "Missing singleton register class info!"); 1199 1200 if (CI->ValueName.empty()) { 1201 CI->ClassName = Rec->getName(); 1202 CI->Name = "MCK_" + Rec->getName(); 1203 CI->ValueName = Rec->getName(); 1204 } else 1205 CI->ValueName = CI->ValueName + "," + Rec->getName(); 1206 } 1207 } 1208 1209 void AsmMatcherInfo::buildOperandClasses() { 1210 std::vector<Record*> AsmOperands = 1211 Records.getAllDerivedDefinitions("AsmOperandClass"); 1212 1213 // Pre-populate AsmOperandClasses map. 1214 for (std::vector<Record*>::iterator it = AsmOperands.begin(), 1215 ie = AsmOperands.end(); it != ie; ++it) 1216 AsmOperandClasses[*it] = new ClassInfo(); 1217 1218 unsigned Index = 0; 1219 for (std::vector<Record*>::iterator it = AsmOperands.begin(), 1220 ie = AsmOperands.end(); it != ie; ++it, ++Index) { 1221 ClassInfo *CI = AsmOperandClasses[*it]; 1222 CI->Kind = ClassInfo::UserClass0 + Index; 1223 1224 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses"); 1225 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) { 1226 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i)); 1227 if (!DI) { 1228 PrintError((*it)->getLoc(), "Invalid super class reference!"); 1229 continue; 1230 } 1231 1232 ClassInfo *SC = AsmOperandClasses[DI->getDef()]; 1233 if (!SC) 1234 PrintError((*it)->getLoc(), "Invalid super class reference!"); 1235 else 1236 CI->SuperClasses.push_back(SC); 1237 } 1238 CI->ClassName = (*it)->getValueAsString("Name"); 1239 CI->Name = "MCK_" + CI->ClassName; 1240 CI->ValueName = (*it)->getName(); 1241 1242 // Get or construct the predicate method name. 1243 Init *PMName = (*it)->getValueInit("PredicateMethod"); 1244 if (StringInit *SI = dyn_cast<StringInit>(PMName)) { 1245 CI->PredicateMethod = SI->getValue(); 1246 } else { 1247 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!"); 1248 CI->PredicateMethod = "is" + CI->ClassName; 1249 } 1250 1251 // Get or construct the render method name. 1252 Init *RMName = (*it)->getValueInit("RenderMethod"); 1253 if (StringInit *SI = dyn_cast<StringInit>(RMName)) { 1254 CI->RenderMethod = SI->getValue(); 1255 } else { 1256 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!"); 1257 CI->RenderMethod = "add" + CI->ClassName + "Operands"; 1258 } 1259 1260 // Get the parse method name or leave it as empty. 1261 Init *PRMName = (*it)->getValueInit("ParserMethod"); 1262 if (StringInit *SI = dyn_cast<StringInit>(PRMName)) 1263 CI->ParserMethod = SI->getValue(); 1264 1265 // Get the diagnostic type or leave it as empty. 1266 // Get the parse method name or leave it as empty. 1267 Init *DiagnosticType = (*it)->getValueInit("DiagnosticType"); 1268 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType)) 1269 CI->DiagnosticType = SI->getValue(); 1270 1271 AsmOperandClasses[*it] = CI; 1272 Classes.push_back(CI); 1273 } 1274 } 1275 1276 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, 1277 CodeGenTarget &target, 1278 RecordKeeper &records) 1279 : Records(records), AsmParser(asmParser), Target(target) { 1280 } 1281 1282 /// buildOperandMatchInfo - Build the necessary information to handle user 1283 /// defined operand parsing methods. 1284 void AsmMatcherInfo::buildOperandMatchInfo() { 1285 1286 /// Map containing a mask with all operands indices that can be found for 1287 /// that class inside a instruction. 1288 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy; 1289 OpClassMaskTy OpClassMask; 1290 1291 for (std::vector<MatchableInfo*>::const_iterator it = 1292 Matchables.begin(), ie = Matchables.end(); 1293 it != ie; ++it) { 1294 MatchableInfo &II = **it; 1295 OpClassMask.clear(); 1296 1297 // Keep track of all operands of this instructions which belong to the 1298 // same class. 1299 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { 1300 MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; 1301 if (Op.Class->ParserMethod.empty()) 1302 continue; 1303 unsigned &OperandMask = OpClassMask[Op.Class]; 1304 OperandMask |= (1 << i); 1305 } 1306 1307 // Generate operand match info for each mnemonic/operand class pair. 1308 for (OpClassMaskTy::iterator iit = OpClassMask.begin(), 1309 iie = OpClassMask.end(); iit != iie; ++iit) { 1310 unsigned OpMask = iit->second; 1311 ClassInfo *CI = iit->first; 1312 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask)); 1313 } 1314 } 1315 } 1316 1317 void AsmMatcherInfo::buildInfo() { 1318 // Build information about all of the AssemblerPredicates. 1319 std::vector<Record*> AllPredicates = 1320 Records.getAllDerivedDefinitions("Predicate"); 1321 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) { 1322 Record *Pred = AllPredicates[i]; 1323 // Ignore predicates that are not intended for the assembler. 1324 if (!Pred->getValueAsBit("AssemblerMatcherPredicate")) 1325 continue; 1326 1327 if (Pred->getName().empty()) 1328 PrintFatalError(Pred->getLoc(), "Predicate has no name!"); 1329 1330 unsigned FeatureNo = SubtargetFeatures.size(); 1331 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo); 1332 DEBUG(SubtargetFeatures[Pred]->dump()); 1333 assert(FeatureNo < 32 && "Too many subtarget features!"); 1334 } 1335 1336 // Parse the instructions; we need to do this first so that we can gather the 1337 // singleton register classes. 1338 SmallPtrSet<Record*, 16> SingletonRegisters; 1339 unsigned VariantCount = Target.getAsmParserVariantCount(); 1340 for (unsigned VC = 0; VC != VariantCount; ++VC) { 1341 Record *AsmVariant = Target.getAsmParserVariant(VC); 1342 std::string CommentDelimiter = 1343 AsmVariant->getValueAsString("CommentDelimiter"); 1344 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix"); 1345 int AsmVariantNo = AsmVariant->getValueAsInt("Variant"); 1346 1347 for (CodeGenTarget::inst_iterator I = Target.inst_begin(), 1348 E = Target.inst_end(); I != E; ++I) { 1349 const CodeGenInstruction &CGI = **I; 1350 1351 // If the tblgen -match-prefix option is specified (for tblgen hackers), 1352 // filter the set of instructions we consider. 1353 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix)) 1354 continue; 1355 1356 // Ignore "codegen only" instructions. 1357 if (CGI.TheDef->getValueAsBit("isCodeGenOnly")) 1358 continue; 1359 1360 std::unique_ptr<MatchableInfo> II(new MatchableInfo(CGI)); 1361 1362 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix); 1363 1364 // Ignore instructions which shouldn't be matched and diagnose invalid 1365 // instruction definitions with an error. 1366 if (!II->validate(CommentDelimiter, true)) 1367 continue; 1368 1369 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases. 1370 // 1371 // FIXME: This is a total hack. 1372 if (StringRef(II->TheDef->getName()).startswith("Int_") || 1373 StringRef(II->TheDef->getName()).endswith("_Int")) 1374 continue; 1375 1376 Matchables.push_back(II.release()); 1377 } 1378 1379 // Parse all of the InstAlias definitions and stick them in the list of 1380 // matchables. 1381 std::vector<Record*> AllInstAliases = 1382 Records.getAllDerivedDefinitions("InstAlias"); 1383 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) { 1384 CodeGenInstAlias *Alias = 1385 new CodeGenInstAlias(AllInstAliases[i], AsmVariantNo, Target); 1386 1387 // If the tblgen -match-prefix option is specified (for tblgen hackers), 1388 // filter the set of instruction aliases we consider, based on the target 1389 // instruction. 1390 if (!StringRef(Alias->ResultInst->TheDef->getName()) 1391 .startswith( MatchPrefix)) 1392 continue; 1393 1394 std::unique_ptr<MatchableInfo> II(new MatchableInfo(Alias)); 1395 1396 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix); 1397 1398 // Validate the alias definitions. 1399 II->validate(CommentDelimiter, false); 1400 1401 Matchables.push_back(II.release()); 1402 } 1403 } 1404 1405 // Build info for the register classes. 1406 buildRegisterClasses(SingletonRegisters); 1407 1408 // Build info for the user defined assembly operand classes. 1409 buildOperandClasses(); 1410 1411 // Build the information about matchables, now that we have fully formed 1412 // classes. 1413 std::vector<MatchableInfo*> NewMatchables; 1414 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(), 1415 ie = Matchables.end(); it != ie; ++it) { 1416 MatchableInfo *II = *it; 1417 1418 // Parse the tokens after the mnemonic. 1419 // Note: buildInstructionOperandReference may insert new AsmOperands, so 1420 // don't precompute the loop bound. 1421 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) { 1422 MatchableInfo::AsmOperand &Op = II->AsmOperands[i]; 1423 StringRef Token = Op.Token; 1424 1425 // Check for singleton registers. 1426 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) { 1427 Op.Class = RegisterClasses[RegRecord]; 1428 assert(Op.Class && Op.Class->Registers.size() == 1 && 1429 "Unexpected class for singleton register"); 1430 continue; 1431 } 1432 1433 // Check for simple tokens. 1434 if (Token[0] != '$') { 1435 Op.Class = getTokenClass(Token); 1436 continue; 1437 } 1438 1439 if (Token.size() > 1 && isdigit(Token[1])) { 1440 Op.Class = getTokenClass(Token); 1441 continue; 1442 } 1443 1444 // Otherwise this is an operand reference. 1445 StringRef OperandName; 1446 if (Token[1] == '{') 1447 OperandName = Token.substr(2, Token.size() - 3); 1448 else 1449 OperandName = Token.substr(1); 1450 1451 if (II->DefRec.is<const CodeGenInstruction*>()) 1452 buildInstructionOperandReference(II, OperandName, i); 1453 else 1454 buildAliasOperandReference(II, OperandName, Op); 1455 } 1456 1457 if (II->DefRec.is<const CodeGenInstruction*>()) { 1458 II->buildInstructionResultOperands(); 1459 // If the instruction has a two-operand alias, build up the 1460 // matchable here. We'll add them in bulk at the end to avoid 1461 // confusing this loop. 1462 std::string Constraint = 1463 II->TheDef->getValueAsString("TwoOperandAliasConstraint"); 1464 if (Constraint != "") { 1465 // Start by making a copy of the original matchable. 1466 std::unique_ptr<MatchableInfo> AliasII(new MatchableInfo(*II)); 1467 1468 // Adjust it to be a two-operand alias. 1469 AliasII->formTwoOperandAlias(Constraint); 1470 1471 // Add the alias to the matchables list. 1472 NewMatchables.push_back(AliasII.release()); 1473 } 1474 } else 1475 II->buildAliasResultOperands(); 1476 } 1477 if (!NewMatchables.empty()) 1478 Matchables.insert(Matchables.end(), NewMatchables.begin(), 1479 NewMatchables.end()); 1480 1481 // Process token alias definitions and set up the associated superclass 1482 // information. 1483 std::vector<Record*> AllTokenAliases = 1484 Records.getAllDerivedDefinitions("TokenAlias"); 1485 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) { 1486 Record *Rec = AllTokenAliases[i]; 1487 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken")); 1488 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken")); 1489 if (FromClass == ToClass) 1490 PrintFatalError(Rec->getLoc(), 1491 "error: Destination value identical to source value."); 1492 FromClass->SuperClasses.push_back(ToClass); 1493 } 1494 1495 // Reorder classes so that classes precede super classes. 1496 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>()); 1497 } 1498 1499 /// buildInstructionOperandReference - The specified operand is a reference to a 1500 /// named operand such as $src. Resolve the Class and OperandInfo pointers. 1501 void AsmMatcherInfo:: 1502 buildInstructionOperandReference(MatchableInfo *II, 1503 StringRef OperandName, 1504 unsigned AsmOpIdx) { 1505 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>(); 1506 const CGIOperandList &Operands = CGI.Operands; 1507 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx]; 1508 1509 // Map this token to an operand. 1510 unsigned Idx; 1511 if (!Operands.hasOperandNamed(OperandName, Idx)) 1512 PrintFatalError(II->TheDef->getLoc(), 1513 "error: unable to find operand: '" + OperandName + "'"); 1514 1515 // If the instruction operand has multiple suboperands, but the parser 1516 // match class for the asm operand is still the default "ImmAsmOperand", 1517 // then handle each suboperand separately. 1518 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) { 1519 Record *Rec = Operands[Idx].Rec; 1520 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!"); 1521 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass"); 1522 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") { 1523 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands. 1524 StringRef Token = Op->Token; // save this in case Op gets moved 1525 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) { 1526 MatchableInfo::AsmOperand NewAsmOp(Token); 1527 NewAsmOp.SubOpIdx = SI; 1528 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp); 1529 } 1530 // Replace Op with first suboperand. 1531 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved 1532 Op->SubOpIdx = 0; 1533 } 1534 } 1535 1536 // Set up the operand class. 1537 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx); 1538 1539 // If the named operand is tied, canonicalize it to the untied operand. 1540 // For example, something like: 1541 // (outs GPR:$dst), (ins GPR:$src) 1542 // with an asmstring of 1543 // "inc $src" 1544 // we want to canonicalize to: 1545 // "inc $dst" 1546 // so that we know how to provide the $dst operand when filling in the result. 1547 int OITied = -1; 1548 if (Operands[Idx].MINumOperands == 1) 1549 OITied = Operands[Idx].getTiedRegister(); 1550 if (OITied != -1) { 1551 // The tied operand index is an MIOperand index, find the operand that 1552 // contains it. 1553 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied); 1554 OperandName = Operands[Idx.first].Name; 1555 Op->SubOpIdx = Idx.second; 1556 } 1557 1558 Op->SrcOpName = OperandName; 1559 } 1560 1561 /// buildAliasOperandReference - When parsing an operand reference out of the 1562 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the 1563 /// operand reference is by looking it up in the result pattern definition. 1564 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II, 1565 StringRef OperandName, 1566 MatchableInfo::AsmOperand &Op) { 1567 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>(); 1568 1569 // Set up the operand class. 1570 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i) 1571 if (CGA.ResultOperands[i].isRecord() && 1572 CGA.ResultOperands[i].getName() == OperandName) { 1573 // It's safe to go with the first one we find, because CodeGenInstAlias 1574 // validates that all operands with the same name have the same record. 1575 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second; 1576 // Use the match class from the Alias definition, not the 1577 // destination instruction, as we may have an immediate that's 1578 // being munged by the match class. 1579 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(), 1580 Op.SubOpIdx); 1581 Op.SrcOpName = OperandName; 1582 return; 1583 } 1584 1585 PrintFatalError(II->TheDef->getLoc(), 1586 "error: unable to find operand: '" + OperandName + "'"); 1587 } 1588 1589 void MatchableInfo::buildInstructionResultOperands() { 1590 const CodeGenInstruction *ResultInst = getResultInst(); 1591 1592 // Loop over all operands of the result instruction, determining how to 1593 // populate them. 1594 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { 1595 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i]; 1596 1597 // If this is a tied operand, just copy from the previously handled operand. 1598 int TiedOp = -1; 1599 if (OpInfo.MINumOperands == 1) 1600 TiedOp = OpInfo.getTiedRegister(); 1601 if (TiedOp != -1) { 1602 ResOperands.push_back(ResOperand::getTiedOp(TiedOp)); 1603 continue; 1604 } 1605 1606 // Find out what operand from the asmparser this MCInst operand comes from. 1607 int SrcOperand = findAsmOperandNamed(OpInfo.Name); 1608 if (OpInfo.Name.empty() || SrcOperand == -1) { 1609 // This may happen for operands that are tied to a suboperand of a 1610 // complex operand. Simply use a dummy value here; nobody should 1611 // use this operand slot. 1612 // FIXME: The long term goal is for the MCOperand list to not contain 1613 // tied operands at all. 1614 ResOperands.push_back(ResOperand::getImmOp(0)); 1615 continue; 1616 } 1617 1618 // Check if the one AsmOperand populates the entire operand. 1619 unsigned NumOperands = OpInfo.MINumOperands; 1620 if (AsmOperands[SrcOperand].SubOpIdx == -1) { 1621 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands)); 1622 continue; 1623 } 1624 1625 // Add a separate ResOperand for each suboperand. 1626 for (unsigned AI = 0; AI < NumOperands; ++AI) { 1627 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI && 1628 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name && 1629 "unexpected AsmOperands for suboperands"); 1630 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1)); 1631 } 1632 } 1633 } 1634 1635 void MatchableInfo::buildAliasResultOperands() { 1636 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>(); 1637 const CodeGenInstruction *ResultInst = getResultInst(); 1638 1639 // Loop over all operands of the result instruction, determining how to 1640 // populate them. 1641 unsigned AliasOpNo = 0; 1642 unsigned LastOpNo = CGA.ResultInstOperandIndex.size(); 1643 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { 1644 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i]; 1645 1646 // If this is a tied operand, just copy from the previously handled operand. 1647 int TiedOp = -1; 1648 if (OpInfo->MINumOperands == 1) 1649 TiedOp = OpInfo->getTiedRegister(); 1650 if (TiedOp != -1) { 1651 ResOperands.push_back(ResOperand::getTiedOp(TiedOp)); 1652 continue; 1653 } 1654 1655 // Handle all the suboperands for this operand. 1656 const std::string &OpName = OpInfo->Name; 1657 for ( ; AliasOpNo < LastOpNo && 1658 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) { 1659 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second; 1660 1661 // Find out what operand from the asmparser that this MCInst operand 1662 // comes from. 1663 switch (CGA.ResultOperands[AliasOpNo].Kind) { 1664 case CodeGenInstAlias::ResultOperand::K_Record: { 1665 StringRef Name = CGA.ResultOperands[AliasOpNo].getName(); 1666 int SrcOperand = findAsmOperand(Name, SubIdx); 1667 if (SrcOperand == -1) 1668 PrintFatalError(TheDef->getLoc(), "Instruction '" + 1669 TheDef->getName() + "' has operand '" + OpName + 1670 "' that doesn't appear in asm string!"); 1671 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1); 1672 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, 1673 NumOperands)); 1674 break; 1675 } 1676 case CodeGenInstAlias::ResultOperand::K_Imm: { 1677 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm(); 1678 ResOperands.push_back(ResOperand::getImmOp(ImmVal)); 1679 break; 1680 } 1681 case CodeGenInstAlias::ResultOperand::K_Reg: { 1682 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister(); 1683 ResOperands.push_back(ResOperand::getRegOp(Reg)); 1684 break; 1685 } 1686 } 1687 } 1688 } 1689 } 1690 1691 static unsigned getConverterOperandID(const std::string &Name, 1692 SetVector<std::string> &Table, 1693 bool &IsNew) { 1694 IsNew = Table.insert(Name); 1695 1696 unsigned ID = IsNew ? Table.size() - 1 : 1697 std::find(Table.begin(), Table.end(), Name) - Table.begin(); 1698 1699 assert(ID < Table.size()); 1700 1701 return ID; 1702 } 1703 1704 1705 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName, 1706 std::vector<MatchableInfo*> &Infos, 1707 raw_ostream &OS) { 1708 SetVector<std::string> OperandConversionKinds; 1709 SetVector<std::string> InstructionConversionKinds; 1710 std::vector<std::vector<uint8_t> > ConversionTable; 1711 size_t MaxRowLength = 2; // minimum is custom converter plus terminator. 1712 1713 // TargetOperandClass - This is the target's operand class, like X86Operand. 1714 std::string TargetOperandClass = Target.getName() + "Operand"; 1715 1716 // Write the convert function to a separate stream, so we can drop it after 1717 // the enum. We'll build up the conversion handlers for the individual 1718 // operand types opportunistically as we encounter them. 1719 std::string ConvertFnBody; 1720 raw_string_ostream CvtOS(ConvertFnBody); 1721 // Start the unified conversion function. 1722 CvtOS << "void " << Target.getName() << ClassName << "::\n" 1723 << "convertToMCInst(unsigned Kind, MCInst &Inst, " 1724 << "unsigned Opcode,\n" 1725 << " const OperandVector" 1726 << " &Operands) {\n" 1727 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n" 1728 << " const uint8_t *Converter = ConversionTable[Kind];\n" 1729 << " Inst.setOpcode(Opcode);\n" 1730 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n" 1731 << " switch (*p) {\n" 1732 << " default: llvm_unreachable(\"invalid conversion entry!\");\n" 1733 << " case CVT_Reg:\n" 1734 << " static_cast<" << TargetOperandClass 1735 << "&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);\n" 1736 << " break;\n" 1737 << " case CVT_Tied:\n" 1738 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n" 1739 << " break;\n"; 1740 1741 std::string OperandFnBody; 1742 raw_string_ostream OpOS(OperandFnBody); 1743 // Start the operand number lookup function. 1744 OpOS << "void " << Target.getName() << ClassName << "::\n" 1745 << "convertToMapAndConstraints(unsigned Kind,\n"; 1746 OpOS.indent(27); 1747 OpOS << "const OperandVector &Operands) {\n" 1748 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n" 1749 << " unsigned NumMCOperands = 0;\n" 1750 << " const uint8_t *Converter = ConversionTable[Kind];\n" 1751 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n" 1752 << " switch (*p) {\n" 1753 << " default: llvm_unreachable(\"invalid conversion entry!\");\n" 1754 << " case CVT_Reg:\n" 1755 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n" 1756 << " Operands[*(p + 1)]->setConstraint(\"r\");\n" 1757 << " ++NumMCOperands;\n" 1758 << " break;\n" 1759 << " case CVT_Tied:\n" 1760 << " ++NumMCOperands;\n" 1761 << " break;\n"; 1762 1763 // Pre-populate the operand conversion kinds with the standard always 1764 // available entries. 1765 OperandConversionKinds.insert("CVT_Done"); 1766 OperandConversionKinds.insert("CVT_Reg"); 1767 OperandConversionKinds.insert("CVT_Tied"); 1768 enum { CVT_Done, CVT_Reg, CVT_Tied }; 1769 1770 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(), 1771 ie = Infos.end(); it != ie; ++it) { 1772 MatchableInfo &II = **it; 1773 1774 // Check if we have a custom match function. 1775 std::string AsmMatchConverter = 1776 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter"); 1777 if (!AsmMatchConverter.empty()) { 1778 std::string Signature = "ConvertCustom_" + AsmMatchConverter; 1779 II.ConversionFnKind = Signature; 1780 1781 // Check if we have already generated this signature. 1782 if (!InstructionConversionKinds.insert(Signature)) 1783 continue; 1784 1785 // Remember this converter for the kind enum. 1786 unsigned KindID = OperandConversionKinds.size(); 1787 OperandConversionKinds.insert("CVT_" + 1788 getEnumNameForToken(AsmMatchConverter)); 1789 1790 // Add the converter row for this instruction. 1791 ConversionTable.push_back(std::vector<uint8_t>()); 1792 ConversionTable.back().push_back(KindID); 1793 ConversionTable.back().push_back(CVT_Done); 1794 1795 // Add the handler to the conversion driver function. 1796 CvtOS << " case CVT_" 1797 << getEnumNameForToken(AsmMatchConverter) << ":\n" 1798 << " " << AsmMatchConverter << "(Inst, Operands);\n" 1799 << " break;\n"; 1800 1801 // FIXME: Handle the operand number lookup for custom match functions. 1802 continue; 1803 } 1804 1805 // Build the conversion function signature. 1806 std::string Signature = "Convert"; 1807 1808 std::vector<uint8_t> ConversionRow; 1809 1810 // Compute the convert enum and the case body. 1811 MaxRowLength = std::max(MaxRowLength, II.ResOperands.size()*2 + 1 ); 1812 1813 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) { 1814 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i]; 1815 1816 // Generate code to populate each result operand. 1817 switch (OpInfo.Kind) { 1818 case MatchableInfo::ResOperand::RenderAsmOperand: { 1819 // This comes from something we parsed. 1820 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum]; 1821 1822 // Registers are always converted the same, don't duplicate the 1823 // conversion function based on them. 1824 Signature += "__"; 1825 std::string Class; 1826 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName; 1827 Signature += Class; 1828 Signature += utostr(OpInfo.MINumOperands); 1829 Signature += "_" + itostr(OpInfo.AsmOperandNum); 1830 1831 // Add the conversion kind, if necessary, and get the associated ID 1832 // the index of its entry in the vector). 1833 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" : 1834 Op.Class->RenderMethod); 1835 Name = getEnumNameForToken(Name); 1836 1837 bool IsNewConverter = false; 1838 unsigned ID = getConverterOperandID(Name, OperandConversionKinds, 1839 IsNewConverter); 1840 1841 // Add the operand entry to the instruction kind conversion row. 1842 ConversionRow.push_back(ID); 1843 ConversionRow.push_back(OpInfo.AsmOperandNum + 1); 1844 1845 if (!IsNewConverter) 1846 break; 1847 1848 // This is a new operand kind. Add a handler for it to the 1849 // converter driver. 1850 CvtOS << " case " << Name << ":\n" 1851 << " static_cast<" << TargetOperandClass 1852 << "&>(*Operands[*(p + 1)])." << Op.Class->RenderMethod 1853 << "(Inst, " << OpInfo.MINumOperands << ");\n" 1854 << " break;\n"; 1855 1856 // Add a handler for the operand number lookup. 1857 OpOS << " case " << Name << ":\n" 1858 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"; 1859 1860 if (Op.Class->isRegisterClass()) 1861 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n"; 1862 else 1863 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n"; 1864 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n" 1865 << " break;\n"; 1866 break; 1867 } 1868 case MatchableInfo::ResOperand::TiedOperand: { 1869 // If this operand is tied to a previous one, just copy the MCInst 1870 // operand from the earlier one.We can only tie single MCOperand values. 1871 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand"); 1872 unsigned TiedOp = OpInfo.TiedOperandNum; 1873 assert(i > TiedOp && "Tied operand precedes its target!"); 1874 Signature += "__Tie" + utostr(TiedOp); 1875 ConversionRow.push_back(CVT_Tied); 1876 ConversionRow.push_back(TiedOp); 1877 break; 1878 } 1879 case MatchableInfo::ResOperand::ImmOperand: { 1880 int64_t Val = OpInfo.ImmVal; 1881 std::string Ty = "imm_" + itostr(Val); 1882 Signature += "__" + Ty; 1883 1884 std::string Name = "CVT_" + Ty; 1885 bool IsNewConverter = false; 1886 unsigned ID = getConverterOperandID(Name, OperandConversionKinds, 1887 IsNewConverter); 1888 // Add the operand entry to the instruction kind conversion row. 1889 ConversionRow.push_back(ID); 1890 ConversionRow.push_back(0); 1891 1892 if (!IsNewConverter) 1893 break; 1894 1895 CvtOS << " case " << Name << ":\n" 1896 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n" 1897 << " break;\n"; 1898 1899 OpOS << " case " << Name << ":\n" 1900 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n" 1901 << " Operands[*(p + 1)]->setConstraint(\"\");\n" 1902 << " ++NumMCOperands;\n" 1903 << " break;\n"; 1904 break; 1905 } 1906 case MatchableInfo::ResOperand::RegOperand: { 1907 std::string Reg, Name; 1908 if (!OpInfo.Register) { 1909 Name = "reg0"; 1910 Reg = "0"; 1911 } else { 1912 Reg = getQualifiedName(OpInfo.Register); 1913 Name = "reg" + OpInfo.Register->getName(); 1914 } 1915 Signature += "__" + Name; 1916 Name = "CVT_" + Name; 1917 bool IsNewConverter = false; 1918 unsigned ID = getConverterOperandID(Name, OperandConversionKinds, 1919 IsNewConverter); 1920 // Add the operand entry to the instruction kind conversion row. 1921 ConversionRow.push_back(ID); 1922 ConversionRow.push_back(0); 1923 1924 if (!IsNewConverter) 1925 break; 1926 CvtOS << " case " << Name << ":\n" 1927 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n" 1928 << " break;\n"; 1929 1930 OpOS << " case " << Name << ":\n" 1931 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n" 1932 << " Operands[*(p + 1)]->setConstraint(\"m\");\n" 1933 << " ++NumMCOperands;\n" 1934 << " break;\n"; 1935 } 1936 } 1937 } 1938 1939 // If there were no operands, add to the signature to that effect 1940 if (Signature == "Convert") 1941 Signature += "_NoOperands"; 1942 1943 II.ConversionFnKind = Signature; 1944 1945 // Save the signature. If we already have it, don't add a new row 1946 // to the table. 1947 if (!InstructionConversionKinds.insert(Signature)) 1948 continue; 1949 1950 // Add the row to the table. 1951 ConversionTable.push_back(ConversionRow); 1952 } 1953 1954 // Finish up the converter driver function. 1955 CvtOS << " }\n }\n}\n\n"; 1956 1957 // Finish up the operand number lookup function. 1958 OpOS << " }\n }\n}\n\n"; 1959 1960 OS << "namespace {\n"; 1961 1962 // Output the operand conversion kind enum. 1963 OS << "enum OperatorConversionKind {\n"; 1964 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i) 1965 OS << " " << OperandConversionKinds[i] << ",\n"; 1966 OS << " CVT_NUM_CONVERTERS\n"; 1967 OS << "};\n\n"; 1968 1969 // Output the instruction conversion kind enum. 1970 OS << "enum InstructionConversionKind {\n"; 1971 for (SetVector<std::string>::const_iterator 1972 i = InstructionConversionKinds.begin(), 1973 e = InstructionConversionKinds.end(); i != e; ++i) 1974 OS << " " << *i << ",\n"; 1975 OS << " CVT_NUM_SIGNATURES\n"; 1976 OS << "};\n\n"; 1977 1978 1979 OS << "} // end anonymous namespace\n\n"; 1980 1981 // Output the conversion table. 1982 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][" 1983 << MaxRowLength << "] = {\n"; 1984 1985 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) { 1986 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!"); 1987 OS << " // " << InstructionConversionKinds[Row] << "\n"; 1988 OS << " { "; 1989 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2) 1990 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", " 1991 << (unsigned)(ConversionTable[Row][i + 1]) << ", "; 1992 OS << "CVT_Done },\n"; 1993 } 1994 1995 OS << "};\n\n"; 1996 1997 // Spit out the conversion driver function. 1998 OS << CvtOS.str(); 1999 2000 // Spit out the operand number lookup function. 2001 OS << OpOS.str(); 2002 } 2003 2004 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds. 2005 static void emitMatchClassEnumeration(CodeGenTarget &Target, 2006 std::vector<ClassInfo*> &Infos, 2007 raw_ostream &OS) { 2008 OS << "namespace {\n\n"; 2009 2010 OS << "/// MatchClassKind - The kinds of classes which participate in\n" 2011 << "/// instruction matching.\n"; 2012 OS << "enum MatchClassKind {\n"; 2013 OS << " InvalidMatchClass = 0,\n"; 2014 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 2015 ie = Infos.end(); it != ie; ++it) { 2016 ClassInfo &CI = **it; 2017 OS << " " << CI.Name << ", // "; 2018 if (CI.Kind == ClassInfo::Token) { 2019 OS << "'" << CI.ValueName << "'\n"; 2020 } else if (CI.isRegisterClass()) { 2021 if (!CI.ValueName.empty()) 2022 OS << "register class '" << CI.ValueName << "'\n"; 2023 else 2024 OS << "derived register class\n"; 2025 } else { 2026 OS << "user defined class '" << CI.ValueName << "'\n"; 2027 } 2028 } 2029 OS << " NumMatchClassKinds\n"; 2030 OS << "};\n\n"; 2031 2032 OS << "}\n\n"; 2033 } 2034 2035 /// emitValidateOperandClass - Emit the function to validate an operand class. 2036 static void emitValidateOperandClass(AsmMatcherInfo &Info, 2037 raw_ostream &OS) { 2038 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, " 2039 << "MatchClassKind Kind) {\n"; 2040 OS << " " << Info.Target.getName() << "Operand &Operand = (" 2041 << Info.Target.getName() << "Operand&)GOp;\n"; 2042 2043 // The InvalidMatchClass is not to match any operand. 2044 OS << " if (Kind == InvalidMatchClass)\n"; 2045 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n"; 2046 2047 // Check for Token operands first. 2048 // FIXME: Use a more specific diagnostic type. 2049 OS << " if (Operand.isToken())\n"; 2050 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n" 2051 << " MCTargetAsmParser::Match_Success :\n" 2052 << " MCTargetAsmParser::Match_InvalidOperand;\n\n"; 2053 2054 // Check the user classes. We don't care what order since we're only 2055 // actually matching against one of them. 2056 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(), 2057 ie = Info.Classes.end(); it != ie; ++it) { 2058 ClassInfo &CI = **it; 2059 2060 if (!CI.isUserClass()) 2061 continue; 2062 2063 OS << " // '" << CI.ClassName << "' class\n"; 2064 OS << " if (Kind == " << CI.Name << ") {\n"; 2065 OS << " if (Operand." << CI.PredicateMethod << "())\n"; 2066 OS << " return MCTargetAsmParser::Match_Success;\n"; 2067 if (!CI.DiagnosticType.empty()) 2068 OS << " return " << Info.Target.getName() << "AsmParser::Match_" 2069 << CI.DiagnosticType << ";\n"; 2070 OS << " }\n\n"; 2071 } 2072 2073 // Check for register operands, including sub-classes. 2074 OS << " if (Operand.isReg()) {\n"; 2075 OS << " MatchClassKind OpKind;\n"; 2076 OS << " switch (Operand.getReg()) {\n"; 2077 OS << " default: OpKind = InvalidMatchClass; break;\n"; 2078 for (AsmMatcherInfo::RegisterClassesTy::iterator 2079 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end(); 2080 it != ie; ++it) 2081 OS << " case " << Info.Target.getName() << "::" 2082 << it->first->getName() << ": OpKind = " << it->second->Name 2083 << "; break;\n"; 2084 OS << " }\n"; 2085 OS << " return isSubclass(OpKind, Kind) ? " 2086 << "MCTargetAsmParser::Match_Success :\n " 2087 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n"; 2088 2089 // Generic fallthrough match failure case for operands that don't have 2090 // specialized diagnostic types. 2091 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n"; 2092 OS << "}\n\n"; 2093 } 2094 2095 /// emitIsSubclass - Emit the subclass predicate function. 2096 static void emitIsSubclass(CodeGenTarget &Target, 2097 std::vector<ClassInfo*> &Infos, 2098 raw_ostream &OS) { 2099 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n"; 2100 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n"; 2101 OS << " if (A == B)\n"; 2102 OS << " return true;\n\n"; 2103 2104 std::string OStr; 2105 raw_string_ostream SS(OStr); 2106 unsigned Count = 0; 2107 SS << " switch (A) {\n"; 2108 SS << " default:\n"; 2109 SS << " return false;\n"; 2110 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 2111 ie = Infos.end(); it != ie; ++it) { 2112 ClassInfo &A = **it; 2113 2114 std::vector<StringRef> SuperClasses; 2115 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 2116 ie = Infos.end(); it != ie; ++it) { 2117 ClassInfo &B = **it; 2118 2119 if (&A != &B && A.isSubsetOf(B)) 2120 SuperClasses.push_back(B.Name); 2121 } 2122 2123 if (SuperClasses.empty()) 2124 continue; 2125 ++Count; 2126 2127 SS << "\n case " << A.Name << ":\n"; 2128 2129 if (SuperClasses.size() == 1) { 2130 SS << " return B == " << SuperClasses.back().str() << ";\n"; 2131 continue; 2132 } 2133 2134 if (!SuperClasses.empty()) { 2135 SS << " switch (B) {\n"; 2136 SS << " default: return false;\n"; 2137 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i) 2138 SS << " case " << SuperClasses[i].str() << ": return true;\n"; 2139 SS << " }\n"; 2140 } else { 2141 // No case statement to emit 2142 SS << " return false;\n"; 2143 } 2144 } 2145 SS << " }\n"; 2146 2147 // If there were case statements emitted into the string stream, write them 2148 // to the output stream, otherwise write the default. 2149 if (Count) 2150 OS << SS.str(); 2151 else 2152 OS << " return false;\n"; 2153 2154 OS << "}\n\n"; 2155 } 2156 2157 /// emitMatchTokenString - Emit the function to match a token string to the 2158 /// appropriate match class value. 2159 static void emitMatchTokenString(CodeGenTarget &Target, 2160 std::vector<ClassInfo*> &Infos, 2161 raw_ostream &OS) { 2162 // Construct the match list. 2163 std::vector<StringMatcher::StringPair> Matches; 2164 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 2165 ie = Infos.end(); it != ie; ++it) { 2166 ClassInfo &CI = **it; 2167 2168 if (CI.Kind == ClassInfo::Token) 2169 Matches.push_back(StringMatcher::StringPair(CI.ValueName, 2170 "return " + CI.Name + ";")); 2171 } 2172 2173 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n"; 2174 2175 StringMatcher("Name", Matches, OS).Emit(); 2176 2177 OS << " return InvalidMatchClass;\n"; 2178 OS << "}\n\n"; 2179 } 2180 2181 /// emitMatchRegisterName - Emit the function to match a string to the target 2182 /// specific register enum. 2183 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser, 2184 raw_ostream &OS) { 2185 // Construct the match list. 2186 std::vector<StringMatcher::StringPair> Matches; 2187 const std::vector<CodeGenRegister*> &Regs = 2188 Target.getRegBank().getRegisters(); 2189 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 2190 const CodeGenRegister *Reg = Regs[i]; 2191 if (Reg->TheDef->getValueAsString("AsmName").empty()) 2192 continue; 2193 2194 Matches.push_back(StringMatcher::StringPair( 2195 Reg->TheDef->getValueAsString("AsmName"), 2196 "return " + utostr(Reg->EnumValue) + ";")); 2197 } 2198 2199 OS << "static unsigned MatchRegisterName(StringRef Name) {\n"; 2200 2201 StringMatcher("Name", Matches, OS).Emit(); 2202 2203 OS << " return 0;\n"; 2204 OS << "}\n\n"; 2205 } 2206 2207 static const char *getMinimalTypeForRange(uint64_t Range) { 2208 assert(Range <= 0xFFFFFFFFULL && "Enum too large"); 2209 if (Range > 0xFFFF) 2210 return "uint32_t"; 2211 if (Range > 0xFF) 2212 return "uint16_t"; 2213 return "uint8_t"; 2214 } 2215 2216 static const char *getMinimalRequiredFeaturesType(const AsmMatcherInfo &Info) { 2217 uint64_t MaxIndex = Info.SubtargetFeatures.size(); 2218 if (MaxIndex > 0) 2219 MaxIndex--; 2220 return getMinimalTypeForRange(1ULL << MaxIndex); 2221 } 2222 2223 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag 2224 /// definitions. 2225 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info, 2226 raw_ostream &OS) { 2227 OS << "// Flags for subtarget features that participate in " 2228 << "instruction matching.\n"; 2229 OS << "enum SubtargetFeatureFlag : " << getMinimalRequiredFeaturesType(Info) 2230 << " {\n"; 2231 for (std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator 2232 it = Info.SubtargetFeatures.begin(), 2233 ie = Info.SubtargetFeatures.end(); it != ie; ++it) { 2234 SubtargetFeatureInfo &SFI = *it->second; 2235 OS << " " << SFI.getEnumName() << " = (1U << " << SFI.Index << "),\n"; 2236 } 2237 OS << " Feature_None = 0\n"; 2238 OS << "};\n\n"; 2239 } 2240 2241 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types. 2242 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) { 2243 // Get the set of diagnostic types from all of the operand classes. 2244 std::set<StringRef> Types; 2245 for (std::map<Record*, ClassInfo*>::const_iterator 2246 I = Info.AsmOperandClasses.begin(), 2247 E = Info.AsmOperandClasses.end(); I != E; ++I) { 2248 if (!I->second->DiagnosticType.empty()) 2249 Types.insert(I->second->DiagnosticType); 2250 } 2251 2252 if (Types.empty()) return; 2253 2254 // Now emit the enum entries. 2255 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end(); 2256 I != E; ++I) 2257 OS << " Match_" << *I << ",\n"; 2258 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n"; 2259 } 2260 2261 /// emitGetSubtargetFeatureName - Emit the helper function to get the 2262 /// user-level name for a subtarget feature. 2263 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) { 2264 OS << "// User-level names for subtarget features that participate in\n" 2265 << "// instruction matching.\n" 2266 << "static const char *getSubtargetFeatureName(unsigned Val) {\n"; 2267 if (!Info.SubtargetFeatures.empty()) { 2268 OS << " switch(Val) {\n"; 2269 typedef std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> RecFeatMap; 2270 for (RecFeatMap::const_iterator it = Info.SubtargetFeatures.begin(), 2271 ie = Info.SubtargetFeatures.end(); it != ie; ++it) { 2272 SubtargetFeatureInfo &SFI = *it->second; 2273 // FIXME: Totally just a placeholder name to get the algorithm working. 2274 OS << " case " << SFI.getEnumName() << ": return \"" 2275 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n"; 2276 } 2277 OS << " default: return \"(unknown)\";\n"; 2278 OS << " }\n"; 2279 } else { 2280 // Nothing to emit, so skip the switch 2281 OS << " return \"(unknown)\";\n"; 2282 } 2283 OS << "}\n\n"; 2284 } 2285 2286 /// emitComputeAvailableFeatures - Emit the function to compute the list of 2287 /// available features given a subtarget. 2288 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info, 2289 raw_ostream &OS) { 2290 std::string ClassName = 2291 Info.AsmParser->getValueAsString("AsmParserClassName"); 2292 2293 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n" 2294 << "ComputeAvailableFeatures(uint64_t FB) const {\n"; 2295 OS << " unsigned Features = 0;\n"; 2296 for (std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator 2297 it = Info.SubtargetFeatures.begin(), 2298 ie = Info.SubtargetFeatures.end(); it != ie; ++it) { 2299 SubtargetFeatureInfo &SFI = *it->second; 2300 2301 OS << " if ("; 2302 std::string CondStorage = 2303 SFI.TheDef->getValueAsString("AssemblerCondString"); 2304 StringRef Conds = CondStorage; 2305 std::pair<StringRef,StringRef> Comma = Conds.split(','); 2306 bool First = true; 2307 do { 2308 if (!First) 2309 OS << " && "; 2310 2311 bool Neg = false; 2312 StringRef Cond = Comma.first; 2313 if (Cond[0] == '!') { 2314 Neg = true; 2315 Cond = Cond.substr(1); 2316 } 2317 2318 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")"; 2319 if (Neg) 2320 OS << " == 0"; 2321 else 2322 OS << " != 0"; 2323 OS << ")"; 2324 2325 if (Comma.second.empty()) 2326 break; 2327 2328 First = false; 2329 Comma = Comma.second.split(','); 2330 } while (true); 2331 2332 OS << ")\n"; 2333 OS << " Features |= " << SFI.getEnumName() << ";\n"; 2334 } 2335 OS << " return Features;\n"; 2336 OS << "}\n\n"; 2337 } 2338 2339 static std::string GetAliasRequiredFeatures(Record *R, 2340 const AsmMatcherInfo &Info) { 2341 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates"); 2342 std::string Result; 2343 unsigned NumFeatures = 0; 2344 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) { 2345 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]); 2346 2347 if (!F) 2348 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() + 2349 "' is not marked as an AssemblerPredicate!"); 2350 2351 if (NumFeatures) 2352 Result += '|'; 2353 2354 Result += F->getEnumName(); 2355 ++NumFeatures; 2356 } 2357 2358 if (NumFeatures > 1) 2359 Result = '(' + Result + ')'; 2360 return Result; 2361 } 2362 2363 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info, 2364 std::vector<Record*> &Aliases, 2365 unsigned Indent = 0, 2366 StringRef AsmParserVariantName = StringRef()){ 2367 // Keep track of all the aliases from a mnemonic. Use an std::map so that the 2368 // iteration order of the map is stable. 2369 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic; 2370 2371 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) { 2372 Record *R = Aliases[i]; 2373 // FIXME: Allow AssemblerVariantName to be a comma separated list. 2374 std::string AsmVariantName = R->getValueAsString("AsmVariantName"); 2375 if (AsmVariantName != AsmParserVariantName) 2376 continue; 2377 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R); 2378 } 2379 if (AliasesFromMnemonic.empty()) 2380 return; 2381 2382 // Process each alias a "from" mnemonic at a time, building the code executed 2383 // by the string remapper. 2384 std::vector<StringMatcher::StringPair> Cases; 2385 for (std::map<std::string, std::vector<Record*> >::iterator 2386 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end(); 2387 I != E; ++I) { 2388 const std::vector<Record*> &ToVec = I->second; 2389 2390 // Loop through each alias and emit code that handles each case. If there 2391 // are two instructions without predicates, emit an error. If there is one, 2392 // emit it last. 2393 std::string MatchCode; 2394 int AliasWithNoPredicate = -1; 2395 2396 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) { 2397 Record *R = ToVec[i]; 2398 std::string FeatureMask = GetAliasRequiredFeatures(R, Info); 2399 2400 // If this unconditionally matches, remember it for later and diagnose 2401 // duplicates. 2402 if (FeatureMask.empty()) { 2403 if (AliasWithNoPredicate != -1) { 2404 // We can't have two aliases from the same mnemonic with no predicate. 2405 PrintError(ToVec[AliasWithNoPredicate]->getLoc(), 2406 "two MnemonicAliases with the same 'from' mnemonic!"); 2407 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias."); 2408 } 2409 2410 AliasWithNoPredicate = i; 2411 continue; 2412 } 2413 if (R->getValueAsString("ToMnemonic") == I->first) 2414 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string"); 2415 2416 if (!MatchCode.empty()) 2417 MatchCode += "else "; 2418 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n"; 2419 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n"; 2420 } 2421 2422 if (AliasWithNoPredicate != -1) { 2423 Record *R = ToVec[AliasWithNoPredicate]; 2424 if (!MatchCode.empty()) 2425 MatchCode += "else\n "; 2426 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n"; 2427 } 2428 2429 MatchCode += "return;"; 2430 2431 Cases.push_back(std::make_pair(I->first, MatchCode)); 2432 } 2433 StringMatcher("Mnemonic", Cases, OS).Emit(Indent); 2434 } 2435 2436 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions, 2437 /// emit a function for them and return true, otherwise return false. 2438 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info, 2439 CodeGenTarget &Target) { 2440 // Ignore aliases when match-prefix is set. 2441 if (!MatchPrefix.empty()) 2442 return false; 2443 2444 std::vector<Record*> Aliases = 2445 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias"); 2446 if (Aliases.empty()) return false; 2447 2448 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, " 2449 "unsigned Features, unsigned VariantID) {\n"; 2450 OS << " switch (VariantID) {\n"; 2451 unsigned VariantCount = Target.getAsmParserVariantCount(); 2452 for (unsigned VC = 0; VC != VariantCount; ++VC) { 2453 Record *AsmVariant = Target.getAsmParserVariant(VC); 2454 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant"); 2455 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name"); 2456 OS << " case " << AsmParserVariantNo << ":\n"; 2457 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2, 2458 AsmParserVariantName); 2459 OS << " break;\n"; 2460 } 2461 OS << " }\n"; 2462 2463 // Emit aliases that apply to all variants. 2464 emitMnemonicAliasVariant(OS, Info, Aliases); 2465 2466 OS << "}\n\n"; 2467 2468 return true; 2469 } 2470 2471 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target, 2472 const AsmMatcherInfo &Info, StringRef ClassName, 2473 StringToOffsetTable &StringTable, 2474 unsigned MaxMnemonicIndex) { 2475 unsigned MaxMask = 0; 2476 for (std::vector<OperandMatchEntry>::const_iterator it = 2477 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end(); 2478 it != ie; ++it) { 2479 MaxMask |= it->OperandMask; 2480 } 2481 2482 // Emit the static custom operand parsing table; 2483 OS << "namespace {\n"; 2484 OS << " struct OperandMatchEntry {\n"; 2485 OS << " " << getMinimalRequiredFeaturesType(Info) 2486 << " RequiredFeatures;\n"; 2487 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex) 2488 << " Mnemonic;\n"; 2489 OS << " " << getMinimalTypeForRange(Info.Classes.size()) 2490 << " Class;\n"; 2491 OS << " " << getMinimalTypeForRange(MaxMask) 2492 << " OperandMask;\n\n"; 2493 OS << " StringRef getMnemonic() const {\n"; 2494 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n"; 2495 OS << " MnemonicTable[Mnemonic]);\n"; 2496 OS << " }\n"; 2497 OS << " };\n\n"; 2498 2499 OS << " // Predicate for searching for an opcode.\n"; 2500 OS << " struct LessOpcodeOperand {\n"; 2501 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n"; 2502 OS << " return LHS.getMnemonic() < RHS;\n"; 2503 OS << " }\n"; 2504 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n"; 2505 OS << " return LHS < RHS.getMnemonic();\n"; 2506 OS << " }\n"; 2507 OS << " bool operator()(const OperandMatchEntry &LHS,"; 2508 OS << " const OperandMatchEntry &RHS) {\n"; 2509 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n"; 2510 OS << " }\n"; 2511 OS << " };\n"; 2512 2513 OS << "} // end anonymous namespace.\n\n"; 2514 2515 OS << "static const OperandMatchEntry OperandMatchTable[" 2516 << Info.OperandMatchInfo.size() << "] = {\n"; 2517 2518 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n"; 2519 for (std::vector<OperandMatchEntry>::const_iterator it = 2520 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end(); 2521 it != ie; ++it) { 2522 const OperandMatchEntry &OMI = *it; 2523 const MatchableInfo &II = *OMI.MI; 2524 2525 OS << " { "; 2526 2527 // Write the required features mask. 2528 if (!II.RequiredFeatures.empty()) { 2529 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) { 2530 if (i) OS << "|"; 2531 OS << II.RequiredFeatures[i]->getEnumName(); 2532 } 2533 } else 2534 OS << "0"; 2535 2536 // Store a pascal-style length byte in the mnemonic. 2537 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str(); 2538 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false) 2539 << " /* " << II.Mnemonic << " */, "; 2540 2541 OS << OMI.CI->Name; 2542 2543 OS << ", " << OMI.OperandMask; 2544 OS << " /* "; 2545 bool printComma = false; 2546 for (int i = 0, e = 31; i !=e; ++i) 2547 if (OMI.OperandMask & (1 << i)) { 2548 if (printComma) 2549 OS << ", "; 2550 OS << i; 2551 printComma = true; 2552 } 2553 OS << " */"; 2554 2555 OS << " },\n"; 2556 } 2557 OS << "};\n\n"; 2558 2559 // Emit the operand class switch to call the correct custom parser for 2560 // the found operand class. 2561 OS << Target.getName() << ClassName << "::OperandMatchResultTy " 2562 << Target.getName() << ClassName << "::\n" 2563 << "tryCustomParseOperand(OperandVector" 2564 << " &Operands,\n unsigned MCK) {\n\n" 2565 << " switch(MCK) {\n"; 2566 2567 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(), 2568 ie = Info.Classes.end(); it != ie; ++it) { 2569 ClassInfo *CI = *it; 2570 if (CI->ParserMethod.empty()) 2571 continue; 2572 OS << " case " << CI->Name << ":\n" 2573 << " return " << CI->ParserMethod << "(Operands);\n"; 2574 } 2575 2576 OS << " default:\n"; 2577 OS << " return MatchOperand_NoMatch;\n"; 2578 OS << " }\n"; 2579 OS << " return MatchOperand_NoMatch;\n"; 2580 OS << "}\n\n"; 2581 2582 // Emit the static custom operand parser. This code is very similar with 2583 // the other matcher. Also use MatchResultTy here just in case we go for 2584 // a better error handling. 2585 OS << Target.getName() << ClassName << "::OperandMatchResultTy " 2586 << Target.getName() << ClassName << "::\n" 2587 << "MatchOperandParserImpl(OperandVector" 2588 << " &Operands,\n StringRef Mnemonic) {\n"; 2589 2590 // Emit code to get the available features. 2591 OS << " // Get the current feature set.\n"; 2592 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n"; 2593 2594 OS << " // Get the next operand index.\n"; 2595 OS << " unsigned NextOpNum = Operands.size()-1;\n"; 2596 2597 // Emit code to search the table. 2598 OS << " // Search the table.\n"; 2599 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>"; 2600 OS << " MnemonicRange =\n"; 2601 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+" 2602 << Info.OperandMatchInfo.size() << ", Mnemonic,\n" 2603 << " LessOpcodeOperand());\n\n"; 2604 2605 OS << " if (MnemonicRange.first == MnemonicRange.second)\n"; 2606 OS << " return MatchOperand_NoMatch;\n\n"; 2607 2608 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n" 2609 << " *ie = MnemonicRange.second; it != ie; ++it) {\n"; 2610 2611 OS << " // equal_range guarantees that instruction mnemonic matches.\n"; 2612 OS << " assert(Mnemonic == it->getMnemonic());\n\n"; 2613 2614 // Emit check that the required features are available. 2615 OS << " // check if the available features match\n"; 2616 OS << " if ((AvailableFeatures & it->RequiredFeatures) " 2617 << "!= it->RequiredFeatures) {\n"; 2618 OS << " continue;\n"; 2619 OS << " }\n\n"; 2620 2621 // Emit check to ensure the operand number matches. 2622 OS << " // check if the operand in question has a custom parser.\n"; 2623 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n"; 2624 OS << " continue;\n\n"; 2625 2626 // Emit call to the custom parser method 2627 OS << " // call custom parse method to handle the operand\n"; 2628 OS << " OperandMatchResultTy Result = "; 2629 OS << "tryCustomParseOperand(Operands, it->Class);\n"; 2630 OS << " if (Result != MatchOperand_NoMatch)\n"; 2631 OS << " return Result;\n"; 2632 OS << " }\n\n"; 2633 2634 OS << " // Okay, we had no match.\n"; 2635 OS << " return MatchOperand_NoMatch;\n"; 2636 OS << "}\n\n"; 2637 } 2638 2639 void AsmMatcherEmitter::run(raw_ostream &OS) { 2640 CodeGenTarget Target(Records); 2641 Record *AsmParser = Target.getAsmParser(); 2642 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName"); 2643 2644 // Compute the information on the instructions to match. 2645 AsmMatcherInfo Info(AsmParser, Target, Records); 2646 Info.buildInfo(); 2647 2648 // Sort the instruction table using the partial order on classes. We use 2649 // stable_sort to ensure that ambiguous instructions are still 2650 // deterministically ordered. 2651 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(), 2652 less_ptr<MatchableInfo>()); 2653 2654 DEBUG_WITH_TYPE("instruction_info", { 2655 for (std::vector<MatchableInfo*>::iterator 2656 it = Info.Matchables.begin(), ie = Info.Matchables.end(); 2657 it != ie; ++it) 2658 (*it)->dump(); 2659 }); 2660 2661 // Check for ambiguous matchables. 2662 DEBUG_WITH_TYPE("ambiguous_instrs", { 2663 unsigned NumAmbiguous = 0; 2664 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) { 2665 for (unsigned j = i + 1; j != e; ++j) { 2666 MatchableInfo &A = *Info.Matchables[i]; 2667 MatchableInfo &B = *Info.Matchables[j]; 2668 2669 if (A.couldMatchAmbiguouslyWith(B)) { 2670 errs() << "warning: ambiguous matchables:\n"; 2671 A.dump(); 2672 errs() << "\nis incomparable with:\n"; 2673 B.dump(); 2674 errs() << "\n\n"; 2675 ++NumAmbiguous; 2676 } 2677 } 2678 } 2679 if (NumAmbiguous) 2680 errs() << "warning: " << NumAmbiguous 2681 << " ambiguous matchables!\n"; 2682 }); 2683 2684 // Compute the information on the custom operand parsing. 2685 Info.buildOperandMatchInfo(); 2686 2687 // Write the output. 2688 2689 // Information for the class declaration. 2690 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n"; 2691 OS << "#undef GET_ASSEMBLER_HEADER\n"; 2692 OS << " // This should be included into the middle of the declaration of\n"; 2693 OS << " // your subclasses implementation of MCTargetAsmParser.\n"; 2694 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n"; 2695 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, " 2696 << "unsigned Opcode,\n" 2697 << " const OperandVector " 2698 << "&Operands);\n"; 2699 OS << " void convertToMapAndConstraints(unsigned Kind,\n "; 2700 OS << " const OperandVector &Operands) override;\n"; 2701 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;\n"; 2702 OS << " unsigned MatchInstructionImpl(\n"; 2703 OS.indent(27); 2704 OS << "const OperandVector &Operands,\n" 2705 << " MCInst &Inst,\n" 2706 << " unsigned &ErrorInfo," 2707 << " bool matchingInlineAsm,\n" 2708 << " unsigned VariantID = 0);\n"; 2709 2710 if (Info.OperandMatchInfo.size()) { 2711 OS << "\n enum OperandMatchResultTy {\n"; 2712 OS << " MatchOperand_Success, // operand matched successfully\n"; 2713 OS << " MatchOperand_NoMatch, // operand did not match\n"; 2714 OS << " MatchOperand_ParseFail // operand matched but had errors\n"; 2715 OS << " };\n"; 2716 OS << " OperandMatchResultTy MatchOperandParserImpl(\n"; 2717 OS << " OperandVector &Operands,\n"; 2718 OS << " StringRef Mnemonic);\n"; 2719 2720 OS << " OperandMatchResultTy tryCustomParseOperand(\n"; 2721 OS << " OperandVector &Operands,\n"; 2722 OS << " unsigned MCK);\n\n"; 2723 } 2724 2725 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n"; 2726 2727 // Emit the operand match diagnostic enum names. 2728 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n"; 2729 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n"; 2730 emitOperandDiagnosticTypes(Info, OS); 2731 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n"; 2732 2733 2734 OS << "\n#ifdef GET_REGISTER_MATCHER\n"; 2735 OS << "#undef GET_REGISTER_MATCHER\n\n"; 2736 2737 // Emit the subtarget feature enumeration. 2738 emitSubtargetFeatureFlagEnumeration(Info, OS); 2739 2740 // Emit the function to match a register name to number. 2741 // This should be omitted for Mips target 2742 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName")) 2743 emitMatchRegisterName(Target, AsmParser, OS); 2744 2745 OS << "#endif // GET_REGISTER_MATCHER\n\n"; 2746 2747 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n"; 2748 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n"; 2749 2750 // Generate the helper function to get the names for subtarget features. 2751 emitGetSubtargetFeatureName(Info, OS); 2752 2753 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n"; 2754 2755 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n"; 2756 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n"; 2757 2758 // Generate the function that remaps for mnemonic aliases. 2759 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target); 2760 2761 // Generate the convertToMCInst function to convert operands into an MCInst. 2762 // Also, generate the convertToMapAndConstraints function for MS-style inline 2763 // assembly. The latter doesn't actually generate a MCInst. 2764 emitConvertFuncs(Target, ClassName, Info.Matchables, OS); 2765 2766 // Emit the enumeration for classes which participate in matching. 2767 emitMatchClassEnumeration(Target, Info.Classes, OS); 2768 2769 // Emit the routine to match token strings to their match class. 2770 emitMatchTokenString(Target, Info.Classes, OS); 2771 2772 // Emit the subclass predicate routine. 2773 emitIsSubclass(Target, Info.Classes, OS); 2774 2775 // Emit the routine to validate an operand against a match class. 2776 emitValidateOperandClass(Info, OS); 2777 2778 // Emit the available features compute function. 2779 emitComputeAvailableFeatures(Info, OS); 2780 2781 2782 StringToOffsetTable StringTable; 2783 2784 size_t MaxNumOperands = 0; 2785 unsigned MaxMnemonicIndex = 0; 2786 bool HasDeprecation = false; 2787 for (std::vector<MatchableInfo*>::const_iterator it = 2788 Info.Matchables.begin(), ie = Info.Matchables.end(); 2789 it != ie; ++it) { 2790 MatchableInfo &II = **it; 2791 MaxNumOperands = std::max(MaxNumOperands, II.AsmOperands.size()); 2792 HasDeprecation |= II.HasDeprecation; 2793 2794 // Store a pascal-style length byte in the mnemonic. 2795 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str(); 2796 MaxMnemonicIndex = std::max(MaxMnemonicIndex, 2797 StringTable.GetOrAddStringOffset(LenMnemonic, false)); 2798 } 2799 2800 OS << "static const char *const MnemonicTable =\n"; 2801 StringTable.EmitString(OS); 2802 OS << ";\n\n"; 2803 2804 // Emit the static match table; unused classes get initalized to 0 which is 2805 // guaranteed to be InvalidMatchClass. 2806 // 2807 // FIXME: We can reduce the size of this table very easily. First, we change 2808 // it so that store the kinds in separate bit-fields for each index, which 2809 // only needs to be the max width used for classes at that index (we also need 2810 // to reject based on this during classification). If we then make sure to 2811 // order the match kinds appropriately (putting mnemonics last), then we 2812 // should only end up using a few bits for each class, especially the ones 2813 // following the mnemonic. 2814 OS << "namespace {\n"; 2815 OS << " struct MatchEntry {\n"; 2816 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex) 2817 << " Mnemonic;\n"; 2818 OS << " uint16_t Opcode;\n"; 2819 OS << " " << getMinimalTypeForRange(Info.Matchables.size()) 2820 << " ConvertFn;\n"; 2821 OS << " " << getMinimalRequiredFeaturesType(Info) 2822 << " RequiredFeatures;\n"; 2823 OS << " " << getMinimalTypeForRange(Info.Classes.size()) 2824 << " Classes[" << MaxNumOperands << "];\n"; 2825 OS << " StringRef getMnemonic() const {\n"; 2826 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n"; 2827 OS << " MnemonicTable[Mnemonic]);\n"; 2828 OS << " }\n"; 2829 OS << " };\n\n"; 2830 2831 OS << " // Predicate for searching for an opcode.\n"; 2832 OS << " struct LessOpcode {\n"; 2833 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n"; 2834 OS << " return LHS.getMnemonic() < RHS;\n"; 2835 OS << " }\n"; 2836 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n"; 2837 OS << " return LHS < RHS.getMnemonic();\n"; 2838 OS << " }\n"; 2839 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n"; 2840 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n"; 2841 OS << " }\n"; 2842 OS << " };\n"; 2843 2844 OS << "} // end anonymous namespace.\n\n"; 2845 2846 unsigned VariantCount = Target.getAsmParserVariantCount(); 2847 for (unsigned VC = 0; VC != VariantCount; ++VC) { 2848 Record *AsmVariant = Target.getAsmParserVariant(VC); 2849 int AsmVariantNo = AsmVariant->getValueAsInt("Variant"); 2850 2851 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n"; 2852 2853 for (std::vector<MatchableInfo*>::const_iterator it = 2854 Info.Matchables.begin(), ie = Info.Matchables.end(); 2855 it != ie; ++it) { 2856 MatchableInfo &II = **it; 2857 if (II.AsmVariantID != AsmVariantNo) 2858 continue; 2859 2860 // Store a pascal-style length byte in the mnemonic. 2861 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str(); 2862 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false) 2863 << " /* " << II.Mnemonic << " */, " 2864 << Target.getName() << "::" 2865 << II.getResultInst()->TheDef->getName() << ", " 2866 << II.ConversionFnKind << ", "; 2867 2868 // Write the required features mask. 2869 if (!II.RequiredFeatures.empty()) { 2870 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) { 2871 if (i) OS << "|"; 2872 OS << II.RequiredFeatures[i]->getEnumName(); 2873 } 2874 } else 2875 OS << "0"; 2876 2877 OS << ", { "; 2878 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { 2879 MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; 2880 2881 if (i) OS << ", "; 2882 OS << Op.Class->Name; 2883 } 2884 OS << " }, },\n"; 2885 } 2886 2887 OS << "};\n\n"; 2888 } 2889 2890 // A method to determine if a mnemonic is in the list. 2891 OS << "bool " << Target.getName() << ClassName << "::\n" 2892 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n"; 2893 OS << " // Find the appropriate table for this asm variant.\n"; 2894 OS << " const MatchEntry *Start, *End;\n"; 2895 OS << " switch (VariantID) {\n"; 2896 OS << " default: // unreachable\n"; 2897 for (unsigned VC = 0; VC != VariantCount; ++VC) { 2898 Record *AsmVariant = Target.getAsmParserVariant(VC); 2899 int AsmVariantNo = AsmVariant->getValueAsInt("Variant"); 2900 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC 2901 << "); End = std::end(MatchTable" << VC << "); break;\n"; 2902 } 2903 OS << " }\n"; 2904 OS << " // Search the table.\n"; 2905 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n"; 2906 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n"; 2907 OS << " return MnemonicRange.first != MnemonicRange.second;\n"; 2908 OS << "}\n\n"; 2909 2910 // Finally, build the match function. 2911 OS << "unsigned " << Target.getName() << ClassName << "::\n" 2912 << "MatchInstructionImpl(const OperandVector" 2913 << " &Operands,\n"; 2914 OS << " MCInst &Inst,\n" 2915 << "unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n"; 2916 2917 OS << " // Eliminate obvious mismatches.\n"; 2918 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n"; 2919 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n"; 2920 OS << " return Match_InvalidOperand;\n"; 2921 OS << " }\n\n"; 2922 2923 // Emit code to get the available features. 2924 OS << " // Get the current feature set.\n"; 2925 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n"; 2926 2927 OS << " // Get the instruction mnemonic, which is the first token.\n"; 2928 OS << " StringRef Mnemonic = ((" << Target.getName() 2929 << "Operand&)*Operands[0]).getToken();\n\n"; 2930 2931 if (HasMnemonicAliases) { 2932 OS << " // Process all MnemonicAliases to remap the mnemonic.\n"; 2933 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n"; 2934 } 2935 2936 // Emit code to compute the class list for this operand vector. 2937 OS << " // Some state to try to produce better error messages.\n"; 2938 OS << " bool HadMatchOtherThanFeatures = false;\n"; 2939 OS << " bool HadMatchOtherThanPredicate = false;\n"; 2940 OS << " unsigned RetCode = Match_InvalidOperand;\n"; 2941 OS << " unsigned MissingFeatures = ~0U;\n"; 2942 OS << " // Set ErrorInfo to the operand that mismatches if it is\n"; 2943 OS << " // wrong for all instances of the instruction.\n"; 2944 OS << " ErrorInfo = ~0U;\n"; 2945 2946 // Emit code to search the table. 2947 OS << " // Find the appropriate table for this asm variant.\n"; 2948 OS << " const MatchEntry *Start, *End;\n"; 2949 OS << " switch (VariantID) {\n"; 2950 OS << " default: // unreachable\n"; 2951 for (unsigned VC = 0; VC != VariantCount; ++VC) { 2952 Record *AsmVariant = Target.getAsmParserVariant(VC); 2953 int AsmVariantNo = AsmVariant->getValueAsInt("Variant"); 2954 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC 2955 << "); End = std::end(MatchTable" << VC << "); break;\n"; 2956 } 2957 OS << " }\n"; 2958 OS << " // Search the table.\n"; 2959 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n"; 2960 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n"; 2961 2962 OS << " // Return a more specific error code if no mnemonics match.\n"; 2963 OS << " if (MnemonicRange.first == MnemonicRange.second)\n"; 2964 OS << " return Match_MnemonicFail;\n\n"; 2965 2966 OS << " for (const MatchEntry *it = MnemonicRange.first, " 2967 << "*ie = MnemonicRange.second;\n"; 2968 OS << " it != ie; ++it) {\n"; 2969 2970 OS << " // equal_range guarantees that instruction mnemonic matches.\n"; 2971 OS << " assert(Mnemonic == it->getMnemonic());\n"; 2972 2973 // Emit check that the subclasses match. 2974 OS << " bool OperandsValid = true;\n"; 2975 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n"; 2976 OS << " if (i + 1 >= Operands.size()) {\n"; 2977 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n"; 2978 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n"; 2979 OS << " break;\n"; 2980 OS << " }\n"; 2981 OS << " unsigned Diag = validateOperandClass(*Operands[i+1],\n"; 2982 OS.indent(43); 2983 OS << "(MatchClassKind)it->Classes[i]);\n"; 2984 OS << " if (Diag == Match_Success)\n"; 2985 OS << " continue;\n"; 2986 OS << " // If the generic handler indicates an invalid operand\n"; 2987 OS << " // failure, check for a special case.\n"; 2988 OS << " if (Diag == Match_InvalidOperand) {\n"; 2989 OS << " Diag = validateTargetOperandClass(*Operands[i+1],\n"; 2990 OS.indent(43); 2991 OS << "(MatchClassKind)it->Classes[i]);\n"; 2992 OS << " if (Diag == Match_Success)\n"; 2993 OS << " continue;\n"; 2994 OS << " }\n"; 2995 OS << " // If this operand is broken for all of the instances of this\n"; 2996 OS << " // mnemonic, keep track of it so we can report loc info.\n"; 2997 OS << " // If we already had a match that only failed due to a\n"; 2998 OS << " // target predicate, that diagnostic is preferred.\n"; 2999 OS << " if (!HadMatchOtherThanPredicate &&\n"; 3000 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n"; 3001 OS << " ErrorInfo = i+1;\n"; 3002 OS << " // InvalidOperand is the default. Prefer specificity.\n"; 3003 OS << " if (Diag != Match_InvalidOperand)\n"; 3004 OS << " RetCode = Diag;\n"; 3005 OS << " }\n"; 3006 OS << " // Otherwise, just reject this instance of the mnemonic.\n"; 3007 OS << " OperandsValid = false;\n"; 3008 OS << " break;\n"; 3009 OS << " }\n\n"; 3010 3011 OS << " if (!OperandsValid) continue;\n"; 3012 3013 // Emit check that the required features are available. 3014 OS << " if ((AvailableFeatures & it->RequiredFeatures) " 3015 << "!= it->RequiredFeatures) {\n"; 3016 OS << " HadMatchOtherThanFeatures = true;\n"; 3017 OS << " unsigned NewMissingFeatures = it->RequiredFeatures & " 3018 "~AvailableFeatures;\n"; 3019 OS << " if (CountPopulation_32(NewMissingFeatures) <=\n" 3020 " CountPopulation_32(MissingFeatures))\n"; 3021 OS << " MissingFeatures = NewMissingFeatures;\n"; 3022 OS << " continue;\n"; 3023 OS << " }\n"; 3024 OS << "\n"; 3025 OS << " if (matchingInlineAsm) {\n"; 3026 OS << " Inst.setOpcode(it->Opcode);\n"; 3027 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n"; 3028 OS << " return Match_Success;\n"; 3029 OS << " }\n\n"; 3030 OS << " // We have selected a definite instruction, convert the parsed\n" 3031 << " // operands into the appropriate MCInst.\n"; 3032 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n"; 3033 OS << "\n"; 3034 3035 // Verify the instruction with the target-specific match predicate function. 3036 OS << " // We have a potential match. Check the target predicate to\n" 3037 << " // handle any context sensitive constraints.\n" 3038 << " unsigned MatchResult;\n" 3039 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !=" 3040 << " Match_Success) {\n" 3041 << " Inst.clear();\n" 3042 << " RetCode = MatchResult;\n" 3043 << " HadMatchOtherThanPredicate = true;\n" 3044 << " continue;\n" 3045 << " }\n\n"; 3046 3047 // Call the post-processing function, if used. 3048 std::string InsnCleanupFn = 3049 AsmParser->getValueAsString("AsmParserInstCleanup"); 3050 if (!InsnCleanupFn.empty()) 3051 OS << " " << InsnCleanupFn << "(Inst);\n"; 3052 3053 if (HasDeprecation) { 3054 OS << " std::string Info;\n"; 3055 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n"; 3056 OS << " SMLoc Loc = ((" << Target.getName() 3057 << "Operand&)*Operands[0]).getStartLoc();\n"; 3058 OS << " Parser.Warning(Loc, Info, None);\n"; 3059 OS << " }\n"; 3060 } 3061 3062 OS << " return Match_Success;\n"; 3063 OS << " }\n\n"; 3064 3065 OS << " // Okay, we had no match. Try to return a useful error code.\n"; 3066 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n"; 3067 OS << " return RetCode;\n\n"; 3068 OS << " // Missing feature matches return which features were missing\n"; 3069 OS << " ErrorInfo = MissingFeatures;\n"; 3070 OS << " return Match_MissingFeature;\n"; 3071 OS << "}\n\n"; 3072 3073 if (Info.OperandMatchInfo.size()) 3074 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable, 3075 MaxMnemonicIndex); 3076 3077 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n"; 3078 } 3079 3080 namespace llvm { 3081 3082 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) { 3083 emitSourceFileHeader("Assembly Matcher Source Fragment", OS); 3084 AsmMatcherEmitter(RK).run(OS); 3085 } 3086 3087 } // End llvm namespace 3088