1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/ADT/StringSwitch.h" 26 #include "llvm/ADT/Triple.h" 27 #include "llvm/IR/Type.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // Set the appropriate OS version define. 141 if (Triple.isiOS()) { 142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 143 char Str[6]; 144 Str[0] = '0' + Maj; 145 Str[1] = '0' + (Min / 10); 146 Str[2] = '0' + (Min % 10); 147 Str[3] = '0' + (Rev / 10); 148 Str[4] = '0' + (Rev % 10); 149 Str[5] = '\0'; 150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 151 Str); 152 } else if (Triple.isMacOSX()) { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[5]; 159 Str[0] = '0' + (Maj / 10); 160 Str[1] = '0' + (Maj % 10); 161 Str[2] = '0' + std::min(Min, 9U); 162 Str[3] = '0' + std::min(Rev, 9U); 163 Str[4] = '\0'; 164 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 165 } 166 167 // Tell users about the kernel if there is one. 168 if (Triple.isOSDarwin()) 169 Builder.defineMacro("__MACH__"); 170 171 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 172 } 173 174 namespace { 175 template<typename Target> 176 class DarwinTargetInfo : public OSTargetInfo<Target> { 177 protected: 178 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 179 MacroBuilder &Builder) const override { 180 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 181 this->PlatformMinVersion); 182 } 183 184 public: 185 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 186 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 187 this->MCountName = "\01mcount"; 188 } 189 190 std::string isValidSectionSpecifier(StringRef SR) const override { 191 // Let MCSectionMachO validate this. 192 StringRef Segment, Section; 193 unsigned TAA, StubSize; 194 bool HasTAA; 195 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 196 TAA, HasTAA, StubSize); 197 } 198 199 const char *getStaticInitSectionSpecifier() const override { 200 // FIXME: We should return 0 when building kexts. 201 return "__TEXT,__StaticInit,regular,pure_instructions"; 202 } 203 204 /// Darwin does not support protected visibility. Darwin's "default" 205 /// is very similar to ELF's "protected"; Darwin requires a "weak" 206 /// attribute on declarations that can be dynamically replaced. 207 bool hasProtectedVisibility() const override { 208 return false; 209 } 210 }; 211 212 213 // DragonFlyBSD Target 214 template<typename Target> 215 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 216 protected: 217 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 218 MacroBuilder &Builder) const override { 219 // DragonFly defines; list based off of gcc output 220 Builder.defineMacro("__DragonFly__"); 221 Builder.defineMacro("__DragonFly_cc_version", "100001"); 222 Builder.defineMacro("__ELF__"); 223 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 224 Builder.defineMacro("__tune_i386__"); 225 DefineStd(Builder, "unix", Opts); 226 } 227 public: 228 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 229 : OSTargetInfo<Target>(Triple) { 230 this->UserLabelPrefix = ""; 231 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const override { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 260 // On FreeBSD, wchar_t contains the number of the code point as 261 // used by the character set of the locale. These character sets are 262 // not necessarily a superset of ASCII. 263 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 264 } 265 public: 266 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 267 this->UserLabelPrefix = ""; 268 269 switch (Triple.getArch()) { 270 default: 271 case llvm::Triple::x86: 272 case llvm::Triple::x86_64: 273 this->MCountName = ".mcount"; 274 break; 275 case llvm::Triple::mips: 276 case llvm::Triple::mipsel: 277 case llvm::Triple::ppc: 278 case llvm::Triple::ppc64: 279 case llvm::Triple::ppc64le: 280 this->MCountName = "_mcount"; 281 break; 282 case llvm::Triple::arm: 283 this->MCountName = "__mcount"; 284 break; 285 } 286 } 287 }; 288 289 // GNU/kFreeBSD Target 290 template<typename Target> 291 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 292 protected: 293 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 294 MacroBuilder &Builder) const override { 295 // GNU/kFreeBSD defines; list based off of gcc output 296 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__FreeBSD_kernel__"); 299 Builder.defineMacro("__GLIBC__"); 300 Builder.defineMacro("__ELF__"); 301 if (Opts.POSIXThreads) 302 Builder.defineMacro("_REENTRANT"); 303 if (Opts.CPlusPlus) 304 Builder.defineMacro("_GNU_SOURCE"); 305 } 306 public: 307 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 } 310 }; 311 312 // Minix Target 313 template<typename Target> 314 class MinixTargetInfo : public OSTargetInfo<Target> { 315 protected: 316 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 317 MacroBuilder &Builder) const override { 318 // Minix defines 319 320 Builder.defineMacro("__minix", "3"); 321 Builder.defineMacro("_EM_WSIZE", "4"); 322 Builder.defineMacro("_EM_PSIZE", "4"); 323 Builder.defineMacro("_EM_SSIZE", "2"); 324 Builder.defineMacro("_EM_LSIZE", "4"); 325 Builder.defineMacro("_EM_FSIZE", "4"); 326 Builder.defineMacro("_EM_DSIZE", "8"); 327 Builder.defineMacro("__ELF__"); 328 DefineStd(Builder, "unix", Opts); 329 } 330 public: 331 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 332 this->UserLabelPrefix = ""; 333 } 334 }; 335 336 // Linux target 337 template<typename Target> 338 class LinuxTargetInfo : public OSTargetInfo<Target> { 339 protected: 340 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 341 MacroBuilder &Builder) const override { 342 // Linux defines; list based off of gcc output 343 DefineStd(Builder, "unix", Opts); 344 DefineStd(Builder, "linux", Opts); 345 Builder.defineMacro("__gnu_linux__"); 346 Builder.defineMacro("__ELF__"); 347 if (Triple.getEnvironment() == llvm::Triple::Android) 348 Builder.defineMacro("__ANDROID__", "1"); 349 if (Opts.POSIXThreads) 350 Builder.defineMacro("_REENTRANT"); 351 if (Opts.CPlusPlus) 352 Builder.defineMacro("_GNU_SOURCE"); 353 } 354 public: 355 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 356 this->UserLabelPrefix = ""; 357 this->WIntType = TargetInfo::UnsignedInt; 358 359 switch (Triple.getArch()) { 360 default: 361 break; 362 case llvm::Triple::ppc: 363 case llvm::Triple::ppc64: 364 case llvm::Triple::ppc64le: 365 this->MCountName = "_mcount"; 366 break; 367 } 368 } 369 370 const char *getStaticInitSectionSpecifier() const override { 371 return ".text.startup"; 372 } 373 }; 374 375 // NetBSD Target 376 template<typename Target> 377 class NetBSDTargetInfo : public OSTargetInfo<Target> { 378 protected: 379 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 380 MacroBuilder &Builder) const override { 381 // NetBSD defines; list based off of gcc output 382 Builder.defineMacro("__NetBSD__"); 383 Builder.defineMacro("__unix__"); 384 Builder.defineMacro("__ELF__"); 385 if (Opts.POSIXThreads) 386 Builder.defineMacro("_POSIX_THREADS"); 387 388 switch (Triple.getArch()) { 389 default: 390 break; 391 case llvm::Triple::arm: 392 case llvm::Triple::armeb: 393 case llvm::Triple::thumb: 394 case llvm::Triple::thumbeb: 395 Builder.defineMacro("__ARM_DWARF_EH__"); 396 break; 397 } 398 } 399 public: 400 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 401 this->UserLabelPrefix = ""; 402 } 403 }; 404 405 // OpenBSD Target 406 template<typename Target> 407 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // OpenBSD defines; list based off of gcc output 412 413 Builder.defineMacro("__OpenBSD__"); 414 DefineStd(Builder, "unix", Opts); 415 Builder.defineMacro("__ELF__"); 416 if (Opts.POSIXThreads) 417 Builder.defineMacro("_REENTRANT"); 418 } 419 public: 420 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 421 this->UserLabelPrefix = ""; 422 this->TLSSupported = false; 423 424 switch (Triple.getArch()) { 425 default: 426 case llvm::Triple::x86: 427 case llvm::Triple::x86_64: 428 case llvm::Triple::arm: 429 case llvm::Triple::sparc: 430 this->MCountName = "__mcount"; 431 break; 432 case llvm::Triple::mips64: 433 case llvm::Triple::mips64el: 434 case llvm::Triple::ppc: 435 case llvm::Triple::sparcv9: 436 this->MCountName = "_mcount"; 437 break; 438 } 439 } 440 }; 441 442 // Bitrig Target 443 template<typename Target> 444 class BitrigTargetInfo : public OSTargetInfo<Target> { 445 protected: 446 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 447 MacroBuilder &Builder) const override { 448 // Bitrig defines; list based off of gcc output 449 450 Builder.defineMacro("__Bitrig__"); 451 DefineStd(Builder, "unix", Opts); 452 Builder.defineMacro("__ELF__"); 453 if (Opts.POSIXThreads) 454 Builder.defineMacro("_REENTRANT"); 455 } 456 public: 457 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 458 this->UserLabelPrefix = ""; 459 this->MCountName = "__mcount"; 460 } 461 }; 462 463 // PSP Target 464 template<typename Target> 465 class PSPTargetInfo : public OSTargetInfo<Target> { 466 protected: 467 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 468 MacroBuilder &Builder) const override { 469 // PSP defines; list based on the output of the pspdev gcc toolchain. 470 Builder.defineMacro("PSP"); 471 Builder.defineMacro("_PSP"); 472 Builder.defineMacro("__psp__"); 473 Builder.defineMacro("__ELF__"); 474 } 475 public: 476 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 477 this->UserLabelPrefix = ""; 478 } 479 }; 480 481 // PS3 PPU Target 482 template<typename Target> 483 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 484 protected: 485 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 486 MacroBuilder &Builder) const override { 487 // PS3 PPU defines. 488 Builder.defineMacro("__PPC__"); 489 Builder.defineMacro("__PPU__"); 490 Builder.defineMacro("__CELLOS_LV2__"); 491 Builder.defineMacro("__ELF__"); 492 Builder.defineMacro("__LP32__"); 493 Builder.defineMacro("_ARCH_PPC64"); 494 Builder.defineMacro("__powerpc64__"); 495 } 496 public: 497 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 498 this->UserLabelPrefix = ""; 499 this->LongWidth = this->LongAlign = 32; 500 this->PointerWidth = this->PointerAlign = 32; 501 this->IntMaxType = TargetInfo::SignedLongLong; 502 this->UIntMaxType = TargetInfo::UnsignedLongLong; 503 this->Int64Type = TargetInfo::SignedLongLong; 504 this->SizeType = TargetInfo::UnsignedInt; 505 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 506 } 507 }; 508 509 // AuroraUX target 510 template<typename Target> 511 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 512 protected: 513 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 514 MacroBuilder &Builder) const override { 515 DefineStd(Builder, "sun", Opts); 516 DefineStd(Builder, "unix", Opts); 517 Builder.defineMacro("__ELF__"); 518 Builder.defineMacro("__svr4__"); 519 Builder.defineMacro("__SVR4"); 520 } 521 public: 522 AuroraUXTargetInfo(const llvm::Triple &Triple) 523 : OSTargetInfo<Target>(Triple) { 524 this->UserLabelPrefix = ""; 525 this->WCharType = this->SignedLong; 526 // FIXME: WIntType should be SignedLong 527 } 528 }; 529 530 // Solaris target 531 template<typename Target> 532 class SolarisTargetInfo : public OSTargetInfo<Target> { 533 protected: 534 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 535 MacroBuilder &Builder) const override { 536 DefineStd(Builder, "sun", Opts); 537 DefineStd(Builder, "unix", Opts); 538 Builder.defineMacro("__ELF__"); 539 Builder.defineMacro("__svr4__"); 540 Builder.defineMacro("__SVR4"); 541 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 542 // newer, but to 500 for everything else. feature_test.h has a check to 543 // ensure that you are not using C99 with an old version of X/Open or C89 544 // with a new version. 545 if (Opts.C99 || Opts.C11) 546 Builder.defineMacro("_XOPEN_SOURCE", "600"); 547 else 548 Builder.defineMacro("_XOPEN_SOURCE", "500"); 549 if (Opts.CPlusPlus) 550 Builder.defineMacro("__C99FEATURES__"); 551 Builder.defineMacro("_LARGEFILE_SOURCE"); 552 Builder.defineMacro("_LARGEFILE64_SOURCE"); 553 Builder.defineMacro("__EXTENSIONS__"); 554 Builder.defineMacro("_REENTRANT"); 555 } 556 public: 557 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 558 this->UserLabelPrefix = ""; 559 this->WCharType = this->SignedInt; 560 // FIXME: WIntType should be SignedLong 561 } 562 }; 563 564 // Windows target 565 template<typename Target> 566 class WindowsTargetInfo : public OSTargetInfo<Target> { 567 protected: 568 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 569 MacroBuilder &Builder) const override { 570 Builder.defineMacro("_WIN32"); 571 } 572 void getVisualStudioDefines(const LangOptions &Opts, 573 MacroBuilder &Builder) const { 574 if (Opts.CPlusPlus) { 575 if (Opts.RTTIData) 576 Builder.defineMacro("_CPPRTTI"); 577 578 if (Opts.Exceptions) 579 Builder.defineMacro("_CPPUNWIND"); 580 } 581 582 if (!Opts.CharIsSigned) 583 Builder.defineMacro("_CHAR_UNSIGNED"); 584 585 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 586 // but it works for now. 587 if (Opts.POSIXThreads) 588 Builder.defineMacro("_MT"); 589 590 if (Opts.MSCVersion != 0) { 591 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion / 100000)); 592 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCVersion)); 593 // FIXME We cannot encode the revision information into 32-bits 594 Builder.defineMacro("_MSC_BUILD", Twine(1)); 595 } 596 597 if (Opts.MicrosoftExt) { 598 Builder.defineMacro("_MSC_EXTENSIONS"); 599 600 if (Opts.CPlusPlus11) { 601 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 602 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 603 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 604 } 605 } 606 607 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 608 } 609 610 public: 611 WindowsTargetInfo(const llvm::Triple &Triple) 612 : OSTargetInfo<Target>(Triple) {} 613 }; 614 615 template <typename Target> 616 class NaClTargetInfo : public OSTargetInfo<Target> { 617 protected: 618 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 619 MacroBuilder &Builder) const override { 620 if (Opts.POSIXThreads) 621 Builder.defineMacro("_REENTRANT"); 622 if (Opts.CPlusPlus) 623 Builder.defineMacro("_GNU_SOURCE"); 624 625 DefineStd(Builder, "unix", Opts); 626 Builder.defineMacro("__ELF__"); 627 Builder.defineMacro("__native_client__"); 628 } 629 630 public: 631 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 632 this->UserLabelPrefix = ""; 633 this->LongAlign = 32; 634 this->LongWidth = 32; 635 this->PointerAlign = 32; 636 this->PointerWidth = 32; 637 this->IntMaxType = TargetInfo::SignedLongLong; 638 this->UIntMaxType = TargetInfo::UnsignedLongLong; 639 this->Int64Type = TargetInfo::SignedLongLong; 640 this->DoubleAlign = 64; 641 this->LongDoubleWidth = 64; 642 this->LongDoubleAlign = 64; 643 this->LongLongWidth = 64; 644 this->LongLongAlign = 64; 645 this->SizeType = TargetInfo::UnsignedInt; 646 this->PtrDiffType = TargetInfo::SignedInt; 647 this->IntPtrType = TargetInfo::SignedInt; 648 // RegParmMax is inherited from the underlying architecture 649 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 650 if (Triple.getArch() == llvm::Triple::arm) { 651 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 652 } else if (Triple.getArch() == llvm::Triple::x86) { 653 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 654 } else if (Triple.getArch() == llvm::Triple::x86_64) { 655 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 656 } else if (Triple.getArch() == llvm::Triple::mipsel) { 657 // Handled on mips' setDescriptionString. 658 } else { 659 assert(Triple.getArch() == llvm::Triple::le32); 660 this->DescriptionString = "e-p:32:32-i64:64"; 661 } 662 } 663 typename Target::CallingConvCheckResult checkCallingConvention( 664 CallingConv CC) const override { 665 return CC == CC_PnaclCall ? Target::CCCR_OK : 666 Target::checkCallingConvention(CC); 667 } 668 }; 669 } // end anonymous namespace. 670 671 //===----------------------------------------------------------------------===// 672 // Specific target implementations. 673 //===----------------------------------------------------------------------===// 674 675 namespace { 676 // PPC abstract base class 677 class PPCTargetInfo : public TargetInfo { 678 static const Builtin::Info BuiltinInfo[]; 679 static const char * const GCCRegNames[]; 680 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 681 std::string CPU; 682 683 // Target cpu features. 684 bool HasVSX; 685 686 public: 687 PPCTargetInfo(const llvm::Triple &Triple) 688 : TargetInfo(Triple), HasVSX(false) { 689 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 690 LongDoubleWidth = LongDoubleAlign = 128; 691 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 692 } 693 694 /// \brief Flags for architecture specific defines. 695 typedef enum { 696 ArchDefineNone = 0, 697 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 698 ArchDefinePpcgr = 1 << 1, 699 ArchDefinePpcsq = 1 << 2, 700 ArchDefine440 = 1 << 3, 701 ArchDefine603 = 1 << 4, 702 ArchDefine604 = 1 << 5, 703 ArchDefinePwr4 = 1 << 6, 704 ArchDefinePwr5 = 1 << 7, 705 ArchDefinePwr5x = 1 << 8, 706 ArchDefinePwr6 = 1 << 9, 707 ArchDefinePwr6x = 1 << 10, 708 ArchDefinePwr7 = 1 << 11, 709 ArchDefinePwr8 = 1 << 12, 710 ArchDefineA2 = 1 << 13, 711 ArchDefineA2q = 1 << 14 712 } ArchDefineTypes; 713 714 // Note: GCC recognizes the following additional cpus: 715 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 716 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 717 // titan, rs64. 718 bool setCPU(const std::string &Name) override { 719 bool CPUKnown = llvm::StringSwitch<bool>(Name) 720 .Case("generic", true) 721 .Case("440", true) 722 .Case("450", true) 723 .Case("601", true) 724 .Case("602", true) 725 .Case("603", true) 726 .Case("603e", true) 727 .Case("603ev", true) 728 .Case("604", true) 729 .Case("604e", true) 730 .Case("620", true) 731 .Case("630", true) 732 .Case("g3", true) 733 .Case("7400", true) 734 .Case("g4", true) 735 .Case("7450", true) 736 .Case("g4+", true) 737 .Case("750", true) 738 .Case("970", true) 739 .Case("g5", true) 740 .Case("a2", true) 741 .Case("a2q", true) 742 .Case("e500mc", true) 743 .Case("e5500", true) 744 .Case("power3", true) 745 .Case("pwr3", true) 746 .Case("power4", true) 747 .Case("pwr4", true) 748 .Case("power5", true) 749 .Case("pwr5", true) 750 .Case("power5x", true) 751 .Case("pwr5x", true) 752 .Case("power6", true) 753 .Case("pwr6", true) 754 .Case("power6x", true) 755 .Case("pwr6x", true) 756 .Case("power7", true) 757 .Case("pwr7", true) 758 .Case("power8", true) 759 .Case("pwr8", true) 760 .Case("powerpc", true) 761 .Case("ppc", true) 762 .Case("powerpc64", true) 763 .Case("ppc64", true) 764 .Case("powerpc64le", true) 765 .Case("ppc64le", true) 766 .Default(false); 767 768 if (CPUKnown) 769 CPU = Name; 770 771 return CPUKnown; 772 } 773 774 void getTargetBuiltins(const Builtin::Info *&Records, 775 unsigned &NumRecords) const override { 776 Records = BuiltinInfo; 777 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 778 } 779 780 bool isCLZForZeroUndef() const override { return false; } 781 782 void getTargetDefines(const LangOptions &Opts, 783 MacroBuilder &Builder) const override; 784 785 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 786 787 bool handleTargetFeatures(std::vector<std::string> &Features, 788 DiagnosticsEngine &Diags) override; 789 bool hasFeature(StringRef Feature) const override; 790 791 void getGCCRegNames(const char * const *&Names, 792 unsigned &NumNames) const override; 793 void getGCCRegAliases(const GCCRegAlias *&Aliases, 794 unsigned &NumAliases) const override; 795 bool validateAsmConstraint(const char *&Name, 796 TargetInfo::ConstraintInfo &Info) const override { 797 switch (*Name) { 798 default: return false; 799 case 'O': // Zero 800 break; 801 case 'b': // Base register 802 case 'f': // Floating point register 803 Info.setAllowsRegister(); 804 break; 805 // FIXME: The following are added to allow parsing. 806 // I just took a guess at what the actions should be. 807 // Also, is more specific checking needed? I.e. specific registers? 808 case 'd': // Floating point register (containing 64-bit value) 809 case 'v': // Altivec vector register 810 Info.setAllowsRegister(); 811 break; 812 case 'w': 813 switch (Name[1]) { 814 case 'd':// VSX vector register to hold vector double data 815 case 'f':// VSX vector register to hold vector float data 816 case 's':// VSX vector register to hold scalar float data 817 case 'a':// Any VSX register 818 case 'c':// An individual CR bit 819 break; 820 default: 821 return false; 822 } 823 Info.setAllowsRegister(); 824 Name++; // Skip over 'w'. 825 break; 826 case 'h': // `MQ', `CTR', or `LINK' register 827 case 'q': // `MQ' register 828 case 'c': // `CTR' register 829 case 'l': // `LINK' register 830 case 'x': // `CR' register (condition register) number 0 831 case 'y': // `CR' register (condition register) 832 case 'z': // `XER[CA]' carry bit (part of the XER register) 833 Info.setAllowsRegister(); 834 break; 835 case 'I': // Signed 16-bit constant 836 case 'J': // Unsigned 16-bit constant shifted left 16 bits 837 // (use `L' instead for SImode constants) 838 case 'K': // Unsigned 16-bit constant 839 case 'L': // Signed 16-bit constant shifted left 16 bits 840 case 'M': // Constant larger than 31 841 case 'N': // Exact power of 2 842 case 'P': // Constant whose negation is a signed 16-bit constant 843 case 'G': // Floating point constant that can be loaded into a 844 // register with one instruction per word 845 case 'H': // Integer/Floating point constant that can be loaded 846 // into a register using three instructions 847 break; 848 case 'm': // Memory operand. Note that on PowerPC targets, m can 849 // include addresses that update the base register. It 850 // is therefore only safe to use `m' in an asm statement 851 // if that asm statement accesses the operand exactly once. 852 // The asm statement must also use `%U<opno>' as a 853 // placeholder for the "update" flag in the corresponding 854 // load or store instruction. For example: 855 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 856 // is correct but: 857 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 858 // is not. Use es rather than m if you don't want the base 859 // register to be updated. 860 case 'e': 861 if (Name[1] != 's') 862 return false; 863 // es: A "stable" memory operand; that is, one which does not 864 // include any automodification of the base register. Unlike 865 // `m', this constraint can be used in asm statements that 866 // might access the operand several times, or that might not 867 // access it at all. 868 Info.setAllowsMemory(); 869 Name++; // Skip over 'e'. 870 break; 871 case 'Q': // Memory operand that is an offset from a register (it is 872 // usually better to use `m' or `es' in asm statements) 873 case 'Z': // Memory operand that is an indexed or indirect from a 874 // register (it is usually better to use `m' or `es' in 875 // asm statements) 876 Info.setAllowsMemory(); 877 Info.setAllowsRegister(); 878 break; 879 case 'R': // AIX TOC entry 880 case 'a': // Address operand that is an indexed or indirect from a 881 // register (`p' is preferable for asm statements) 882 case 'S': // Constant suitable as a 64-bit mask operand 883 case 'T': // Constant suitable as a 32-bit mask operand 884 case 'U': // System V Release 4 small data area reference 885 case 't': // AND masks that can be performed by two rldic{l, r} 886 // instructions 887 case 'W': // Vector constant that does not require memory 888 case 'j': // Vector constant that is all zeros. 889 break; 890 // End FIXME. 891 } 892 return true; 893 } 894 std::string convertConstraint(const char *&Constraint) const override { 895 std::string R; 896 switch (*Constraint) { 897 case 'e': 898 case 'w': 899 // Two-character constraint; add "^" hint for later parsing. 900 R = std::string("^") + std::string(Constraint, 2); 901 Constraint++; 902 break; 903 default: 904 return TargetInfo::convertConstraint(Constraint); 905 } 906 return R; 907 } 908 const char *getClobbers() const override { 909 return ""; 910 } 911 int getEHDataRegisterNumber(unsigned RegNo) const override { 912 if (RegNo == 0) return 3; 913 if (RegNo == 1) return 4; 914 return -1; 915 } 916 }; 917 918 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 919 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 920 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 921 ALL_LANGUAGES }, 922 #include "clang/Basic/BuiltinsPPC.def" 923 }; 924 925 /// handleTargetFeatures - Perform initialization based on the user 926 /// configured set of features. 927 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 928 DiagnosticsEngine &Diags) { 929 // Remember the maximum enabled sselevel. 930 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 931 // Ignore disabled features. 932 if (Features[i][0] == '-') 933 continue; 934 935 StringRef Feature = StringRef(Features[i]).substr(1); 936 937 if (Feature == "vsx") { 938 HasVSX = true; 939 continue; 940 } 941 942 // TODO: Finish this list and add an assert that we've handled them 943 // all. 944 } 945 946 return true; 947 } 948 949 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 950 /// #defines that are not tied to a specific subtarget. 951 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 952 MacroBuilder &Builder) const { 953 // Target identification. 954 Builder.defineMacro("__ppc__"); 955 Builder.defineMacro("__PPC__"); 956 Builder.defineMacro("_ARCH_PPC"); 957 Builder.defineMacro("__powerpc__"); 958 Builder.defineMacro("__POWERPC__"); 959 if (PointerWidth == 64) { 960 Builder.defineMacro("_ARCH_PPC64"); 961 Builder.defineMacro("__powerpc64__"); 962 Builder.defineMacro("__ppc64__"); 963 Builder.defineMacro("__PPC64__"); 964 } 965 966 // Target properties. 967 if (getTriple().getArch() == llvm::Triple::ppc64le) { 968 Builder.defineMacro("_LITTLE_ENDIAN"); 969 Builder.defineMacro("_CALL_ELF","2"); 970 } else { 971 if (getTriple().getOS() != llvm::Triple::NetBSD && 972 getTriple().getOS() != llvm::Triple::OpenBSD) 973 Builder.defineMacro("_BIG_ENDIAN"); 974 } 975 976 // Subtarget options. 977 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 978 Builder.defineMacro("__REGISTER_PREFIX__", ""); 979 980 // FIXME: Should be controlled by command line option. 981 if (LongDoubleWidth == 128) 982 Builder.defineMacro("__LONG_DOUBLE_128__"); 983 984 if (Opts.AltiVec) { 985 Builder.defineMacro("__VEC__", "10206"); 986 Builder.defineMacro("__ALTIVEC__"); 987 } 988 989 // CPU identification. 990 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 991 .Case("440", ArchDefineName) 992 .Case("450", ArchDefineName | ArchDefine440) 993 .Case("601", ArchDefineName) 994 .Case("602", ArchDefineName | ArchDefinePpcgr) 995 .Case("603", ArchDefineName | ArchDefinePpcgr) 996 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 997 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 998 .Case("604", ArchDefineName | ArchDefinePpcgr) 999 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1000 .Case("620", ArchDefineName | ArchDefinePpcgr) 1001 .Case("630", ArchDefineName | ArchDefinePpcgr) 1002 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1003 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1004 .Case("750", ArchDefineName | ArchDefinePpcgr) 1005 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1006 | ArchDefinePpcsq) 1007 .Case("a2", ArchDefineA2) 1008 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1009 .Case("pwr3", ArchDefinePpcgr) 1010 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1011 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1012 | ArchDefinePpcsq) 1013 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1014 | ArchDefinePpcgr | ArchDefinePpcsq) 1015 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1016 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1017 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1018 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1019 | ArchDefinePpcsq) 1020 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1021 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1022 | ArchDefinePpcgr | ArchDefinePpcsq) 1023 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1024 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1025 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1026 .Case("power3", ArchDefinePpcgr) 1027 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1028 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1029 | ArchDefinePpcsq) 1030 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1031 | ArchDefinePpcgr | ArchDefinePpcsq) 1032 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1033 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1034 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1035 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1036 | ArchDefinePpcsq) 1037 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1038 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1039 | ArchDefinePpcgr | ArchDefinePpcsq) 1040 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1041 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1042 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1043 .Default(ArchDefineNone); 1044 1045 if (defs & ArchDefineName) 1046 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1047 if (defs & ArchDefinePpcgr) 1048 Builder.defineMacro("_ARCH_PPCGR"); 1049 if (defs & ArchDefinePpcsq) 1050 Builder.defineMacro("_ARCH_PPCSQ"); 1051 if (defs & ArchDefine440) 1052 Builder.defineMacro("_ARCH_440"); 1053 if (defs & ArchDefine603) 1054 Builder.defineMacro("_ARCH_603"); 1055 if (defs & ArchDefine604) 1056 Builder.defineMacro("_ARCH_604"); 1057 if (defs & ArchDefinePwr4) 1058 Builder.defineMacro("_ARCH_PWR4"); 1059 if (defs & ArchDefinePwr5) 1060 Builder.defineMacro("_ARCH_PWR5"); 1061 if (defs & ArchDefinePwr5x) 1062 Builder.defineMacro("_ARCH_PWR5X"); 1063 if (defs & ArchDefinePwr6) 1064 Builder.defineMacro("_ARCH_PWR6"); 1065 if (defs & ArchDefinePwr6x) 1066 Builder.defineMacro("_ARCH_PWR6X"); 1067 if (defs & ArchDefinePwr7) 1068 Builder.defineMacro("_ARCH_PWR7"); 1069 if (defs & ArchDefinePwr8) 1070 Builder.defineMacro("_ARCH_PWR8"); 1071 if (defs & ArchDefineA2) 1072 Builder.defineMacro("_ARCH_A2"); 1073 if (defs & ArchDefineA2q) { 1074 Builder.defineMacro("_ARCH_A2Q"); 1075 Builder.defineMacro("_ARCH_QP"); 1076 } 1077 1078 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1079 Builder.defineMacro("__bg__"); 1080 Builder.defineMacro("__THW_BLUEGENE__"); 1081 Builder.defineMacro("__bgq__"); 1082 Builder.defineMacro("__TOS_BGQ__"); 1083 } 1084 1085 if (HasVSX) 1086 Builder.defineMacro("__VSX__"); 1087 1088 // FIXME: The following are not yet generated here by Clang, but are 1089 // generated by GCC: 1090 // 1091 // _SOFT_FLOAT_ 1092 // __RECIP_PRECISION__ 1093 // __APPLE_ALTIVEC__ 1094 // __RECIP__ 1095 // __RECIPF__ 1096 // __RSQRTE__ 1097 // __RSQRTEF__ 1098 // _SOFT_DOUBLE_ 1099 // __NO_LWSYNC__ 1100 // __HAVE_BSWAP__ 1101 // __LONGDOUBLE128 1102 // __CMODEL_MEDIUM__ 1103 // __CMODEL_LARGE__ 1104 // _CALL_SYSV 1105 // _CALL_DARWIN 1106 // __NO_FPRS__ 1107 } 1108 1109 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1110 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1111 .Case("7400", true) 1112 .Case("g4", true) 1113 .Case("7450", true) 1114 .Case("g4+", true) 1115 .Case("970", true) 1116 .Case("g5", true) 1117 .Case("pwr6", true) 1118 .Case("pwr7", true) 1119 .Case("pwr8", true) 1120 .Case("ppc64", true) 1121 .Case("ppc64le", true) 1122 .Default(false); 1123 1124 Features["qpx"] = (CPU == "a2q"); 1125 } 1126 1127 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1128 return Feature == "powerpc"; 1129 } 1130 1131 1132 const char * const PPCTargetInfo::GCCRegNames[] = { 1133 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1134 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1135 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1136 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1137 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1138 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1139 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1140 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1141 "mq", "lr", "ctr", "ap", 1142 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1143 "xer", 1144 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1145 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1146 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1147 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1148 "vrsave", "vscr", 1149 "spe_acc", "spefscr", 1150 "sfp" 1151 }; 1152 1153 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1154 unsigned &NumNames) const { 1155 Names = GCCRegNames; 1156 NumNames = llvm::array_lengthof(GCCRegNames); 1157 } 1158 1159 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1160 // While some of these aliases do map to different registers 1161 // they still share the same register name. 1162 { { "0" }, "r0" }, 1163 { { "1"}, "r1" }, 1164 { { "2" }, "r2" }, 1165 { { "3" }, "r3" }, 1166 { { "4" }, "r4" }, 1167 { { "5" }, "r5" }, 1168 { { "6" }, "r6" }, 1169 { { "7" }, "r7" }, 1170 { { "8" }, "r8" }, 1171 { { "9" }, "r9" }, 1172 { { "10" }, "r10" }, 1173 { { "11" }, "r11" }, 1174 { { "12" }, "r12" }, 1175 { { "13" }, "r13" }, 1176 { { "14" }, "r14" }, 1177 { { "15" }, "r15" }, 1178 { { "16" }, "r16" }, 1179 { { "17" }, "r17" }, 1180 { { "18" }, "r18" }, 1181 { { "19" }, "r19" }, 1182 { { "20" }, "r20" }, 1183 { { "21" }, "r21" }, 1184 { { "22" }, "r22" }, 1185 { { "23" }, "r23" }, 1186 { { "24" }, "r24" }, 1187 { { "25" }, "r25" }, 1188 { { "26" }, "r26" }, 1189 { { "27" }, "r27" }, 1190 { { "28" }, "r28" }, 1191 { { "29" }, "r29" }, 1192 { { "30" }, "r30" }, 1193 { { "31" }, "r31" }, 1194 { { "fr0" }, "f0" }, 1195 { { "fr1" }, "f1" }, 1196 { { "fr2" }, "f2" }, 1197 { { "fr3" }, "f3" }, 1198 { { "fr4" }, "f4" }, 1199 { { "fr5" }, "f5" }, 1200 { { "fr6" }, "f6" }, 1201 { { "fr7" }, "f7" }, 1202 { { "fr8" }, "f8" }, 1203 { { "fr9" }, "f9" }, 1204 { { "fr10" }, "f10" }, 1205 { { "fr11" }, "f11" }, 1206 { { "fr12" }, "f12" }, 1207 { { "fr13" }, "f13" }, 1208 { { "fr14" }, "f14" }, 1209 { { "fr15" }, "f15" }, 1210 { { "fr16" }, "f16" }, 1211 { { "fr17" }, "f17" }, 1212 { { "fr18" }, "f18" }, 1213 { { "fr19" }, "f19" }, 1214 { { "fr20" }, "f20" }, 1215 { { "fr21" }, "f21" }, 1216 { { "fr22" }, "f22" }, 1217 { { "fr23" }, "f23" }, 1218 { { "fr24" }, "f24" }, 1219 { { "fr25" }, "f25" }, 1220 { { "fr26" }, "f26" }, 1221 { { "fr27" }, "f27" }, 1222 { { "fr28" }, "f28" }, 1223 { { "fr29" }, "f29" }, 1224 { { "fr30" }, "f30" }, 1225 { { "fr31" }, "f31" }, 1226 { { "cc" }, "cr0" }, 1227 }; 1228 1229 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1230 unsigned &NumAliases) const { 1231 Aliases = GCCRegAliases; 1232 NumAliases = llvm::array_lengthof(GCCRegAliases); 1233 } 1234 } // end anonymous namespace. 1235 1236 namespace { 1237 class PPC32TargetInfo : public PPCTargetInfo { 1238 public: 1239 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1240 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1241 1242 switch (getTriple().getOS()) { 1243 case llvm::Triple::Linux: 1244 case llvm::Triple::FreeBSD: 1245 case llvm::Triple::NetBSD: 1246 SizeType = UnsignedInt; 1247 PtrDiffType = SignedInt; 1248 IntPtrType = SignedInt; 1249 break; 1250 default: 1251 break; 1252 } 1253 1254 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1255 LongDoubleWidth = LongDoubleAlign = 64; 1256 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1257 } 1258 1259 // PPC32 supports atomics up to 4 bytes. 1260 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1261 } 1262 1263 BuiltinVaListKind getBuiltinVaListKind() const override { 1264 // This is the ELF definition, and is overridden by the Darwin sub-target 1265 return TargetInfo::PowerABIBuiltinVaList; 1266 } 1267 }; 1268 } // end anonymous namespace. 1269 1270 // Note: ABI differences may eventually require us to have a separate 1271 // TargetInfo for little endian. 1272 namespace { 1273 class PPC64TargetInfo : public PPCTargetInfo { 1274 public: 1275 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1276 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1277 IntMaxType = SignedLong; 1278 UIntMaxType = UnsignedLong; 1279 Int64Type = SignedLong; 1280 1281 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1282 LongDoubleWidth = LongDoubleAlign = 64; 1283 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1284 DescriptionString = "E-m:e-i64:64-n32:64"; 1285 } else { 1286 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1287 DescriptionString = "e-m:e-i64:64-n32:64"; 1288 } else { 1289 DescriptionString = "E-m:e-i64:64-n32:64"; 1290 } 1291 } 1292 1293 // PPC64 supports atomics up to 8 bytes. 1294 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1295 } 1296 BuiltinVaListKind getBuiltinVaListKind() const override { 1297 return TargetInfo::CharPtrBuiltinVaList; 1298 } 1299 }; 1300 } // end anonymous namespace. 1301 1302 1303 namespace { 1304 class DarwinPPC32TargetInfo : 1305 public DarwinTargetInfo<PPC32TargetInfo> { 1306 public: 1307 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1308 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1309 HasAlignMac68kSupport = true; 1310 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1311 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1312 LongLongAlign = 32; 1313 SuitableAlign = 128; 1314 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1315 } 1316 BuiltinVaListKind getBuiltinVaListKind() const override { 1317 return TargetInfo::CharPtrBuiltinVaList; 1318 } 1319 }; 1320 1321 class DarwinPPC64TargetInfo : 1322 public DarwinTargetInfo<PPC64TargetInfo> { 1323 public: 1324 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1325 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1326 HasAlignMac68kSupport = true; 1327 SuitableAlign = 128; 1328 DescriptionString = "E-m:o-i64:64-n32:64"; 1329 } 1330 }; 1331 } // end anonymous namespace. 1332 1333 namespace { 1334 static const unsigned NVPTXAddrSpaceMap[] = { 1335 1, // opencl_global 1336 3, // opencl_local 1337 4, // opencl_constant 1338 1, // cuda_device 1339 4, // cuda_constant 1340 3, // cuda_shared 1341 }; 1342 class NVPTXTargetInfo : public TargetInfo { 1343 static const char * const GCCRegNames[]; 1344 static const Builtin::Info BuiltinInfo[]; 1345 public: 1346 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1347 BigEndian = false; 1348 TLSSupported = false; 1349 LongWidth = LongAlign = 64; 1350 AddrSpaceMap = &NVPTXAddrSpaceMap; 1351 UseAddrSpaceMapMangling = true; 1352 // Define available target features 1353 // These must be defined in sorted order! 1354 NoAsmVariants = true; 1355 } 1356 void getTargetDefines(const LangOptions &Opts, 1357 MacroBuilder &Builder) const override { 1358 Builder.defineMacro("__PTX__"); 1359 Builder.defineMacro("__NVPTX__"); 1360 } 1361 void getTargetBuiltins(const Builtin::Info *&Records, 1362 unsigned &NumRecords) const override { 1363 Records = BuiltinInfo; 1364 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1365 } 1366 bool hasFeature(StringRef Feature) const override { 1367 return Feature == "ptx" || Feature == "nvptx"; 1368 } 1369 1370 void getGCCRegNames(const char * const *&Names, 1371 unsigned &NumNames) const override; 1372 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1373 unsigned &NumAliases) const override { 1374 // No aliases. 1375 Aliases = nullptr; 1376 NumAliases = 0; 1377 } 1378 bool validateAsmConstraint(const char *&Name, 1379 TargetInfo::ConstraintInfo &Info) const override { 1380 switch (*Name) { 1381 default: return false; 1382 case 'c': 1383 case 'h': 1384 case 'r': 1385 case 'l': 1386 case 'f': 1387 case 'd': 1388 Info.setAllowsRegister(); 1389 return true; 1390 } 1391 } 1392 const char *getClobbers() const override { 1393 // FIXME: Is this really right? 1394 return ""; 1395 } 1396 BuiltinVaListKind getBuiltinVaListKind() const override { 1397 // FIXME: implement 1398 return TargetInfo::CharPtrBuiltinVaList; 1399 } 1400 bool setCPU(const std::string &Name) override { 1401 bool Valid = llvm::StringSwitch<bool>(Name) 1402 .Case("sm_20", true) 1403 .Case("sm_21", true) 1404 .Case("sm_30", true) 1405 .Case("sm_35", true) 1406 .Default(false); 1407 1408 return Valid; 1409 } 1410 }; 1411 1412 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1413 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1414 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1415 ALL_LANGUAGES }, 1416 #include "clang/Basic/BuiltinsNVPTX.def" 1417 }; 1418 1419 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1420 "r0" 1421 }; 1422 1423 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1424 unsigned &NumNames) const { 1425 Names = GCCRegNames; 1426 NumNames = llvm::array_lengthof(GCCRegNames); 1427 } 1428 1429 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1430 public: 1431 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1432 PointerWidth = PointerAlign = 32; 1433 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1434 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1435 } 1436 }; 1437 1438 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1439 public: 1440 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1441 PointerWidth = PointerAlign = 64; 1442 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1443 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1444 } 1445 }; 1446 } 1447 1448 namespace { 1449 1450 static const unsigned R600AddrSpaceMap[] = { 1451 1, // opencl_global 1452 3, // opencl_local 1453 2, // opencl_constant 1454 1, // cuda_device 1455 2, // cuda_constant 1456 3 // cuda_shared 1457 }; 1458 1459 static const char *DescriptionStringR600 = 1460 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1461 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1462 1463 static const char *DescriptionStringR600DoubleOps = 1464 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1465 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1466 1467 static const char *DescriptionStringSI = 1468 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1469 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1470 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1471 1472 class R600TargetInfo : public TargetInfo { 1473 static const Builtin::Info BuiltinInfo[]; 1474 1475 /// \brief The GPU profiles supported by the R600 target. 1476 enum GPUKind { 1477 GK_NONE, 1478 GK_R600, 1479 GK_R600_DOUBLE_OPS, 1480 GK_R700, 1481 GK_R700_DOUBLE_OPS, 1482 GK_EVERGREEN, 1483 GK_EVERGREEN_DOUBLE_OPS, 1484 GK_NORTHERN_ISLANDS, 1485 GK_CAYMAN, 1486 GK_SOUTHERN_ISLANDS, 1487 GK_SEA_ISLANDS 1488 } GPU; 1489 1490 public: 1491 R600TargetInfo(const llvm::Triple &Triple) 1492 : TargetInfo(Triple), GPU(GK_R600) { 1493 DescriptionString = DescriptionStringR600; 1494 AddrSpaceMap = &R600AddrSpaceMap; 1495 UseAddrSpaceMapMangling = true; 1496 } 1497 1498 const char * getClobbers() const override { 1499 return ""; 1500 } 1501 1502 void getGCCRegNames(const char * const *&Names, 1503 unsigned &numNames) const override { 1504 Names = nullptr; 1505 numNames = 0; 1506 } 1507 1508 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1509 unsigned &NumAliases) const override { 1510 Aliases = nullptr; 1511 NumAliases = 0; 1512 } 1513 1514 bool validateAsmConstraint(const char *&Name, 1515 TargetInfo::ConstraintInfo &info) const override { 1516 return true; 1517 } 1518 1519 void getTargetBuiltins(const Builtin::Info *&Records, 1520 unsigned &NumRecords) const override { 1521 Records = BuiltinInfo; 1522 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1523 } 1524 1525 void getTargetDefines(const LangOptions &Opts, 1526 MacroBuilder &Builder) const override { 1527 Builder.defineMacro("__R600__"); 1528 } 1529 1530 BuiltinVaListKind getBuiltinVaListKind() const override { 1531 return TargetInfo::CharPtrBuiltinVaList; 1532 } 1533 1534 bool setCPU(const std::string &Name) override { 1535 GPU = llvm::StringSwitch<GPUKind>(Name) 1536 .Case("r600" , GK_R600) 1537 .Case("rv610", GK_R600) 1538 .Case("rv620", GK_R600) 1539 .Case("rv630", GK_R600) 1540 .Case("rv635", GK_R600) 1541 .Case("rs780", GK_R600) 1542 .Case("rs880", GK_R600) 1543 .Case("rv670", GK_R600_DOUBLE_OPS) 1544 .Case("rv710", GK_R700) 1545 .Case("rv730", GK_R700) 1546 .Case("rv740", GK_R700_DOUBLE_OPS) 1547 .Case("rv770", GK_R700_DOUBLE_OPS) 1548 .Case("palm", GK_EVERGREEN) 1549 .Case("cedar", GK_EVERGREEN) 1550 .Case("sumo", GK_EVERGREEN) 1551 .Case("sumo2", GK_EVERGREEN) 1552 .Case("redwood", GK_EVERGREEN) 1553 .Case("juniper", GK_EVERGREEN) 1554 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1555 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1556 .Case("barts", GK_NORTHERN_ISLANDS) 1557 .Case("turks", GK_NORTHERN_ISLANDS) 1558 .Case("caicos", GK_NORTHERN_ISLANDS) 1559 .Case("cayman", GK_CAYMAN) 1560 .Case("aruba", GK_CAYMAN) 1561 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1562 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1563 .Case("verde", GK_SOUTHERN_ISLANDS) 1564 .Case("oland", GK_SOUTHERN_ISLANDS) 1565 .Case("bonaire", GK_SEA_ISLANDS) 1566 .Case("kabini", GK_SEA_ISLANDS) 1567 .Case("kaveri", GK_SEA_ISLANDS) 1568 .Case("hawaii", GK_SEA_ISLANDS) 1569 .Default(GK_NONE); 1570 1571 if (GPU == GK_NONE) { 1572 return false; 1573 } 1574 1575 // Set the correct data layout 1576 switch (GPU) { 1577 case GK_NONE: 1578 case GK_R600: 1579 case GK_R700: 1580 case GK_EVERGREEN: 1581 case GK_NORTHERN_ISLANDS: 1582 DescriptionString = DescriptionStringR600; 1583 break; 1584 case GK_R600_DOUBLE_OPS: 1585 case GK_R700_DOUBLE_OPS: 1586 case GK_EVERGREEN_DOUBLE_OPS: 1587 case GK_CAYMAN: 1588 DescriptionString = DescriptionStringR600DoubleOps; 1589 break; 1590 case GK_SOUTHERN_ISLANDS: 1591 case GK_SEA_ISLANDS: 1592 DescriptionString = DescriptionStringSI; 1593 break; 1594 } 1595 1596 return true; 1597 } 1598 }; 1599 1600 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1601 #define BUILTIN(ID, TYPE, ATTRS) \ 1602 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1603 #include "clang/Basic/BuiltinsR600.def" 1604 }; 1605 1606 } // end anonymous namespace 1607 1608 namespace { 1609 // Namespace for x86 abstract base class 1610 const Builtin::Info BuiltinInfo[] = { 1611 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1612 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1613 ALL_LANGUAGES }, 1614 #include "clang/Basic/BuiltinsX86.def" 1615 }; 1616 1617 static const char* const GCCRegNames[] = { 1618 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1619 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1620 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1621 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1622 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1623 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1624 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1625 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1626 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1627 }; 1628 1629 const TargetInfo::AddlRegName AddlRegNames[] = { 1630 { { "al", "ah", "eax", "rax" }, 0 }, 1631 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1632 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1633 { { "dl", "dh", "edx", "rdx" }, 1 }, 1634 { { "esi", "rsi" }, 4 }, 1635 { { "edi", "rdi" }, 5 }, 1636 { { "esp", "rsp" }, 7 }, 1637 { { "ebp", "rbp" }, 6 }, 1638 }; 1639 1640 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1641 // most of the implementation can be shared. 1642 class X86TargetInfo : public TargetInfo { 1643 enum X86SSEEnum { 1644 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1645 } SSELevel; 1646 enum MMX3DNowEnum { 1647 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1648 } MMX3DNowLevel; 1649 enum XOPEnum { 1650 NoXOP, 1651 SSE4A, 1652 FMA4, 1653 XOP 1654 } XOPLevel; 1655 1656 bool HasAES; 1657 bool HasPCLMUL; 1658 bool HasLZCNT; 1659 bool HasRDRND; 1660 bool HasBMI; 1661 bool HasBMI2; 1662 bool HasPOPCNT; 1663 bool HasRTM; 1664 bool HasPRFCHW; 1665 bool HasRDSEED; 1666 bool HasTBM; 1667 bool HasFMA; 1668 bool HasF16C; 1669 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1670 bool HasSHA; 1671 bool HasCX16; 1672 1673 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1674 /// 1675 /// Each enumeration represents a particular CPU supported by Clang. These 1676 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1677 enum CPUKind { 1678 CK_Generic, 1679 1680 /// \name i386 1681 /// i386-generation processors. 1682 //@{ 1683 CK_i386, 1684 //@} 1685 1686 /// \name i486 1687 /// i486-generation processors. 1688 //@{ 1689 CK_i486, 1690 CK_WinChipC6, 1691 CK_WinChip2, 1692 CK_C3, 1693 //@} 1694 1695 /// \name i586 1696 /// i586-generation processors, P5 microarchitecture based. 1697 //@{ 1698 CK_i586, 1699 CK_Pentium, 1700 CK_PentiumMMX, 1701 //@} 1702 1703 /// \name i686 1704 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1705 //@{ 1706 CK_i686, 1707 CK_PentiumPro, 1708 CK_Pentium2, 1709 CK_Pentium3, 1710 CK_Pentium3M, 1711 CK_PentiumM, 1712 CK_C3_2, 1713 1714 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1715 /// Clang however has some logic to suport this. 1716 // FIXME: Warn, deprecate, and potentially remove this. 1717 CK_Yonah, 1718 //@} 1719 1720 /// \name Netburst 1721 /// Netburst microarchitecture based processors. 1722 //@{ 1723 CK_Pentium4, 1724 CK_Pentium4M, 1725 CK_Prescott, 1726 CK_Nocona, 1727 //@} 1728 1729 /// \name Core 1730 /// Core microarchitecture based processors. 1731 //@{ 1732 CK_Core2, 1733 1734 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1735 /// codename which GCC no longer accepts as an option to -march, but Clang 1736 /// has some logic for recognizing it. 1737 // FIXME: Warn, deprecate, and potentially remove this. 1738 CK_Penryn, 1739 //@} 1740 1741 /// \name Atom 1742 /// Atom processors 1743 //@{ 1744 CK_Atom, 1745 CK_Silvermont, 1746 //@} 1747 1748 /// \name Nehalem 1749 /// Nehalem microarchitecture based processors. 1750 //@{ 1751 CK_Corei7, 1752 CK_Corei7AVX, 1753 CK_CoreAVXi, 1754 CK_CoreAVX2, 1755 //@} 1756 1757 /// \name Knights Landing 1758 /// Knights Landing processor. 1759 CK_KNL, 1760 1761 /// \name K6 1762 /// K6 architecture processors. 1763 //@{ 1764 CK_K6, 1765 CK_K6_2, 1766 CK_K6_3, 1767 //@} 1768 1769 /// \name K7 1770 /// K7 architecture processors. 1771 //@{ 1772 CK_Athlon, 1773 CK_AthlonThunderbird, 1774 CK_Athlon4, 1775 CK_AthlonXP, 1776 CK_AthlonMP, 1777 //@} 1778 1779 /// \name K8 1780 /// K8 architecture processors. 1781 //@{ 1782 CK_Athlon64, 1783 CK_Athlon64SSE3, 1784 CK_AthlonFX, 1785 CK_K8, 1786 CK_K8SSE3, 1787 CK_Opteron, 1788 CK_OpteronSSE3, 1789 CK_AMDFAM10, 1790 //@} 1791 1792 /// \name Bobcat 1793 /// Bobcat architecture processors. 1794 //@{ 1795 CK_BTVER1, 1796 CK_BTVER2, 1797 //@} 1798 1799 /// \name Bulldozer 1800 /// Bulldozer architecture processors. 1801 //@{ 1802 CK_BDVER1, 1803 CK_BDVER2, 1804 CK_BDVER3, 1805 CK_BDVER4, 1806 //@} 1807 1808 /// This specification is deprecated and will be removed in the future. 1809 /// Users should prefer \see CK_K8. 1810 // FIXME: Warn on this when the CPU is set to it. 1811 CK_x86_64, 1812 //@} 1813 1814 /// \name Geode 1815 /// Geode processors. 1816 //@{ 1817 CK_Geode 1818 //@} 1819 } CPU; 1820 1821 enum FPMathKind { 1822 FP_Default, 1823 FP_SSE, 1824 FP_387 1825 } FPMath; 1826 1827 public: 1828 X86TargetInfo(const llvm::Triple &Triple) 1829 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1830 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1831 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1832 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1833 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1834 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1835 FPMath(FP_Default) { 1836 BigEndian = false; 1837 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1838 } 1839 unsigned getFloatEvalMethod() const override { 1840 // X87 evaluates with 80 bits "long double" precision. 1841 return SSELevel == NoSSE ? 2 : 0; 1842 } 1843 void getTargetBuiltins(const Builtin::Info *&Records, 1844 unsigned &NumRecords) const override { 1845 Records = BuiltinInfo; 1846 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1847 } 1848 void getGCCRegNames(const char * const *&Names, 1849 unsigned &NumNames) const override { 1850 Names = GCCRegNames; 1851 NumNames = llvm::array_lengthof(GCCRegNames); 1852 } 1853 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1854 unsigned &NumAliases) const override { 1855 Aliases = nullptr; 1856 NumAliases = 0; 1857 } 1858 void getGCCAddlRegNames(const AddlRegName *&Names, 1859 unsigned &NumNames) const override { 1860 Names = AddlRegNames; 1861 NumNames = llvm::array_lengthof(AddlRegNames); 1862 } 1863 bool validateAsmConstraint(const char *&Name, 1864 TargetInfo::ConstraintInfo &info) const override; 1865 std::string convertConstraint(const char *&Constraint) const override; 1866 const char *getClobbers() const override { 1867 return "~{dirflag},~{fpsr},~{flags}"; 1868 } 1869 void getTargetDefines(const LangOptions &Opts, 1870 MacroBuilder &Builder) const override; 1871 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1872 bool Enabled); 1873 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1874 bool Enabled); 1875 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1876 bool Enabled); 1877 void setFeatureEnabled(llvm::StringMap<bool> &Features, 1878 StringRef Name, bool Enabled) const override { 1879 setFeatureEnabledImpl(Features, Name, Enabled); 1880 } 1881 // This exists purely to cut down on the number of virtual calls in 1882 // getDefaultFeatures which calls this repeatedly. 1883 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1884 StringRef Name, bool Enabled); 1885 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 1886 bool hasFeature(StringRef Feature) const override; 1887 bool handleTargetFeatures(std::vector<std::string> &Features, 1888 DiagnosticsEngine &Diags) override; 1889 StringRef getABI() const override { 1890 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1891 return "avx"; 1892 else if (getTriple().getArch() == llvm::Triple::x86 && 1893 MMX3DNowLevel == NoMMX3DNow) 1894 return "no-mmx"; 1895 return ""; 1896 } 1897 bool setCPU(const std::string &Name) override { 1898 CPU = llvm::StringSwitch<CPUKind>(Name) 1899 .Case("i386", CK_i386) 1900 .Case("i486", CK_i486) 1901 .Case("winchip-c6", CK_WinChipC6) 1902 .Case("winchip2", CK_WinChip2) 1903 .Case("c3", CK_C3) 1904 .Case("i586", CK_i586) 1905 .Case("pentium", CK_Pentium) 1906 .Case("pentium-mmx", CK_PentiumMMX) 1907 .Case("i686", CK_i686) 1908 .Case("pentiumpro", CK_PentiumPro) 1909 .Case("pentium2", CK_Pentium2) 1910 .Case("pentium3", CK_Pentium3) 1911 .Case("pentium3m", CK_Pentium3M) 1912 .Case("pentium-m", CK_PentiumM) 1913 .Case("c3-2", CK_C3_2) 1914 .Case("yonah", CK_Yonah) 1915 .Case("pentium4", CK_Pentium4) 1916 .Case("pentium4m", CK_Pentium4M) 1917 .Case("prescott", CK_Prescott) 1918 .Case("nocona", CK_Nocona) 1919 .Case("core2", CK_Core2) 1920 .Case("penryn", CK_Penryn) 1921 .Case("atom", CK_Atom) 1922 .Case("slm", CK_Silvermont) 1923 .Case("corei7", CK_Corei7) 1924 .Case("corei7-avx", CK_Corei7AVX) 1925 .Case("core-avx-i", CK_CoreAVXi) 1926 .Case("core-avx2", CK_CoreAVX2) 1927 .Case("knl", CK_KNL) 1928 .Case("k6", CK_K6) 1929 .Case("k6-2", CK_K6_2) 1930 .Case("k6-3", CK_K6_3) 1931 .Case("athlon", CK_Athlon) 1932 .Case("athlon-tbird", CK_AthlonThunderbird) 1933 .Case("athlon-4", CK_Athlon4) 1934 .Case("athlon-xp", CK_AthlonXP) 1935 .Case("athlon-mp", CK_AthlonMP) 1936 .Case("athlon64", CK_Athlon64) 1937 .Case("athlon64-sse3", CK_Athlon64SSE3) 1938 .Case("athlon-fx", CK_AthlonFX) 1939 .Case("k8", CK_K8) 1940 .Case("k8-sse3", CK_K8SSE3) 1941 .Case("opteron", CK_Opteron) 1942 .Case("opteron-sse3", CK_OpteronSSE3) 1943 .Case("amdfam10", CK_AMDFAM10) 1944 .Case("btver1", CK_BTVER1) 1945 .Case("btver2", CK_BTVER2) 1946 .Case("bdver1", CK_BDVER1) 1947 .Case("bdver2", CK_BDVER2) 1948 .Case("bdver3", CK_BDVER3) 1949 .Case("bdver4", CK_BDVER4) 1950 .Case("x86-64", CK_x86_64) 1951 .Case("geode", CK_Geode) 1952 .Default(CK_Generic); 1953 1954 // Perform any per-CPU checks necessary to determine if this CPU is 1955 // acceptable. 1956 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1957 // invalid without explaining *why*. 1958 switch (CPU) { 1959 case CK_Generic: 1960 // No processor selected! 1961 return false; 1962 1963 case CK_i386: 1964 case CK_i486: 1965 case CK_WinChipC6: 1966 case CK_WinChip2: 1967 case CK_C3: 1968 case CK_i586: 1969 case CK_Pentium: 1970 case CK_PentiumMMX: 1971 case CK_i686: 1972 case CK_PentiumPro: 1973 case CK_Pentium2: 1974 case CK_Pentium3: 1975 case CK_Pentium3M: 1976 case CK_PentiumM: 1977 case CK_Yonah: 1978 case CK_C3_2: 1979 case CK_Pentium4: 1980 case CK_Pentium4M: 1981 case CK_Prescott: 1982 case CK_K6: 1983 case CK_K6_2: 1984 case CK_K6_3: 1985 case CK_Athlon: 1986 case CK_AthlonThunderbird: 1987 case CK_Athlon4: 1988 case CK_AthlonXP: 1989 case CK_AthlonMP: 1990 case CK_Geode: 1991 // Only accept certain architectures when compiling in 32-bit mode. 1992 if (getTriple().getArch() != llvm::Triple::x86) 1993 return false; 1994 1995 // Fallthrough 1996 case CK_Nocona: 1997 case CK_Core2: 1998 case CK_Penryn: 1999 case CK_Atom: 2000 case CK_Silvermont: 2001 case CK_Corei7: 2002 case CK_Corei7AVX: 2003 case CK_CoreAVXi: 2004 case CK_CoreAVX2: 2005 case CK_KNL: 2006 case CK_Athlon64: 2007 case CK_Athlon64SSE3: 2008 case CK_AthlonFX: 2009 case CK_K8: 2010 case CK_K8SSE3: 2011 case CK_Opteron: 2012 case CK_OpteronSSE3: 2013 case CK_AMDFAM10: 2014 case CK_BTVER1: 2015 case CK_BTVER2: 2016 case CK_BDVER1: 2017 case CK_BDVER2: 2018 case CK_BDVER3: 2019 case CK_BDVER4: 2020 case CK_x86_64: 2021 return true; 2022 } 2023 llvm_unreachable("Unhandled CPU kind"); 2024 } 2025 2026 bool setFPMath(StringRef Name) override; 2027 2028 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2029 // We accept all non-ARM calling conventions 2030 return (CC == CC_X86ThisCall || 2031 CC == CC_X86FastCall || 2032 CC == CC_X86StdCall || 2033 CC == CC_C || 2034 CC == CC_X86Pascal || 2035 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2036 } 2037 2038 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2039 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2040 } 2041 }; 2042 2043 bool X86TargetInfo::setFPMath(StringRef Name) { 2044 if (Name == "387") { 2045 FPMath = FP_387; 2046 return true; 2047 } 2048 if (Name == "sse") { 2049 FPMath = FP_SSE; 2050 return true; 2051 } 2052 return false; 2053 } 2054 2055 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2056 // FIXME: This *really* should not be here. 2057 2058 // X86_64 always has SSE2. 2059 if (getTriple().getArch() == llvm::Triple::x86_64) 2060 setFeatureEnabledImpl(Features, "sse2", true); 2061 2062 switch (CPU) { 2063 case CK_Generic: 2064 case CK_i386: 2065 case CK_i486: 2066 case CK_i586: 2067 case CK_Pentium: 2068 case CK_i686: 2069 case CK_PentiumPro: 2070 break; 2071 case CK_PentiumMMX: 2072 case CK_Pentium2: 2073 setFeatureEnabledImpl(Features, "mmx", true); 2074 break; 2075 case CK_Pentium3: 2076 case CK_Pentium3M: 2077 setFeatureEnabledImpl(Features, "sse", true); 2078 break; 2079 case CK_PentiumM: 2080 case CK_Pentium4: 2081 case CK_Pentium4M: 2082 case CK_x86_64: 2083 setFeatureEnabledImpl(Features, "sse2", true); 2084 break; 2085 case CK_Yonah: 2086 case CK_Prescott: 2087 case CK_Nocona: 2088 setFeatureEnabledImpl(Features, "sse3", true); 2089 setFeatureEnabledImpl(Features, "cx16", true); 2090 break; 2091 case CK_Core2: 2092 setFeatureEnabledImpl(Features, "ssse3", true); 2093 setFeatureEnabledImpl(Features, "cx16", true); 2094 break; 2095 case CK_Penryn: 2096 setFeatureEnabledImpl(Features, "sse4.1", true); 2097 setFeatureEnabledImpl(Features, "cx16", true); 2098 break; 2099 case CK_Atom: 2100 setFeatureEnabledImpl(Features, "ssse3", true); 2101 setFeatureEnabledImpl(Features, "cx16", true); 2102 break; 2103 case CK_Silvermont: 2104 setFeatureEnabledImpl(Features, "sse4.2", true); 2105 setFeatureEnabledImpl(Features, "aes", true); 2106 setFeatureEnabledImpl(Features, "cx16", true); 2107 setFeatureEnabledImpl(Features, "pclmul", true); 2108 break; 2109 case CK_Corei7: 2110 setFeatureEnabledImpl(Features, "sse4.2", true); 2111 setFeatureEnabledImpl(Features, "cx16", true); 2112 break; 2113 case CK_Corei7AVX: 2114 setFeatureEnabledImpl(Features, "avx", true); 2115 setFeatureEnabledImpl(Features, "aes", true); 2116 setFeatureEnabledImpl(Features, "cx16", true); 2117 setFeatureEnabledImpl(Features, "pclmul", true); 2118 break; 2119 case CK_CoreAVXi: 2120 setFeatureEnabledImpl(Features, "avx", true); 2121 setFeatureEnabledImpl(Features, "aes", true); 2122 setFeatureEnabledImpl(Features, "pclmul", true); 2123 setFeatureEnabledImpl(Features, "rdrnd", true); 2124 setFeatureEnabledImpl(Features, "f16c", true); 2125 break; 2126 case CK_CoreAVX2: 2127 setFeatureEnabledImpl(Features, "avx2", true); 2128 setFeatureEnabledImpl(Features, "aes", true); 2129 setFeatureEnabledImpl(Features, "pclmul", true); 2130 setFeatureEnabledImpl(Features, "lzcnt", true); 2131 setFeatureEnabledImpl(Features, "rdrnd", true); 2132 setFeatureEnabledImpl(Features, "f16c", true); 2133 setFeatureEnabledImpl(Features, "bmi", true); 2134 setFeatureEnabledImpl(Features, "bmi2", true); 2135 setFeatureEnabledImpl(Features, "rtm", true); 2136 setFeatureEnabledImpl(Features, "fma", true); 2137 setFeatureEnabledImpl(Features, "cx16", true); 2138 break; 2139 case CK_KNL: 2140 setFeatureEnabledImpl(Features, "avx512f", true); 2141 setFeatureEnabledImpl(Features, "avx512cd", true); 2142 setFeatureEnabledImpl(Features, "avx512er", true); 2143 setFeatureEnabledImpl(Features, "avx512pf", true); 2144 setFeatureEnabledImpl(Features, "aes", true); 2145 setFeatureEnabledImpl(Features, "pclmul", true); 2146 setFeatureEnabledImpl(Features, "lzcnt", true); 2147 setFeatureEnabledImpl(Features, "rdrnd", true); 2148 setFeatureEnabledImpl(Features, "f16c", true); 2149 setFeatureEnabledImpl(Features, "bmi", true); 2150 setFeatureEnabledImpl(Features, "bmi2", true); 2151 setFeatureEnabledImpl(Features, "rtm", true); 2152 setFeatureEnabledImpl(Features, "fma", true); 2153 break; 2154 case CK_K6: 2155 case CK_WinChipC6: 2156 setFeatureEnabledImpl(Features, "mmx", true); 2157 break; 2158 case CK_K6_2: 2159 case CK_K6_3: 2160 case CK_WinChip2: 2161 case CK_C3: 2162 setFeatureEnabledImpl(Features, "3dnow", true); 2163 break; 2164 case CK_Athlon: 2165 case CK_AthlonThunderbird: 2166 case CK_Geode: 2167 setFeatureEnabledImpl(Features, "3dnowa", true); 2168 break; 2169 case CK_Athlon4: 2170 case CK_AthlonXP: 2171 case CK_AthlonMP: 2172 setFeatureEnabledImpl(Features, "sse", true); 2173 setFeatureEnabledImpl(Features, "3dnowa", true); 2174 break; 2175 case CK_K8: 2176 case CK_Opteron: 2177 case CK_Athlon64: 2178 case CK_AthlonFX: 2179 setFeatureEnabledImpl(Features, "sse2", true); 2180 setFeatureEnabledImpl(Features, "3dnowa", true); 2181 break; 2182 case CK_K8SSE3: 2183 case CK_OpteronSSE3: 2184 case CK_Athlon64SSE3: 2185 setFeatureEnabledImpl(Features, "sse3", true); 2186 setFeatureEnabledImpl(Features, "3dnowa", true); 2187 break; 2188 case CK_AMDFAM10: 2189 setFeatureEnabledImpl(Features, "sse3", true); 2190 setFeatureEnabledImpl(Features, "sse4a", true); 2191 setFeatureEnabledImpl(Features, "3dnowa", true); 2192 setFeatureEnabledImpl(Features, "lzcnt", true); 2193 setFeatureEnabledImpl(Features, "popcnt", true); 2194 break; 2195 case CK_BTVER1: 2196 setFeatureEnabledImpl(Features, "ssse3", true); 2197 setFeatureEnabledImpl(Features, "sse4a", true); 2198 setFeatureEnabledImpl(Features, "cx16", true); 2199 setFeatureEnabledImpl(Features, "lzcnt", true); 2200 setFeatureEnabledImpl(Features, "popcnt", true); 2201 setFeatureEnabledImpl(Features, "prfchw", true); 2202 break; 2203 case CK_BTVER2: 2204 setFeatureEnabledImpl(Features, "avx", true); 2205 setFeatureEnabledImpl(Features, "sse4a", true); 2206 setFeatureEnabledImpl(Features, "lzcnt", true); 2207 setFeatureEnabledImpl(Features, "aes", true); 2208 setFeatureEnabledImpl(Features, "pclmul", true); 2209 setFeatureEnabledImpl(Features, "prfchw", true); 2210 setFeatureEnabledImpl(Features, "bmi", true); 2211 setFeatureEnabledImpl(Features, "f16c", true); 2212 setFeatureEnabledImpl(Features, "cx16", true); 2213 break; 2214 case CK_BDVER1: 2215 setFeatureEnabledImpl(Features, "xop", true); 2216 setFeatureEnabledImpl(Features, "lzcnt", true); 2217 setFeatureEnabledImpl(Features, "aes", true); 2218 setFeatureEnabledImpl(Features, "pclmul", true); 2219 setFeatureEnabledImpl(Features, "prfchw", true); 2220 setFeatureEnabledImpl(Features, "cx16", true); 2221 break; 2222 case CK_BDVER4: 2223 setFeatureEnabledImpl(Features, "avx2", true); 2224 setFeatureEnabledImpl(Features, "bmi2", true); 2225 // FALLTHROUGH 2226 case CK_BDVER2: 2227 case CK_BDVER3: 2228 setFeatureEnabledImpl(Features, "xop", true); 2229 setFeatureEnabledImpl(Features, "lzcnt", true); 2230 setFeatureEnabledImpl(Features, "aes", true); 2231 setFeatureEnabledImpl(Features, "pclmul", true); 2232 setFeatureEnabledImpl(Features, "prfchw", true); 2233 setFeatureEnabledImpl(Features, "bmi", true); 2234 setFeatureEnabledImpl(Features, "fma", true); 2235 setFeatureEnabledImpl(Features, "f16c", true); 2236 setFeatureEnabledImpl(Features, "tbm", true); 2237 setFeatureEnabledImpl(Features, "cx16", true); 2238 break; 2239 case CK_C3_2: 2240 setFeatureEnabledImpl(Features, "sse", true); 2241 break; 2242 } 2243 } 2244 2245 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2246 X86SSEEnum Level, bool Enabled) { 2247 if (Enabled) { 2248 switch (Level) { 2249 case AVX512F: 2250 Features["avx512f"] = true; 2251 case AVX2: 2252 Features["avx2"] = true; 2253 case AVX: 2254 Features["avx"] = true; 2255 case SSE42: 2256 Features["sse4.2"] = true; 2257 case SSE41: 2258 Features["sse4.1"] = true; 2259 case SSSE3: 2260 Features["ssse3"] = true; 2261 case SSE3: 2262 Features["sse3"] = true; 2263 case SSE2: 2264 Features["sse2"] = true; 2265 case SSE1: 2266 Features["sse"] = true; 2267 case NoSSE: 2268 break; 2269 } 2270 return; 2271 } 2272 2273 switch (Level) { 2274 case NoSSE: 2275 case SSE1: 2276 Features["sse"] = false; 2277 case SSE2: 2278 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2279 Features["sha"] = false; 2280 case SSE3: 2281 Features["sse3"] = false; 2282 setXOPLevel(Features, NoXOP, false); 2283 case SSSE3: 2284 Features["ssse3"] = false; 2285 case SSE41: 2286 Features["sse4.1"] = false; 2287 case SSE42: 2288 Features["sse4.2"] = false; 2289 case AVX: 2290 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2291 setXOPLevel(Features, FMA4, false); 2292 case AVX2: 2293 Features["avx2"] = false; 2294 case AVX512F: 2295 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2296 Features["avx512pf"] = false; 2297 } 2298 } 2299 2300 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2301 MMX3DNowEnum Level, bool Enabled) { 2302 if (Enabled) { 2303 switch (Level) { 2304 case AMD3DNowAthlon: 2305 Features["3dnowa"] = true; 2306 case AMD3DNow: 2307 Features["3dnow"] = true; 2308 case MMX: 2309 Features["mmx"] = true; 2310 case NoMMX3DNow: 2311 break; 2312 } 2313 return; 2314 } 2315 2316 switch (Level) { 2317 case NoMMX3DNow: 2318 case MMX: 2319 Features["mmx"] = false; 2320 case AMD3DNow: 2321 Features["3dnow"] = false; 2322 case AMD3DNowAthlon: 2323 Features["3dnowa"] = false; 2324 } 2325 } 2326 2327 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2328 bool Enabled) { 2329 if (Enabled) { 2330 switch (Level) { 2331 case XOP: 2332 Features["xop"] = true; 2333 case FMA4: 2334 Features["fma4"] = true; 2335 setSSELevel(Features, AVX, true); 2336 case SSE4A: 2337 Features["sse4a"] = true; 2338 setSSELevel(Features, SSE3, true); 2339 case NoXOP: 2340 break; 2341 } 2342 return; 2343 } 2344 2345 switch (Level) { 2346 case NoXOP: 2347 case SSE4A: 2348 Features["sse4a"] = false; 2349 case FMA4: 2350 Features["fma4"] = false; 2351 case XOP: 2352 Features["xop"] = false; 2353 } 2354 } 2355 2356 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2357 StringRef Name, bool Enabled) { 2358 // FIXME: This *really* should not be here. We need some way of translating 2359 // options into llvm subtarget features. 2360 if (Name == "sse4") 2361 Name = "sse4.2"; 2362 2363 Features[Name] = Enabled; 2364 2365 if (Name == "mmx") { 2366 setMMXLevel(Features, MMX, Enabled); 2367 } else if (Name == "sse") { 2368 setSSELevel(Features, SSE1, Enabled); 2369 } else if (Name == "sse2") { 2370 setSSELevel(Features, SSE2, Enabled); 2371 } else if (Name == "sse3") { 2372 setSSELevel(Features, SSE3, Enabled); 2373 } else if (Name == "ssse3") { 2374 setSSELevel(Features, SSSE3, Enabled); 2375 } else if (Name == "sse4.2") { 2376 setSSELevel(Features, SSE42, Enabled); 2377 } else if (Name == "sse4.1") { 2378 setSSELevel(Features, SSE41, Enabled); 2379 } else if (Name == "3dnow") { 2380 setMMXLevel(Features, AMD3DNow, Enabled); 2381 } else if (Name == "3dnowa") { 2382 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2383 } else if (Name == "aes") { 2384 if (Enabled) 2385 setSSELevel(Features, SSE2, Enabled); 2386 } else if (Name == "pclmul") { 2387 if (Enabled) 2388 setSSELevel(Features, SSE2, Enabled); 2389 } else if (Name == "avx") { 2390 setSSELevel(Features, AVX, Enabled); 2391 } else if (Name == "avx2") { 2392 setSSELevel(Features, AVX2, Enabled); 2393 } else if (Name == "avx512f") { 2394 setSSELevel(Features, AVX512F, Enabled); 2395 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2396 if (Enabled) 2397 setSSELevel(Features, AVX512F, Enabled); 2398 } else if (Name == "fma") { 2399 if (Enabled) 2400 setSSELevel(Features, AVX, Enabled); 2401 } else if (Name == "fma4") { 2402 setXOPLevel(Features, FMA4, Enabled); 2403 } else if (Name == "xop") { 2404 setXOPLevel(Features, XOP, Enabled); 2405 } else if (Name == "sse4a") { 2406 setXOPLevel(Features, SSE4A, Enabled); 2407 } else if (Name == "f16c") { 2408 if (Enabled) 2409 setSSELevel(Features, AVX, Enabled); 2410 } else if (Name == "sha") { 2411 if (Enabled) 2412 setSSELevel(Features, SSE2, Enabled); 2413 } 2414 } 2415 2416 /// handleTargetFeatures - Perform initialization based on the user 2417 /// configured set of features. 2418 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2419 DiagnosticsEngine &Diags) { 2420 // Remember the maximum enabled sselevel. 2421 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2422 // Ignore disabled features. 2423 if (Features[i][0] == '-') 2424 continue; 2425 2426 StringRef Feature = StringRef(Features[i]).substr(1); 2427 2428 if (Feature == "aes") { 2429 HasAES = true; 2430 continue; 2431 } 2432 2433 if (Feature == "pclmul") { 2434 HasPCLMUL = true; 2435 continue; 2436 } 2437 2438 if (Feature == "lzcnt") { 2439 HasLZCNT = true; 2440 continue; 2441 } 2442 2443 if (Feature == "rdrnd") { 2444 HasRDRND = true; 2445 continue; 2446 } 2447 2448 if (Feature == "bmi") { 2449 HasBMI = true; 2450 continue; 2451 } 2452 2453 if (Feature == "bmi2") { 2454 HasBMI2 = true; 2455 continue; 2456 } 2457 2458 if (Feature == "popcnt") { 2459 HasPOPCNT = true; 2460 continue; 2461 } 2462 2463 if (Feature == "rtm") { 2464 HasRTM = true; 2465 continue; 2466 } 2467 2468 if (Feature == "prfchw") { 2469 HasPRFCHW = true; 2470 continue; 2471 } 2472 2473 if (Feature == "rdseed") { 2474 HasRDSEED = true; 2475 continue; 2476 } 2477 2478 if (Feature == "tbm") { 2479 HasTBM = true; 2480 continue; 2481 } 2482 2483 if (Feature == "fma") { 2484 HasFMA = true; 2485 continue; 2486 } 2487 2488 if (Feature == "f16c") { 2489 HasF16C = true; 2490 continue; 2491 } 2492 2493 if (Feature == "avx512cd") { 2494 HasAVX512CD = true; 2495 continue; 2496 } 2497 2498 if (Feature == "avx512er") { 2499 HasAVX512ER = true; 2500 continue; 2501 } 2502 2503 if (Feature == "avx512pf") { 2504 HasAVX512PF = true; 2505 continue; 2506 } 2507 2508 if (Feature == "sha") { 2509 HasSHA = true; 2510 continue; 2511 } 2512 2513 if (Feature == "cx16") { 2514 HasCX16 = true; 2515 continue; 2516 } 2517 2518 assert(Features[i][0] == '+' && "Invalid target feature!"); 2519 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2520 .Case("avx512f", AVX512F) 2521 .Case("avx2", AVX2) 2522 .Case("avx", AVX) 2523 .Case("sse4.2", SSE42) 2524 .Case("sse4.1", SSE41) 2525 .Case("ssse3", SSSE3) 2526 .Case("sse3", SSE3) 2527 .Case("sse2", SSE2) 2528 .Case("sse", SSE1) 2529 .Default(NoSSE); 2530 SSELevel = std::max(SSELevel, Level); 2531 2532 MMX3DNowEnum ThreeDNowLevel = 2533 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2534 .Case("3dnowa", AMD3DNowAthlon) 2535 .Case("3dnow", AMD3DNow) 2536 .Case("mmx", MMX) 2537 .Default(NoMMX3DNow); 2538 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2539 2540 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2541 .Case("xop", XOP) 2542 .Case("fma4", FMA4) 2543 .Case("sse4a", SSE4A) 2544 .Default(NoXOP); 2545 XOPLevel = std::max(XOPLevel, XLevel); 2546 } 2547 2548 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2549 // Can't do this earlier because we need to be able to explicitly enable 2550 // popcnt and still disable sse4.2. 2551 if (!HasPOPCNT && SSELevel >= SSE42 && 2552 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2553 HasPOPCNT = true; 2554 Features.push_back("+popcnt"); 2555 } 2556 2557 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2558 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2559 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2560 HasPRFCHW = true; 2561 Features.push_back("+prfchw"); 2562 } 2563 2564 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2565 // matches the selected sse level. 2566 if (FPMath == FP_SSE && SSELevel < SSE1) { 2567 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2568 return false; 2569 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2570 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2571 return false; 2572 } 2573 2574 // Don't tell the backend if we're turning off mmx; it will end up disabling 2575 // SSE, which we don't want. 2576 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2577 // then enable MMX. 2578 std::vector<std::string>::iterator it; 2579 it = std::find(Features.begin(), Features.end(), "-mmx"); 2580 if (it != Features.end()) 2581 Features.erase(it); 2582 else if (SSELevel > NoSSE) 2583 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2584 return true; 2585 } 2586 2587 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2588 /// definitions for this particular subtarget. 2589 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2590 MacroBuilder &Builder) const { 2591 // Target identification. 2592 if (getTriple().getArch() == llvm::Triple::x86_64) { 2593 Builder.defineMacro("__amd64__"); 2594 Builder.defineMacro("__amd64"); 2595 Builder.defineMacro("__x86_64"); 2596 Builder.defineMacro("__x86_64__"); 2597 } else { 2598 DefineStd(Builder, "i386", Opts); 2599 } 2600 2601 // Subtarget options. 2602 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2603 // truly should be based on -mtune options. 2604 switch (CPU) { 2605 case CK_Generic: 2606 break; 2607 case CK_i386: 2608 // The rest are coming from the i386 define above. 2609 Builder.defineMacro("__tune_i386__"); 2610 break; 2611 case CK_i486: 2612 case CK_WinChipC6: 2613 case CK_WinChip2: 2614 case CK_C3: 2615 defineCPUMacros(Builder, "i486"); 2616 break; 2617 case CK_PentiumMMX: 2618 Builder.defineMacro("__pentium_mmx__"); 2619 Builder.defineMacro("__tune_pentium_mmx__"); 2620 // Fallthrough 2621 case CK_i586: 2622 case CK_Pentium: 2623 defineCPUMacros(Builder, "i586"); 2624 defineCPUMacros(Builder, "pentium"); 2625 break; 2626 case CK_Pentium3: 2627 case CK_Pentium3M: 2628 case CK_PentiumM: 2629 Builder.defineMacro("__tune_pentium3__"); 2630 // Fallthrough 2631 case CK_Pentium2: 2632 case CK_C3_2: 2633 Builder.defineMacro("__tune_pentium2__"); 2634 // Fallthrough 2635 case CK_PentiumPro: 2636 Builder.defineMacro("__tune_i686__"); 2637 Builder.defineMacro("__tune_pentiumpro__"); 2638 // Fallthrough 2639 case CK_i686: 2640 Builder.defineMacro("__i686"); 2641 Builder.defineMacro("__i686__"); 2642 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2643 Builder.defineMacro("__pentiumpro"); 2644 Builder.defineMacro("__pentiumpro__"); 2645 break; 2646 case CK_Pentium4: 2647 case CK_Pentium4M: 2648 defineCPUMacros(Builder, "pentium4"); 2649 break; 2650 case CK_Yonah: 2651 case CK_Prescott: 2652 case CK_Nocona: 2653 defineCPUMacros(Builder, "nocona"); 2654 break; 2655 case CK_Core2: 2656 case CK_Penryn: 2657 defineCPUMacros(Builder, "core2"); 2658 break; 2659 case CK_Atom: 2660 defineCPUMacros(Builder, "atom"); 2661 break; 2662 case CK_Silvermont: 2663 defineCPUMacros(Builder, "slm"); 2664 break; 2665 case CK_Corei7: 2666 case CK_Corei7AVX: 2667 case CK_CoreAVXi: 2668 case CK_CoreAVX2: 2669 defineCPUMacros(Builder, "corei7"); 2670 break; 2671 case CK_KNL: 2672 defineCPUMacros(Builder, "knl"); 2673 break; 2674 case CK_K6_2: 2675 Builder.defineMacro("__k6_2__"); 2676 Builder.defineMacro("__tune_k6_2__"); 2677 // Fallthrough 2678 case CK_K6_3: 2679 if (CPU != CK_K6_2) { // In case of fallthrough 2680 // FIXME: GCC may be enabling these in cases where some other k6 2681 // architecture is specified but -m3dnow is explicitly provided. The 2682 // exact semantics need to be determined and emulated here. 2683 Builder.defineMacro("__k6_3__"); 2684 Builder.defineMacro("__tune_k6_3__"); 2685 } 2686 // Fallthrough 2687 case CK_K6: 2688 defineCPUMacros(Builder, "k6"); 2689 break; 2690 case CK_Athlon: 2691 case CK_AthlonThunderbird: 2692 case CK_Athlon4: 2693 case CK_AthlonXP: 2694 case CK_AthlonMP: 2695 defineCPUMacros(Builder, "athlon"); 2696 if (SSELevel != NoSSE) { 2697 Builder.defineMacro("__athlon_sse__"); 2698 Builder.defineMacro("__tune_athlon_sse__"); 2699 } 2700 break; 2701 case CK_K8: 2702 case CK_K8SSE3: 2703 case CK_x86_64: 2704 case CK_Opteron: 2705 case CK_OpteronSSE3: 2706 case CK_Athlon64: 2707 case CK_Athlon64SSE3: 2708 case CK_AthlonFX: 2709 defineCPUMacros(Builder, "k8"); 2710 break; 2711 case CK_AMDFAM10: 2712 defineCPUMacros(Builder, "amdfam10"); 2713 break; 2714 case CK_BTVER1: 2715 defineCPUMacros(Builder, "btver1"); 2716 break; 2717 case CK_BTVER2: 2718 defineCPUMacros(Builder, "btver2"); 2719 break; 2720 case CK_BDVER1: 2721 defineCPUMacros(Builder, "bdver1"); 2722 break; 2723 case CK_BDVER2: 2724 defineCPUMacros(Builder, "bdver2"); 2725 break; 2726 case CK_BDVER3: 2727 defineCPUMacros(Builder, "bdver3"); 2728 break; 2729 case CK_BDVER4: 2730 defineCPUMacros(Builder, "bdver4"); 2731 break; 2732 case CK_Geode: 2733 defineCPUMacros(Builder, "geode"); 2734 break; 2735 } 2736 2737 // Target properties. 2738 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2739 2740 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2741 // functions in glibc header files that use FP Stack inline asm which the 2742 // backend can't deal with (PR879). 2743 Builder.defineMacro("__NO_MATH_INLINES"); 2744 2745 if (HasAES) 2746 Builder.defineMacro("__AES__"); 2747 2748 if (HasPCLMUL) 2749 Builder.defineMacro("__PCLMUL__"); 2750 2751 if (HasLZCNT) 2752 Builder.defineMacro("__LZCNT__"); 2753 2754 if (HasRDRND) 2755 Builder.defineMacro("__RDRND__"); 2756 2757 if (HasBMI) 2758 Builder.defineMacro("__BMI__"); 2759 2760 if (HasBMI2) 2761 Builder.defineMacro("__BMI2__"); 2762 2763 if (HasPOPCNT) 2764 Builder.defineMacro("__POPCNT__"); 2765 2766 if (HasRTM) 2767 Builder.defineMacro("__RTM__"); 2768 2769 if (HasPRFCHW) 2770 Builder.defineMacro("__PRFCHW__"); 2771 2772 if (HasRDSEED) 2773 Builder.defineMacro("__RDSEED__"); 2774 2775 if (HasTBM) 2776 Builder.defineMacro("__TBM__"); 2777 2778 switch (XOPLevel) { 2779 case XOP: 2780 Builder.defineMacro("__XOP__"); 2781 case FMA4: 2782 Builder.defineMacro("__FMA4__"); 2783 case SSE4A: 2784 Builder.defineMacro("__SSE4A__"); 2785 case NoXOP: 2786 break; 2787 } 2788 2789 if (HasFMA) 2790 Builder.defineMacro("__FMA__"); 2791 2792 if (HasF16C) 2793 Builder.defineMacro("__F16C__"); 2794 2795 if (HasAVX512CD) 2796 Builder.defineMacro("__AVX512CD__"); 2797 if (HasAVX512ER) 2798 Builder.defineMacro("__AVX512ER__"); 2799 if (HasAVX512PF) 2800 Builder.defineMacro("__AVX512PF__"); 2801 2802 if (HasSHA) 2803 Builder.defineMacro("__SHA__"); 2804 2805 if (HasCX16) 2806 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2807 2808 // Each case falls through to the previous one here. 2809 switch (SSELevel) { 2810 case AVX512F: 2811 Builder.defineMacro("__AVX512F__"); 2812 case AVX2: 2813 Builder.defineMacro("__AVX2__"); 2814 case AVX: 2815 Builder.defineMacro("__AVX__"); 2816 case SSE42: 2817 Builder.defineMacro("__SSE4_2__"); 2818 case SSE41: 2819 Builder.defineMacro("__SSE4_1__"); 2820 case SSSE3: 2821 Builder.defineMacro("__SSSE3__"); 2822 case SSE3: 2823 Builder.defineMacro("__SSE3__"); 2824 case SSE2: 2825 Builder.defineMacro("__SSE2__"); 2826 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2827 case SSE1: 2828 Builder.defineMacro("__SSE__"); 2829 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2830 case NoSSE: 2831 break; 2832 } 2833 2834 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2835 switch (SSELevel) { 2836 case AVX512F: 2837 case AVX2: 2838 case AVX: 2839 case SSE42: 2840 case SSE41: 2841 case SSSE3: 2842 case SSE3: 2843 case SSE2: 2844 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2845 break; 2846 case SSE1: 2847 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2848 break; 2849 default: 2850 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2851 } 2852 } 2853 2854 // Each case falls through to the previous one here. 2855 switch (MMX3DNowLevel) { 2856 case AMD3DNowAthlon: 2857 Builder.defineMacro("__3dNOW_A__"); 2858 case AMD3DNow: 2859 Builder.defineMacro("__3dNOW__"); 2860 case MMX: 2861 Builder.defineMacro("__MMX__"); 2862 case NoMMX3DNow: 2863 break; 2864 } 2865 2866 if (CPU >= CK_i486) { 2867 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2868 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2869 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2870 } 2871 if (CPU >= CK_i586) 2872 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2873 } 2874 2875 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2876 return llvm::StringSwitch<bool>(Feature) 2877 .Case("aes", HasAES) 2878 .Case("avx", SSELevel >= AVX) 2879 .Case("avx2", SSELevel >= AVX2) 2880 .Case("avx512f", SSELevel >= AVX512F) 2881 .Case("avx512cd", HasAVX512CD) 2882 .Case("avx512er", HasAVX512ER) 2883 .Case("avx512pf", HasAVX512PF) 2884 .Case("bmi", HasBMI) 2885 .Case("bmi2", HasBMI2) 2886 .Case("cx16", HasCX16) 2887 .Case("f16c", HasF16C) 2888 .Case("fma", HasFMA) 2889 .Case("fma4", XOPLevel >= FMA4) 2890 .Case("tbm", HasTBM) 2891 .Case("lzcnt", HasLZCNT) 2892 .Case("rdrnd", HasRDRND) 2893 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2894 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2895 .Case("mmx", MMX3DNowLevel >= MMX) 2896 .Case("pclmul", HasPCLMUL) 2897 .Case("popcnt", HasPOPCNT) 2898 .Case("rtm", HasRTM) 2899 .Case("prfchw", HasPRFCHW) 2900 .Case("rdseed", HasRDSEED) 2901 .Case("sha", HasSHA) 2902 .Case("sse", SSELevel >= SSE1) 2903 .Case("sse2", SSELevel >= SSE2) 2904 .Case("sse3", SSELevel >= SSE3) 2905 .Case("ssse3", SSELevel >= SSSE3) 2906 .Case("sse4.1", SSELevel >= SSE41) 2907 .Case("sse4.2", SSELevel >= SSE42) 2908 .Case("sse4a", XOPLevel >= SSE4A) 2909 .Case("x86", true) 2910 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2911 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2912 .Case("xop", XOPLevel >= XOP) 2913 .Default(false); 2914 } 2915 2916 bool 2917 X86TargetInfo::validateAsmConstraint(const char *&Name, 2918 TargetInfo::ConstraintInfo &Info) const { 2919 switch (*Name) { 2920 default: return false; 2921 case 'Y': // first letter of a pair: 2922 switch (*(Name+1)) { 2923 default: return false; 2924 case '0': // First SSE register. 2925 case 't': // Any SSE register, when SSE2 is enabled. 2926 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2927 case 'm': // any MMX register, when inter-unit moves enabled. 2928 break; // falls through to setAllowsRegister. 2929 } 2930 case 'a': // eax. 2931 case 'b': // ebx. 2932 case 'c': // ecx. 2933 case 'd': // edx. 2934 case 'S': // esi. 2935 case 'D': // edi. 2936 case 'A': // edx:eax. 2937 case 'f': // any x87 floating point stack register. 2938 case 't': // top of floating point stack. 2939 case 'u': // second from top of floating point stack. 2940 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2941 case 'y': // Any MMX register. 2942 case 'x': // Any SSE register. 2943 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2944 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2945 case 'l': // "Index" registers: any general register that can be used as an 2946 // index in a base+index memory access. 2947 Info.setAllowsRegister(); 2948 return true; 2949 case 'C': // SSE floating point constant. 2950 case 'G': // x87 floating point constant. 2951 case 'e': // 32-bit signed integer constant for use with zero-extending 2952 // x86_64 instructions. 2953 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2954 // x86_64 instructions. 2955 return true; 2956 } 2957 } 2958 2959 2960 std::string 2961 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2962 switch (*Constraint) { 2963 case 'a': return std::string("{ax}"); 2964 case 'b': return std::string("{bx}"); 2965 case 'c': return std::string("{cx}"); 2966 case 'd': return std::string("{dx}"); 2967 case 'S': return std::string("{si}"); 2968 case 'D': return std::string("{di}"); 2969 case 'p': // address 2970 return std::string("im"); 2971 case 't': // top of floating point stack. 2972 return std::string("{st}"); 2973 case 'u': // second from top of floating point stack. 2974 return std::string("{st(1)}"); // second from top of floating point stack. 2975 default: 2976 return std::string(1, *Constraint); 2977 } 2978 } 2979 } // end anonymous namespace 2980 2981 namespace { 2982 // X86-32 generic target 2983 class X86_32TargetInfo : public X86TargetInfo { 2984 public: 2985 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2986 DoubleAlign = LongLongAlign = 32; 2987 LongDoubleWidth = 96; 2988 LongDoubleAlign = 32; 2989 SuitableAlign = 128; 2990 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 2991 SizeType = UnsignedInt; 2992 PtrDiffType = SignedInt; 2993 IntPtrType = SignedInt; 2994 RegParmMax = 3; 2995 2996 // Use fpret for all types. 2997 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2998 (1 << TargetInfo::Double) | 2999 (1 << TargetInfo::LongDouble)); 3000 3001 // x86-32 has atomics up to 8 bytes 3002 // FIXME: Check that we actually have cmpxchg8b before setting 3003 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3004 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3005 } 3006 BuiltinVaListKind getBuiltinVaListKind() const override { 3007 return TargetInfo::CharPtrBuiltinVaList; 3008 } 3009 3010 int getEHDataRegisterNumber(unsigned RegNo) const override { 3011 if (RegNo == 0) return 0; 3012 if (RegNo == 1) return 2; 3013 return -1; 3014 } 3015 bool validateInputSize(StringRef Constraint, 3016 unsigned Size) const override { 3017 switch (Constraint[0]) { 3018 default: break; 3019 case 'a': 3020 case 'b': 3021 case 'c': 3022 case 'd': 3023 return Size <= 32; 3024 } 3025 3026 return true; 3027 } 3028 }; 3029 } // end anonymous namespace 3030 3031 namespace { 3032 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3033 public: 3034 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3035 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3036 3037 unsigned getFloatEvalMethod() const override { 3038 unsigned Major, Minor, Micro; 3039 getTriple().getOSVersion(Major, Minor, Micro); 3040 // New NetBSD uses the default rounding mode. 3041 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3042 return X86_32TargetInfo::getFloatEvalMethod(); 3043 // NetBSD before 6.99.26 defaults to "double" rounding. 3044 return 1; 3045 } 3046 }; 3047 } // end anonymous namespace 3048 3049 namespace { 3050 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3051 public: 3052 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3053 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3054 SizeType = UnsignedLong; 3055 IntPtrType = SignedLong; 3056 PtrDiffType = SignedLong; 3057 } 3058 }; 3059 } // end anonymous namespace 3060 3061 namespace { 3062 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3063 public: 3064 BitrigI386TargetInfo(const llvm::Triple &Triple) 3065 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3066 SizeType = UnsignedLong; 3067 IntPtrType = SignedLong; 3068 PtrDiffType = SignedLong; 3069 } 3070 }; 3071 } // end anonymous namespace 3072 3073 namespace { 3074 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3075 public: 3076 DarwinI386TargetInfo(const llvm::Triple &Triple) 3077 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3078 LongDoubleWidth = 128; 3079 LongDoubleAlign = 128; 3080 SuitableAlign = 128; 3081 MaxVectorAlign = 256; 3082 SizeType = UnsignedLong; 3083 IntPtrType = SignedLong; 3084 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3085 HasAlignMac68kSupport = true; 3086 } 3087 3088 }; 3089 } // end anonymous namespace 3090 3091 namespace { 3092 // x86-32 Windows target 3093 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3094 public: 3095 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3096 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3097 WCharType = UnsignedShort; 3098 DoubleAlign = LongLongAlign = 64; 3099 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3100 } 3101 void getTargetDefines(const LangOptions &Opts, 3102 MacroBuilder &Builder) const override { 3103 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3104 } 3105 }; 3106 3107 // x86-32 Windows Visual Studio target 3108 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3109 public: 3110 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3111 : WindowsX86_32TargetInfo(Triple) { 3112 LongDoubleWidth = LongDoubleAlign = 64; 3113 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3114 } 3115 void getTargetDefines(const LangOptions &Opts, 3116 MacroBuilder &Builder) const override { 3117 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3118 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3119 // The value of the following reflects processor type. 3120 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3121 // We lost the original triple, so we use the default. 3122 Builder.defineMacro("_M_IX86", "600"); 3123 } 3124 }; 3125 } // end anonymous namespace 3126 3127 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3128 Builder.defineMacro("__MSVCRT__"); 3129 Builder.defineMacro("__MINGW32__"); 3130 3131 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3132 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3133 // macro anyway for pre-processor compatibility. 3134 if (Opts.MicrosoftExt) 3135 Builder.defineMacro("__declspec", "__declspec"); 3136 else 3137 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3138 3139 if (!Opts.MicrosoftExt) { 3140 // Provide macros for all the calling convention keywords. Provide both 3141 // single and double underscore prefixed variants. These are available on 3142 // x64 as well as x86, even though they have no effect. 3143 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3144 for (const char *CC : CCs) { 3145 std::string GCCSpelling = "__attribute__((__"; 3146 GCCSpelling += CC; 3147 GCCSpelling += "__))"; 3148 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3149 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3150 } 3151 } 3152 } 3153 3154 namespace { 3155 // x86-32 MinGW target 3156 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3157 public: 3158 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3159 : WindowsX86_32TargetInfo(Triple) {} 3160 void getTargetDefines(const LangOptions &Opts, 3161 MacroBuilder &Builder) const override { 3162 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3163 DefineStd(Builder, "WIN32", Opts); 3164 DefineStd(Builder, "WINNT", Opts); 3165 Builder.defineMacro("_X86_"); 3166 addMinGWDefines(Opts, Builder); 3167 } 3168 }; 3169 } // end anonymous namespace 3170 3171 namespace { 3172 // x86-32 Cygwin target 3173 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3174 public: 3175 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3176 : X86_32TargetInfo(Triple) { 3177 TLSSupported = false; 3178 WCharType = UnsignedShort; 3179 DoubleAlign = LongLongAlign = 64; 3180 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3181 } 3182 void getTargetDefines(const LangOptions &Opts, 3183 MacroBuilder &Builder) const override { 3184 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3185 Builder.defineMacro("_X86_"); 3186 Builder.defineMacro("__CYGWIN__"); 3187 Builder.defineMacro("__CYGWIN32__"); 3188 DefineStd(Builder, "unix", Opts); 3189 if (Opts.CPlusPlus) 3190 Builder.defineMacro("_GNU_SOURCE"); 3191 } 3192 }; 3193 } // end anonymous namespace 3194 3195 namespace { 3196 // x86-32 Haiku target 3197 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3198 public: 3199 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3200 SizeType = UnsignedLong; 3201 IntPtrType = SignedLong; 3202 PtrDiffType = SignedLong; 3203 ProcessIDType = SignedLong; 3204 this->UserLabelPrefix = ""; 3205 this->TLSSupported = false; 3206 } 3207 void getTargetDefines(const LangOptions &Opts, 3208 MacroBuilder &Builder) const override { 3209 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3210 Builder.defineMacro("__INTEL__"); 3211 Builder.defineMacro("__HAIKU__"); 3212 } 3213 }; 3214 } // end anonymous namespace 3215 3216 // RTEMS Target 3217 template<typename Target> 3218 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3219 protected: 3220 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3221 MacroBuilder &Builder) const override { 3222 // RTEMS defines; list based off of gcc output 3223 3224 Builder.defineMacro("__rtems__"); 3225 Builder.defineMacro("__ELF__"); 3226 } 3227 3228 public: 3229 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3230 this->UserLabelPrefix = ""; 3231 3232 switch (Triple.getArch()) { 3233 default: 3234 case llvm::Triple::x86: 3235 // this->MCountName = ".mcount"; 3236 break; 3237 case llvm::Triple::mips: 3238 case llvm::Triple::mipsel: 3239 case llvm::Triple::ppc: 3240 case llvm::Triple::ppc64: 3241 case llvm::Triple::ppc64le: 3242 // this->MCountName = "_mcount"; 3243 break; 3244 case llvm::Triple::arm: 3245 // this->MCountName = "__mcount"; 3246 break; 3247 } 3248 } 3249 }; 3250 3251 namespace { 3252 // x86-32 RTEMS target 3253 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3254 public: 3255 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3256 SizeType = UnsignedLong; 3257 IntPtrType = SignedLong; 3258 PtrDiffType = SignedLong; 3259 this->UserLabelPrefix = ""; 3260 } 3261 void getTargetDefines(const LangOptions &Opts, 3262 MacroBuilder &Builder) const override { 3263 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3264 Builder.defineMacro("__INTEL__"); 3265 Builder.defineMacro("__rtems__"); 3266 } 3267 }; 3268 } // end anonymous namespace 3269 3270 namespace { 3271 // x86-64 generic target 3272 class X86_64TargetInfo : public X86TargetInfo { 3273 public: 3274 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3275 const bool IsX32{getTriple().getEnvironment() == llvm::Triple::GNUX32}; 3276 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3277 LongDoubleWidth = 128; 3278 LongDoubleAlign = 128; 3279 LargeArrayMinWidth = 128; 3280 LargeArrayAlign = 128; 3281 SuitableAlign = 128; 3282 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3283 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3284 IntPtrType = IsX32 ? SignedInt : SignedLong; 3285 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3286 UIntMaxType = IsX32 ? UnsignedLongLong : UnsignedLong; 3287 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3288 RegParmMax = 6; 3289 3290 DescriptionString = (IsX32) 3291 ? "e-m:e-" "p:32:32-" "i64:64-f80:128-n8:16:32:64-S128" 3292 : "e-m:e-" "i64:64-f80:128-n8:16:32:64-S128"; 3293 3294 // Use fpret only for long double. 3295 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3296 3297 // Use fp2ret for _Complex long double. 3298 ComplexLongDoubleUsesFP2Ret = true; 3299 3300 // x86-64 has atomics up to 16 bytes. 3301 MaxAtomicPromoteWidth = 128; 3302 MaxAtomicInlineWidth = 128; 3303 } 3304 BuiltinVaListKind getBuiltinVaListKind() const override { 3305 return TargetInfo::X86_64ABIBuiltinVaList; 3306 } 3307 3308 int getEHDataRegisterNumber(unsigned RegNo) const override { 3309 if (RegNo == 0) return 0; 3310 if (RegNo == 1) return 1; 3311 return -1; 3312 } 3313 3314 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3315 return (CC == CC_C || 3316 CC == CC_IntelOclBicc || 3317 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3318 } 3319 3320 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3321 return CC_C; 3322 } 3323 3324 }; 3325 } // end anonymous namespace 3326 3327 namespace { 3328 // x86-64 Windows target 3329 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3330 public: 3331 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3332 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3333 WCharType = UnsignedShort; 3334 LongWidth = LongAlign = 32; 3335 DoubleAlign = LongLongAlign = 64; 3336 IntMaxType = SignedLongLong; 3337 UIntMaxType = UnsignedLongLong; 3338 Int64Type = SignedLongLong; 3339 SizeType = UnsignedLongLong; 3340 PtrDiffType = SignedLongLong; 3341 IntPtrType = SignedLongLong; 3342 this->UserLabelPrefix = ""; 3343 } 3344 void getTargetDefines(const LangOptions &Opts, 3345 MacroBuilder &Builder) const override { 3346 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3347 Builder.defineMacro("_WIN64"); 3348 } 3349 BuiltinVaListKind getBuiltinVaListKind() const override { 3350 return TargetInfo::CharPtrBuiltinVaList; 3351 } 3352 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3353 return (CC == CC_C || 3354 CC == CC_IntelOclBicc || 3355 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3356 } 3357 }; 3358 } // end anonymous namespace 3359 3360 namespace { 3361 // x86-64 Windows Visual Studio target 3362 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3363 public: 3364 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3365 : WindowsX86_64TargetInfo(Triple) { 3366 LongDoubleWidth = LongDoubleAlign = 64; 3367 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3368 } 3369 void getTargetDefines(const LangOptions &Opts, 3370 MacroBuilder &Builder) const override { 3371 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3372 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3373 Builder.defineMacro("_M_X64"); 3374 Builder.defineMacro("_M_AMD64"); 3375 } 3376 }; 3377 } // end anonymous namespace 3378 3379 namespace { 3380 // x86-64 MinGW target 3381 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3382 public: 3383 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3384 : WindowsX86_64TargetInfo(Triple) {} 3385 void getTargetDefines(const LangOptions &Opts, 3386 MacroBuilder &Builder) const override { 3387 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3388 DefineStd(Builder, "WIN64", Opts); 3389 Builder.defineMacro("__MINGW64__"); 3390 addMinGWDefines(Opts, Builder); 3391 } 3392 }; 3393 } // end anonymous namespace 3394 3395 namespace { 3396 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3397 public: 3398 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3399 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3400 Int64Type = SignedLongLong; 3401 MaxVectorAlign = 256; 3402 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3403 llvm::Triple T = llvm::Triple(Triple); 3404 if (T.getOS() == llvm::Triple::IOS) 3405 UseSignedCharForObjCBool = false; 3406 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3407 } 3408 }; 3409 } // end anonymous namespace 3410 3411 namespace { 3412 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3413 public: 3414 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3415 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3416 IntMaxType = SignedLongLong; 3417 UIntMaxType = UnsignedLongLong; 3418 Int64Type = SignedLongLong; 3419 } 3420 }; 3421 } // end anonymous namespace 3422 3423 namespace { 3424 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3425 public: 3426 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3427 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3428 IntMaxType = SignedLongLong; 3429 UIntMaxType = UnsignedLongLong; 3430 Int64Type = SignedLongLong; 3431 } 3432 }; 3433 } 3434 3435 3436 namespace { 3437 class ARMTargetInfo : public TargetInfo { 3438 // Possible FPU choices. 3439 enum FPUMode { 3440 VFP2FPU = (1 << 0), 3441 VFP3FPU = (1 << 1), 3442 VFP4FPU = (1 << 2), 3443 NeonFPU = (1 << 3), 3444 FPARMV8 = (1 << 4) 3445 }; 3446 3447 // Possible HWDiv features. 3448 enum HWDivMode { 3449 HWDivThumb = (1 << 0), 3450 HWDivARM = (1 << 1) 3451 }; 3452 3453 static bool FPUModeIsVFP(FPUMode Mode) { 3454 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3455 } 3456 3457 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3458 static const char * const GCCRegNames[]; 3459 3460 std::string ABI, CPU; 3461 3462 enum { 3463 FP_Default, 3464 FP_VFP, 3465 FP_Neon 3466 } FPMath; 3467 3468 unsigned FPU : 5; 3469 3470 unsigned IsAAPCS : 1; 3471 unsigned IsThumb : 1; 3472 unsigned HWDiv : 2; 3473 3474 // Initialized via features. 3475 unsigned SoftFloat : 1; 3476 unsigned SoftFloatABI : 1; 3477 3478 unsigned CRC : 1; 3479 unsigned Crypto : 1; 3480 3481 static const Builtin::Info BuiltinInfo[]; 3482 3483 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3484 StringRef ArchName = T.getArchName(); 3485 if (T.getArch() == llvm::Triple::arm || 3486 T.getArch() == llvm::Triple::armeb) { 3487 StringRef VersionStr; 3488 if (ArchName.startswith("armv")) 3489 VersionStr = ArchName.substr(4, 1); 3490 else if (ArchName.startswith("armebv")) 3491 VersionStr = ArchName.substr(6, 1); 3492 else 3493 return false; 3494 unsigned Version; 3495 if (VersionStr.getAsInteger(10, Version)) 3496 return false; 3497 return Version >= 6; 3498 } 3499 assert(T.getArch() == llvm::Triple::thumb || 3500 T.getArch() == llvm::Triple::thumbeb); 3501 StringRef VersionStr; 3502 if (ArchName.startswith("thumbv")) 3503 VersionStr = ArchName.substr(6, 1); 3504 else if (ArchName.startswith("thumbebv")) 3505 VersionStr = ArchName.substr(8, 1); 3506 else 3507 return false; 3508 unsigned Version; 3509 if (VersionStr.getAsInteger(10, Version)) 3510 return false; 3511 return Version >= 7; 3512 } 3513 3514 void setABIAAPCS() { 3515 IsAAPCS = true; 3516 3517 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3518 const llvm::Triple &T = getTriple(); 3519 3520 // size_t is unsigned long on Darwin and NetBSD. 3521 if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD) 3522 SizeType = UnsignedLong; 3523 else 3524 SizeType = UnsignedInt; 3525 3526 switch (T.getOS()) { 3527 case llvm::Triple::NetBSD: 3528 WCharType = SignedInt; 3529 break; 3530 case llvm::Triple::Win32: 3531 WCharType = UnsignedShort; 3532 break; 3533 case llvm::Triple::Linux: 3534 default: 3535 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3536 WCharType = UnsignedInt; 3537 break; 3538 } 3539 3540 UseBitFieldTypeAlignment = true; 3541 3542 ZeroLengthBitfieldBoundary = 0; 3543 3544 if (IsThumb) { 3545 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3546 // so set preferred for small types to 32. 3547 if (T.isOSBinFormatMachO()) { 3548 DescriptionString = BigEndian ? 3549 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3550 "v128:64:128-a:0:32-n32-S64" : 3551 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3552 "v128:64:128-a:0:32-n32-S64"; 3553 } else if (T.isOSWindows()) { 3554 // FIXME: this is invalid for WindowsCE 3555 assert(!BigEndian && "Windows on ARM does not support big endian"); 3556 DescriptionString = "e" 3557 "-m:e" 3558 "-p:32:32" 3559 "-i1:8:32-i8:8:32-i16:16:32-i64:64" 3560 "-v128:64:128" 3561 "-a:0:32" 3562 "-n32" 3563 "-S64"; 3564 } else { 3565 DescriptionString = BigEndian ? 3566 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3567 "v128:64:128-a:0:32-n32-S64" : 3568 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3569 "v128:64:128-a:0:32-n32-S64"; 3570 } 3571 } else { 3572 if (T.isOSBinFormatMachO()) 3573 DescriptionString = BigEndian ? 3574 "E-m:o-p:32:32-i64:64-v128:64:128-n32-S64" : 3575 "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3576 else 3577 DescriptionString = BigEndian ? 3578 "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64" : 3579 "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3580 } 3581 3582 // FIXME: Enumerated types are variable width in straight AAPCS. 3583 } 3584 3585 void setABIAPCS() { 3586 const llvm::Triple &T = getTriple(); 3587 3588 IsAAPCS = false; 3589 3590 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3591 3592 // size_t is unsigned int on FreeBSD. 3593 if (T.getOS() == llvm::Triple::FreeBSD) 3594 SizeType = UnsignedInt; 3595 else 3596 SizeType = UnsignedLong; 3597 3598 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3599 WCharType = SignedInt; 3600 3601 // Do not respect the alignment of bit-field types when laying out 3602 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3603 UseBitFieldTypeAlignment = false; 3604 3605 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3606 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3607 /// gcc. 3608 ZeroLengthBitfieldBoundary = 32; 3609 3610 if (IsThumb) { 3611 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3612 // so set preferred for small types to 32. 3613 if (T.isOSBinFormatMachO()) 3614 DescriptionString = BigEndian ? 3615 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3616 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3617 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3618 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3619 else 3620 DescriptionString = BigEndian ? 3621 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3622 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3623 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3624 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3625 } else { 3626 if (T.isOSBinFormatMachO()) 3627 DescriptionString = BigEndian ? 3628 "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3629 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3630 else 3631 DescriptionString = BigEndian ? 3632 "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3633 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3634 } 3635 3636 // FIXME: Override "preferred align" for double and long long. 3637 } 3638 3639 public: 3640 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3641 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3642 IsAAPCS(true) { 3643 BigEndian = IsBigEndian; 3644 3645 switch (getTriple().getOS()) { 3646 case llvm::Triple::NetBSD: 3647 PtrDiffType = SignedLong; 3648 break; 3649 default: 3650 PtrDiffType = SignedInt; 3651 break; 3652 } 3653 3654 // {} in inline assembly are neon specifiers, not assembly variant 3655 // specifiers. 3656 NoAsmVariants = true; 3657 3658 // FIXME: Should we just treat this as a feature? 3659 IsThumb = getTriple().getArchName().startswith("thumb"); 3660 3661 setABI("aapcs-linux"); 3662 3663 // ARM targets default to using the ARM C++ ABI. 3664 TheCXXABI.set(TargetCXXABI::GenericARM); 3665 3666 // ARM has atomics up to 8 bytes 3667 MaxAtomicPromoteWidth = 64; 3668 if (shouldUseInlineAtomic(getTriple())) 3669 MaxAtomicInlineWidth = 64; 3670 3671 // Do force alignment of members that follow zero length bitfields. If 3672 // the alignment of the zero-length bitfield is greater than the member 3673 // that follows it, `bar', `bar' will be aligned as the type of the 3674 // zero length bitfield. 3675 UseZeroLengthBitfieldAlignment = true; 3676 } 3677 StringRef getABI() const override { return ABI; } 3678 bool setABI(const std::string &Name) override { 3679 ABI = Name; 3680 3681 // The defaults (above) are for AAPCS, check if we need to change them. 3682 // 3683 // FIXME: We need support for -meabi... we could just mangle it into the 3684 // name. 3685 if (Name == "apcs-gnu") { 3686 setABIAPCS(); 3687 return true; 3688 } 3689 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3690 setABIAAPCS(); 3691 return true; 3692 } 3693 return false; 3694 } 3695 3696 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 3697 if (IsAAPCS) 3698 Features["aapcs"] = true; 3699 else 3700 Features["apcs"] = true; 3701 3702 StringRef ArchName = getTriple().getArchName(); 3703 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3704 Features["vfp2"] = true; 3705 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3706 CPU == "cortex-a9-mp") { 3707 Features["vfp3"] = true; 3708 Features["neon"] = true; 3709 } 3710 else if (CPU == "cortex-a5") { 3711 Features["vfp4"] = true; 3712 Features["neon"] = true; 3713 } else if (CPU == "swift" || CPU == "cortex-a7" || 3714 CPU == "cortex-a12" || CPU == "cortex-a15" || 3715 CPU == "krait") { 3716 Features["vfp4"] = true; 3717 Features["neon"] = true; 3718 Features["hwdiv"] = true; 3719 Features["hwdiv-arm"] = true; 3720 } else if (CPU == "cyclone") { 3721 Features["v8fp"] = true; 3722 Features["neon"] = true; 3723 Features["hwdiv"] = true; 3724 Features["hwdiv-arm"] = true; 3725 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3726 Features["fp-armv8"] = true; 3727 Features["neon"] = true; 3728 Features["hwdiv"] = true; 3729 Features["hwdiv-arm"] = true; 3730 Features["crc"] = true; 3731 Features["crypto"] = true; 3732 } else if (CPU == "cortex-r5" || 3733 // Enable the hwdiv extension for all v8a AArch32 cores by 3734 // default. 3735 ArchName == "armv8a" || ArchName == "armv8" || 3736 ArchName == "armebv8a" || ArchName == "armebv8" || 3737 ArchName == "thumbv8a" || ArchName == "thumbv8" || 3738 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 3739 Features["hwdiv"] = true; 3740 Features["hwdiv-arm"] = true; 3741 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") { 3742 Features["hwdiv"] = true; 3743 } 3744 } 3745 3746 bool handleTargetFeatures(std::vector<std::string> &Features, 3747 DiagnosticsEngine &Diags) override { 3748 FPU = 0; 3749 CRC = 0; 3750 Crypto = 0; 3751 SoftFloat = SoftFloatABI = false; 3752 HWDiv = 0; 3753 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3754 if (Features[i] == "+soft-float") 3755 SoftFloat = true; 3756 else if (Features[i] == "+soft-float-abi") 3757 SoftFloatABI = true; 3758 else if (Features[i] == "+vfp2") 3759 FPU |= VFP2FPU; 3760 else if (Features[i] == "+vfp3") 3761 FPU |= VFP3FPU; 3762 else if (Features[i] == "+vfp4") 3763 FPU |= VFP4FPU; 3764 else if (Features[i] == "+fp-armv8") 3765 FPU |= FPARMV8; 3766 else if (Features[i] == "+neon") 3767 FPU |= NeonFPU; 3768 else if (Features[i] == "+long64") 3769 LongWidth = LongAlign = 64; // RenderScript uses a 64-bit long type 3770 else if (Features[i] == "+hwdiv") 3771 HWDiv |= HWDivThumb; 3772 else if (Features[i] == "+hwdiv-arm") 3773 HWDiv |= HWDivARM; 3774 else if (Features[i] == "+crc") 3775 CRC = 1; 3776 else if (Features[i] == "+crypto") 3777 Crypto = 1; 3778 } 3779 3780 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3781 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3782 return false; 3783 } 3784 3785 if (FPMath == FP_Neon) 3786 Features.push_back("+neonfp"); 3787 else if (FPMath == FP_VFP) 3788 Features.push_back("-neonfp"); 3789 3790 // Remove front-end specific options which the backend handles differently. 3791 std::vector<std::string>::iterator it; 3792 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3793 if (it != Features.end()) 3794 Features.erase(it); 3795 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3796 if (it != Features.end()) 3797 Features.erase(it); 3798 return true; 3799 } 3800 3801 bool hasFeature(StringRef Feature) const override { 3802 return llvm::StringSwitch<bool>(Feature) 3803 .Case("arm", true) 3804 .Case("softfloat", SoftFloat) 3805 .Case("thumb", IsThumb) 3806 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3807 .Case("hwdiv", HWDiv & HWDivThumb) 3808 .Case("hwdiv-arm", HWDiv & HWDivARM) 3809 .Default(false); 3810 } 3811 // FIXME: Should we actually have some table instead of these switches? 3812 static const char *getCPUDefineSuffix(StringRef Name) { 3813 return llvm::StringSwitch<const char*>(Name) 3814 .Cases("arm8", "arm810", "4") 3815 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3816 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3817 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3818 .Case("ep9312", "4T") 3819 .Cases("arm10tdmi", "arm1020t", "5T") 3820 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3821 .Case("arm926ej-s", "5TEJ") 3822 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3823 .Cases("xscale", "iwmmxt", "5TE") 3824 .Case("arm1136j-s", "6J") 3825 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3826 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3827 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3828 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 3829 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 3830 .Cases("cortex-r4", "cortex-r5", "7R") 3831 .Case("swift", "7S") 3832 .Case("cyclone", "8A") 3833 .Case("cortex-m3", "7M") 3834 .Case("cortex-m4", "7EM") 3835 .Case("cortex-m0", "6M") 3836 .Cases("cortex-a53", "cortex-a57", "8A") 3837 .Default(nullptr); 3838 } 3839 static const char *getCPUProfile(StringRef Name) { 3840 return llvm::StringSwitch<const char*>(Name) 3841 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 3842 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 3843 .Cases("cortex-a53", "cortex-a57", "A") 3844 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3845 .Cases("cortex-r4", "cortex-r5", "R") 3846 .Default(""); 3847 } 3848 bool setCPU(const std::string &Name) override { 3849 if (!getCPUDefineSuffix(Name)) 3850 return false; 3851 3852 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 3853 StringRef Profile = getCPUProfile(Name); 3854 if (Profile == "M" && MaxAtomicInlineWidth) { 3855 MaxAtomicPromoteWidth = 32; 3856 MaxAtomicInlineWidth = 32; 3857 } 3858 3859 CPU = Name; 3860 return true; 3861 } 3862 bool setFPMath(StringRef Name) override; 3863 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 3864 unsigned CPUArchVer) const { 3865 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 3866 (CPUArch.find('M') != StringRef::npos); 3867 } 3868 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 3869 unsigned CPUArchVer) const { 3870 // We check both CPUArchVer and ArchName because when only triple is 3871 // specified, the default CPU is arm1136j-s. 3872 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 3873 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 3874 } 3875 void getTargetDefines(const LangOptions &Opts, 3876 MacroBuilder &Builder) const override { 3877 // Target identification. 3878 Builder.defineMacro("__arm"); 3879 Builder.defineMacro("__arm__"); 3880 3881 // Target properties. 3882 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3883 3884 StringRef CPUArch = getCPUDefineSuffix(CPU); 3885 unsigned int CPUArchVer; 3886 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 3887 llvm_unreachable("Invalid char for architecture version number"); 3888 } 3889 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3890 3891 // ACLE 6.4.1 ARM/Thumb instruction set architecture 3892 StringRef CPUProfile = getCPUProfile(CPU); 3893 StringRef ArchName = getTriple().getArchName(); 3894 3895 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 3896 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3897 3898 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 3899 // is not defined for the M-profile. 3900 // NOTE that the deffault profile is assumed to be 'A' 3901 if (CPUProfile.empty() || CPUProfile != "M") 3902 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 3903 3904 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 3905 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 3906 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 3907 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 3908 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 3909 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 3910 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 3911 3912 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 3913 // instruction set such as ARM or Thumb. 3914 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 3915 3916 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 3917 3918 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 3919 if (!CPUProfile.empty()) 3920 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 3921 3922 // ACLE predefines. 3923 Builder.defineMacro("__ARM_ACLE", "200"); 3924 3925 // Subtarget options. 3926 3927 // FIXME: It's more complicated than this and we don't really support 3928 // interworking. 3929 // Windows on ARM does not "support" interworking 3930 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 3931 Builder.defineMacro("__THUMB_INTERWORK__"); 3932 3933 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3934 // Embedded targets on Darwin follow AAPCS, but not EABI. 3935 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 3936 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 3937 Builder.defineMacro("__ARM_EABI__"); 3938 Builder.defineMacro("__ARM_PCS", "1"); 3939 3940 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3941 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3942 } 3943 3944 if (SoftFloat) 3945 Builder.defineMacro("__SOFTFP__"); 3946 3947 if (CPU == "xscale") 3948 Builder.defineMacro("__XSCALE__"); 3949 3950 if (IsThumb) { 3951 Builder.defineMacro("__THUMBEL__"); 3952 Builder.defineMacro("__thumb__"); 3953 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 3954 Builder.defineMacro("__thumb2__"); 3955 } 3956 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 3957 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 3958 3959 // Note, this is always on in gcc, even though it doesn't make sense. 3960 Builder.defineMacro("__APCS_32__"); 3961 3962 if (FPUModeIsVFP((FPUMode) FPU)) { 3963 Builder.defineMacro("__VFP_FP__"); 3964 if (FPU & VFP2FPU) 3965 Builder.defineMacro("__ARM_VFPV2__"); 3966 if (FPU & VFP3FPU) 3967 Builder.defineMacro("__ARM_VFPV3__"); 3968 if (FPU & VFP4FPU) 3969 Builder.defineMacro("__ARM_VFPV4__"); 3970 } 3971 3972 // This only gets set when Neon instructions are actually available, unlike 3973 // the VFP define, hence the soft float and arch check. This is subtly 3974 // different from gcc, we follow the intent which was that it should be set 3975 // when Neon instructions are actually available. 3976 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 3977 Builder.defineMacro("__ARM_NEON"); 3978 Builder.defineMacro("__ARM_NEON__"); 3979 } 3980 3981 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3982 Opts.ShortWChar ? "2" : "4"); 3983 3984 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3985 Opts.ShortEnums ? "1" : "4"); 3986 3987 if (CRC) 3988 Builder.defineMacro("__ARM_FEATURE_CRC32"); 3989 3990 if (Crypto) 3991 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3992 3993 if (CPUArchVer >= 6 && CPUArch != "6M") { 3994 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3995 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3996 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3997 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3998 } 3999 } 4000 void getTargetBuiltins(const Builtin::Info *&Records, 4001 unsigned &NumRecords) const override { 4002 Records = BuiltinInfo; 4003 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4004 } 4005 bool isCLZForZeroUndef() const override { return false; } 4006 BuiltinVaListKind getBuiltinVaListKind() const override { 4007 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4008 } 4009 void getGCCRegNames(const char * const *&Names, 4010 unsigned &NumNames) const override; 4011 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4012 unsigned &NumAliases) const override; 4013 bool validateAsmConstraint(const char *&Name, 4014 TargetInfo::ConstraintInfo &Info) const override { 4015 switch (*Name) { 4016 default: break; 4017 case 'l': // r0-r7 4018 case 'h': // r8-r15 4019 case 'w': // VFP Floating point register single precision 4020 case 'P': // VFP Floating point register double precision 4021 Info.setAllowsRegister(); 4022 return true; 4023 case 'Q': // A memory address that is a single base register. 4024 Info.setAllowsMemory(); 4025 return true; 4026 case 'U': // a memory reference... 4027 switch (Name[1]) { 4028 case 'q': // ...ARMV4 ldrsb 4029 case 'v': // ...VFP load/store (reg+constant offset) 4030 case 'y': // ...iWMMXt load/store 4031 case 't': // address valid for load/store opaque types wider 4032 // than 128-bits 4033 case 'n': // valid address for Neon doubleword vector load/store 4034 case 'm': // valid address for Neon element and structure load/store 4035 case 's': // valid address for non-offset loads/stores of quad-word 4036 // values in four ARM registers 4037 Info.setAllowsMemory(); 4038 Name++; 4039 return true; 4040 } 4041 } 4042 return false; 4043 } 4044 std::string convertConstraint(const char *&Constraint) const override { 4045 std::string R; 4046 switch (*Constraint) { 4047 case 'U': // Two-character constraint; add "^" hint for later parsing. 4048 R = std::string("^") + std::string(Constraint, 2); 4049 Constraint++; 4050 break; 4051 case 'p': // 'p' should be translated to 'r' by default. 4052 R = std::string("r"); 4053 break; 4054 default: 4055 return std::string(1, *Constraint); 4056 } 4057 return R; 4058 } 4059 bool validateConstraintModifier(StringRef Constraint, const char Modifier, 4060 unsigned Size) const override { 4061 bool isOutput = (Constraint[0] == '='); 4062 bool isInOut = (Constraint[0] == '+'); 4063 4064 // Strip off constraint modifiers. 4065 while (Constraint[0] == '=' || 4066 Constraint[0] == '+' || 4067 Constraint[0] == '&') 4068 Constraint = Constraint.substr(1); 4069 4070 switch (Constraint[0]) { 4071 default: break; 4072 case 'r': { 4073 switch (Modifier) { 4074 default: 4075 return (isInOut || isOutput || Size <= 64); 4076 case 'q': 4077 // A register of size 32 cannot fit a vector type. 4078 return false; 4079 } 4080 } 4081 } 4082 4083 return true; 4084 } 4085 const char *getClobbers() const override { 4086 // FIXME: Is this really right? 4087 return ""; 4088 } 4089 4090 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4091 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4092 } 4093 4094 int getEHDataRegisterNumber(unsigned RegNo) const override { 4095 if (RegNo == 0) return 0; 4096 if (RegNo == 1) return 1; 4097 return -1; 4098 } 4099 }; 4100 4101 bool ARMTargetInfo::setFPMath(StringRef Name) { 4102 if (Name == "neon") { 4103 FPMath = FP_Neon; 4104 return true; 4105 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4106 Name == "vfp4") { 4107 FPMath = FP_VFP; 4108 return true; 4109 } 4110 return false; 4111 } 4112 4113 const char * const ARMTargetInfo::GCCRegNames[] = { 4114 // Integer registers 4115 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4116 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4117 4118 // Float registers 4119 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4120 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4121 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4122 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4123 4124 // Double registers 4125 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4126 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4127 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4128 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4129 4130 // Quad registers 4131 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4132 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4133 }; 4134 4135 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4136 unsigned &NumNames) const { 4137 Names = GCCRegNames; 4138 NumNames = llvm::array_lengthof(GCCRegNames); 4139 } 4140 4141 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4142 { { "a1" }, "r0" }, 4143 { { "a2" }, "r1" }, 4144 { { "a3" }, "r2" }, 4145 { { "a4" }, "r3" }, 4146 { { "v1" }, "r4" }, 4147 { { "v2" }, "r5" }, 4148 { { "v3" }, "r6" }, 4149 { { "v4" }, "r7" }, 4150 { { "v5" }, "r8" }, 4151 { { "v6", "rfp" }, "r9" }, 4152 { { "sl" }, "r10" }, 4153 { { "fp" }, "r11" }, 4154 { { "ip" }, "r12" }, 4155 { { "r13" }, "sp" }, 4156 { { "r14" }, "lr" }, 4157 { { "r15" }, "pc" }, 4158 // The S, D and Q registers overlap, but aren't really aliases; we 4159 // don't want to substitute one of these for a different-sized one. 4160 }; 4161 4162 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4163 unsigned &NumAliases) const { 4164 Aliases = GCCRegAliases; 4165 NumAliases = llvm::array_lengthof(GCCRegAliases); 4166 } 4167 4168 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4169 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4170 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4171 ALL_LANGUAGES }, 4172 #include "clang/Basic/BuiltinsNEON.def" 4173 4174 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4175 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4176 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4177 ALL_LANGUAGES }, 4178 #include "clang/Basic/BuiltinsARM.def" 4179 }; 4180 4181 class ARMleTargetInfo : public ARMTargetInfo { 4182 public: 4183 ARMleTargetInfo(const llvm::Triple &Triple) 4184 : ARMTargetInfo(Triple, false) { } 4185 virtual void getTargetDefines(const LangOptions &Opts, 4186 MacroBuilder &Builder) const { 4187 Builder.defineMacro("__ARMEL__"); 4188 ARMTargetInfo::getTargetDefines(Opts, Builder); 4189 } 4190 }; 4191 4192 class ARMbeTargetInfo : public ARMTargetInfo { 4193 public: 4194 ARMbeTargetInfo(const llvm::Triple &Triple) 4195 : ARMTargetInfo(Triple, true) { } 4196 virtual void getTargetDefines(const LangOptions &Opts, 4197 MacroBuilder &Builder) const { 4198 Builder.defineMacro("__ARMEB__"); 4199 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4200 ARMTargetInfo::getTargetDefines(Opts, Builder); 4201 } 4202 }; 4203 } // end anonymous namespace. 4204 4205 namespace { 4206 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4207 const llvm::Triple Triple; 4208 public: 4209 WindowsARMTargetInfo(const llvm::Triple &Triple) 4210 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4211 TLSSupported = false; 4212 WCharType = UnsignedShort; 4213 SizeType = UnsignedInt; 4214 UserLabelPrefix = ""; 4215 } 4216 void getVisualStudioDefines(const LangOptions &Opts, 4217 MacroBuilder &Builder) const { 4218 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4219 4220 // FIXME: this is invalid for WindowsCE 4221 Builder.defineMacro("_M_ARM_NT", "1"); 4222 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4223 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4224 4225 assert((Triple.getArch() == llvm::Triple::arm || 4226 Triple.getArch() == llvm::Triple::thumb) && 4227 "invalid architecture for Windows ARM target info"); 4228 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4229 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4230 4231 // TODO map the complete set of values 4232 // 31: VFPv3 40: VFPv4 4233 Builder.defineMacro("_M_ARM_FP", "31"); 4234 } 4235 BuiltinVaListKind getBuiltinVaListKind() const override { 4236 return TargetInfo::CharPtrBuiltinVaList; 4237 } 4238 }; 4239 4240 // Windows ARM + Itanium C++ ABI Target 4241 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4242 public: 4243 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4244 : WindowsARMTargetInfo(Triple) { 4245 TheCXXABI.set(TargetCXXABI::GenericARM); 4246 } 4247 4248 void getTargetDefines(const LangOptions &Opts, 4249 MacroBuilder &Builder) const override { 4250 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4251 4252 if (Opts.MSVCCompat) 4253 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4254 } 4255 }; 4256 4257 // Windows ARM, MS (C++) ABI 4258 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4259 public: 4260 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4261 : WindowsARMTargetInfo(Triple) { 4262 TheCXXABI.set(TargetCXXABI::Microsoft); 4263 } 4264 4265 void getTargetDefines(const LangOptions &Opts, 4266 MacroBuilder &Builder) const override { 4267 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4268 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4269 } 4270 }; 4271 } 4272 4273 4274 namespace { 4275 class DarwinARMTargetInfo : 4276 public DarwinTargetInfo<ARMleTargetInfo> { 4277 protected: 4278 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4279 MacroBuilder &Builder) const override { 4280 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4281 } 4282 4283 public: 4284 DarwinARMTargetInfo(const llvm::Triple &Triple) 4285 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4286 HasAlignMac68kSupport = true; 4287 // iOS always has 64-bit atomic instructions. 4288 // FIXME: This should be based off of the target features in ARMleTargetInfo. 4289 MaxAtomicInlineWidth = 64; 4290 4291 // Darwin on iOS uses a variant of the ARM C++ ABI. 4292 TheCXXABI.set(TargetCXXABI::iOS); 4293 } 4294 }; 4295 } // end anonymous namespace. 4296 4297 4298 namespace { 4299 class AArch64TargetInfo : public TargetInfo { 4300 virtual void setDescriptionString() = 0; 4301 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4302 static const char *const GCCRegNames[]; 4303 4304 enum FPUModeEnum { 4305 FPUMode, 4306 NeonMode 4307 }; 4308 4309 std::string CPU; 4310 unsigned FPU; 4311 unsigned CRC; 4312 unsigned Crypto; 4313 4314 static const Builtin::Info BuiltinInfo[]; 4315 4316 std::string ABI; 4317 4318 public: 4319 AArch64TargetInfo(const llvm::Triple &Triple) 4320 : TargetInfo(Triple), ABI("aapcs") { 4321 4322 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4323 WCharType = SignedInt; 4324 4325 // NetBSD apparently prefers consistency across ARM targets to consistency 4326 // across 64-bit targets. 4327 Int64Type = SignedLongLong; 4328 IntMaxType = SignedLongLong; 4329 UIntMaxType = UnsignedLongLong; 4330 } else { 4331 WCharType = UnsignedInt; 4332 Int64Type = SignedLong; 4333 IntMaxType = SignedLong; 4334 UIntMaxType = UnsignedLong; 4335 } 4336 4337 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4338 MaxVectorAlign = 128; 4339 RegParmMax = 8; 4340 MaxAtomicInlineWidth = 128; 4341 MaxAtomicPromoteWidth = 128; 4342 4343 LongDoubleWidth = LongDoubleAlign = 128; 4344 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4345 4346 // {} in inline assembly are neon specifiers, not assembly variant 4347 // specifiers. 4348 NoAsmVariants = true; 4349 4350 // AArch64 targets default to using the ARM C++ ABI. 4351 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4352 } 4353 4354 StringRef getABI() const override { return ABI; } 4355 virtual bool setABI(const std::string &Name) { 4356 if (Name != "aapcs" && Name != "darwinpcs") 4357 return false; 4358 4359 ABI = Name; 4360 return true; 4361 } 4362 4363 virtual bool setCPU(const std::string &Name) { 4364 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4365 .Case("generic", true) 4366 .Cases("cortex-a53", "cortex-a57", true) 4367 .Case("cyclone", true) 4368 .Default(false); 4369 if (CPUKnown) 4370 CPU = Name; 4371 return CPUKnown; 4372 } 4373 4374 virtual void getTargetDefines(const LangOptions &Opts, 4375 MacroBuilder &Builder) const { 4376 // Target identification. 4377 Builder.defineMacro("__aarch64__"); 4378 4379 // Target properties. 4380 Builder.defineMacro("_LP64"); 4381 Builder.defineMacro("__LP64__"); 4382 4383 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4384 Builder.defineMacro("__ARM_ACLE", "200"); 4385 Builder.defineMacro("__ARM_ARCH", "8"); 4386 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4387 4388 Builder.defineMacro("__ARM_64BIT_STATE"); 4389 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4390 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4391 4392 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4393 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4394 Builder.defineMacro("__ARM_FEATURE_FMA"); 4395 Builder.defineMacro("__ARM_FEATURE_DIV"); 4396 4397 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4398 4399 // 0xe implies support for half, single and double precision operations. 4400 Builder.defineMacro("__ARM_FP", "0xe"); 4401 4402 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4403 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4404 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4405 4406 if (Opts.FastMath || Opts.FiniteMathOnly) 4407 Builder.defineMacro("__ARM_FP_FAST"); 4408 4409 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 4410 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4411 4412 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4413 4414 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4415 Opts.ShortEnums ? "1" : "4"); 4416 4417 if (FPU == NeonMode) { 4418 Builder.defineMacro("__ARM_NEON"); 4419 // 64-bit NEON supports half, single and double precision operations. 4420 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4421 } 4422 4423 if (CRC) 4424 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4425 4426 if (Crypto) 4427 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4428 } 4429 4430 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4431 unsigned &NumRecords) const { 4432 Records = BuiltinInfo; 4433 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4434 } 4435 4436 virtual bool hasFeature(StringRef Feature) const { 4437 return Feature == "aarch64" || 4438 Feature == "arm64" || 4439 (Feature == "neon" && FPU == NeonMode); 4440 } 4441 4442 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4443 4444 if (CPU == "cyclone") { 4445 Features["fp-armv8"] = true; 4446 Features["neon"] = true; 4447 Features["crypto"] = true; 4448 Features["crc"] = true; 4449 Features["zcm"] = true; 4450 Features["zcz"] = true; 4451 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 4452 Features["fp-armv8"] = true; 4453 Features["neon"] = true; 4454 Features["crypto"] = true; 4455 Features["crc"] = true; 4456 } 4457 } 4458 4459 bool handleTargetFeatures(std::vector<std::string> &Features, 4460 DiagnosticsEngine &Diags) override { 4461 FPU = FPUMode; 4462 CRC = 0; 4463 Crypto = 0; 4464 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4465 if (Features[i] == "+neon") 4466 FPU = NeonMode; 4467 if (Features[i] == "+crc") 4468 CRC = 1; 4469 if (Features[i] == "+crypto") 4470 Crypto = 1; 4471 } 4472 4473 setDescriptionString(); 4474 4475 return true; 4476 } 4477 4478 virtual bool isCLZForZeroUndef() const { return false; } 4479 4480 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4481 return TargetInfo::AArch64ABIBuiltinVaList; 4482 } 4483 4484 virtual void getGCCRegNames(const char *const *&Names, 4485 unsigned &NumNames) const; 4486 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4487 unsigned &NumAliases) const; 4488 4489 virtual bool validateAsmConstraint(const char *&Name, 4490 TargetInfo::ConstraintInfo &Info) const { 4491 switch (*Name) { 4492 default: 4493 return false; 4494 case 'w': // Floating point and SIMD registers (V0-V31) 4495 Info.setAllowsRegister(); 4496 return true; 4497 case 'I': // Constant that can be used with an ADD instruction 4498 case 'J': // Constant that can be used with a SUB instruction 4499 case 'K': // Constant that can be used with a 32-bit logical instruction 4500 case 'L': // Constant that can be used with a 64-bit logical instruction 4501 case 'M': // Constant that can be used as a 32-bit MOV immediate 4502 case 'N': // Constant that can be used as a 64-bit MOV immediate 4503 case 'Y': // Floating point constant zero 4504 case 'Z': // Integer constant zero 4505 return true; 4506 case 'Q': // A memory reference with base register and no offset 4507 Info.setAllowsMemory(); 4508 return true; 4509 case 'S': // A symbolic address 4510 Info.setAllowsRegister(); 4511 return true; 4512 case 'U': 4513 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 4514 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 4515 // Usa: An absolute symbolic address 4516 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 4517 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 4518 case 'z': // Zero register, wzr or xzr 4519 Info.setAllowsRegister(); 4520 return true; 4521 case 'x': // Floating point and SIMD registers (V0-V15) 4522 Info.setAllowsRegister(); 4523 return true; 4524 } 4525 return false; 4526 } 4527 4528 virtual const char *getClobbers() const { return ""; } 4529 4530 int getEHDataRegisterNumber(unsigned RegNo) const { 4531 if (RegNo == 0) 4532 return 0; 4533 if (RegNo == 1) 4534 return 1; 4535 return -1; 4536 } 4537 }; 4538 4539 const char *const AArch64TargetInfo::GCCRegNames[] = { 4540 // 32-bit Integer registers 4541 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4542 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4543 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4544 4545 // 64-bit Integer registers 4546 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4547 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4548 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4549 4550 // 32-bit floating point regsisters 4551 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4552 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4553 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4554 4555 // 64-bit floating point regsisters 4556 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4557 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4558 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4559 4560 // Vector registers 4561 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4562 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4563 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4564 }; 4565 4566 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 4567 unsigned &NumNames) const { 4568 Names = GCCRegNames; 4569 NumNames = llvm::array_lengthof(GCCRegNames); 4570 } 4571 4572 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 4573 { { "w31" }, "wsp" }, 4574 { { "x29" }, "fp" }, 4575 { { "x30" }, "lr" }, 4576 { { "x31" }, "sp" }, 4577 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4578 // don't want to substitute one of these for a different-sized one. 4579 }; 4580 4581 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4582 unsigned &NumAliases) const { 4583 Aliases = GCCRegAliases; 4584 NumAliases = llvm::array_lengthof(GCCRegAliases); 4585 } 4586 4587 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 4588 #define BUILTIN(ID, TYPE, ATTRS) \ 4589 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4590 #include "clang/Basic/BuiltinsNEON.def" 4591 4592 #define BUILTIN(ID, TYPE, ATTRS) \ 4593 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4594 #include "clang/Basic/BuiltinsAArch64.def" 4595 }; 4596 4597 class AArch64leTargetInfo : public AArch64TargetInfo { 4598 void setDescriptionString() override { 4599 if (getTriple().isOSBinFormatMachO()) 4600 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4601 else 4602 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4603 } 4604 4605 public: 4606 AArch64leTargetInfo(const llvm::Triple &Triple) 4607 : AArch64TargetInfo(Triple) { 4608 BigEndian = false; 4609 } 4610 void getTargetDefines(const LangOptions &Opts, 4611 MacroBuilder &Builder) const override { 4612 Builder.defineMacro("__AARCH64EL__"); 4613 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4614 } 4615 }; 4616 4617 class AArch64beTargetInfo : public AArch64TargetInfo { 4618 void setDescriptionString() override { 4619 assert(!getTriple().isOSBinFormatMachO()); 4620 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 4621 } 4622 4623 public: 4624 AArch64beTargetInfo(const llvm::Triple &Triple) 4625 : AArch64TargetInfo(Triple) { } 4626 void getTargetDefines(const LangOptions &Opts, 4627 MacroBuilder &Builder) const override { 4628 Builder.defineMacro("__AARCH64EB__"); 4629 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 4630 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4631 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4632 } 4633 }; 4634 } // end anonymous namespace. 4635 4636 namespace { 4637 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 4638 protected: 4639 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4640 MacroBuilder &Builder) const override { 4641 Builder.defineMacro("__AARCH64_SIMD__"); 4642 Builder.defineMacro("__ARM64_ARCH_8__"); 4643 Builder.defineMacro("__ARM_NEON__"); 4644 Builder.defineMacro("__LITTLE_ENDIAN__"); 4645 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4646 Builder.defineMacro("__arm64", "1"); 4647 Builder.defineMacro("__arm64__", "1"); 4648 4649 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4650 } 4651 4652 public: 4653 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 4654 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 4655 Int64Type = SignedLongLong; 4656 WCharType = SignedInt; 4657 UseSignedCharForObjCBool = false; 4658 4659 LongDoubleWidth = LongDoubleAlign = 64; 4660 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4661 4662 TheCXXABI.set(TargetCXXABI::iOS64); 4663 } 4664 4665 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4666 return TargetInfo::CharPtrBuiltinVaList; 4667 } 4668 }; 4669 } // end anonymous namespace 4670 4671 namespace { 4672 // Hexagon abstract base class 4673 class HexagonTargetInfo : public TargetInfo { 4674 static const Builtin::Info BuiltinInfo[]; 4675 static const char * const GCCRegNames[]; 4676 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4677 std::string CPU; 4678 public: 4679 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4680 BigEndian = false; 4681 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4682 4683 // {} in inline assembly are packet specifiers, not assembly variant 4684 // specifiers. 4685 NoAsmVariants = true; 4686 } 4687 4688 void getTargetBuiltins(const Builtin::Info *&Records, 4689 unsigned &NumRecords) const override { 4690 Records = BuiltinInfo; 4691 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4692 } 4693 4694 bool validateAsmConstraint(const char *&Name, 4695 TargetInfo::ConstraintInfo &Info) const override { 4696 return true; 4697 } 4698 4699 void getTargetDefines(const LangOptions &Opts, 4700 MacroBuilder &Builder) const override; 4701 4702 bool hasFeature(StringRef Feature) const override { 4703 return Feature == "hexagon"; 4704 } 4705 4706 BuiltinVaListKind getBuiltinVaListKind() const override { 4707 return TargetInfo::CharPtrBuiltinVaList; 4708 } 4709 void getGCCRegNames(const char * const *&Names, 4710 unsigned &NumNames) const override; 4711 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4712 unsigned &NumAliases) const override; 4713 const char *getClobbers() const override { 4714 return ""; 4715 } 4716 4717 static const char *getHexagonCPUSuffix(StringRef Name) { 4718 return llvm::StringSwitch<const char*>(Name) 4719 .Case("hexagonv4", "4") 4720 .Case("hexagonv5", "5") 4721 .Default(nullptr); 4722 } 4723 4724 bool setCPU(const std::string &Name) override { 4725 if (!getHexagonCPUSuffix(Name)) 4726 return false; 4727 4728 CPU = Name; 4729 return true; 4730 } 4731 }; 4732 4733 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4734 MacroBuilder &Builder) const { 4735 Builder.defineMacro("qdsp6"); 4736 Builder.defineMacro("__qdsp6", "1"); 4737 Builder.defineMacro("__qdsp6__", "1"); 4738 4739 Builder.defineMacro("hexagon"); 4740 Builder.defineMacro("__hexagon", "1"); 4741 Builder.defineMacro("__hexagon__", "1"); 4742 4743 if(CPU == "hexagonv1") { 4744 Builder.defineMacro("__HEXAGON_V1__"); 4745 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4746 if(Opts.HexagonQdsp6Compat) { 4747 Builder.defineMacro("__QDSP6_V1__"); 4748 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4749 } 4750 } 4751 else if(CPU == "hexagonv2") { 4752 Builder.defineMacro("__HEXAGON_V2__"); 4753 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4754 if(Opts.HexagonQdsp6Compat) { 4755 Builder.defineMacro("__QDSP6_V2__"); 4756 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4757 } 4758 } 4759 else if(CPU == "hexagonv3") { 4760 Builder.defineMacro("__HEXAGON_V3__"); 4761 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4762 if(Opts.HexagonQdsp6Compat) { 4763 Builder.defineMacro("__QDSP6_V3__"); 4764 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4765 } 4766 } 4767 else if(CPU == "hexagonv4") { 4768 Builder.defineMacro("__HEXAGON_V4__"); 4769 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4770 if(Opts.HexagonQdsp6Compat) { 4771 Builder.defineMacro("__QDSP6_V4__"); 4772 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4773 } 4774 } 4775 else if(CPU == "hexagonv5") { 4776 Builder.defineMacro("__HEXAGON_V5__"); 4777 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4778 if(Opts.HexagonQdsp6Compat) { 4779 Builder.defineMacro("__QDSP6_V5__"); 4780 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4781 } 4782 } 4783 } 4784 4785 const char * const HexagonTargetInfo::GCCRegNames[] = { 4786 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4787 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4788 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4789 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4790 "p0", "p1", "p2", "p3", 4791 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4792 }; 4793 4794 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4795 unsigned &NumNames) const { 4796 Names = GCCRegNames; 4797 NumNames = llvm::array_lengthof(GCCRegNames); 4798 } 4799 4800 4801 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4802 { { "sp" }, "r29" }, 4803 { { "fp" }, "r30" }, 4804 { { "lr" }, "r31" }, 4805 }; 4806 4807 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4808 unsigned &NumAliases) const { 4809 Aliases = GCCRegAliases; 4810 NumAliases = llvm::array_lengthof(GCCRegAliases); 4811 } 4812 4813 4814 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4815 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4816 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4817 ALL_LANGUAGES }, 4818 #include "clang/Basic/BuiltinsHexagon.def" 4819 }; 4820 } 4821 4822 4823 namespace { 4824 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4825 class SparcTargetInfo : public TargetInfo { 4826 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4827 static const char * const GCCRegNames[]; 4828 bool SoftFloat; 4829 public: 4830 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4831 4832 bool handleTargetFeatures(std::vector<std::string> &Features, 4833 DiagnosticsEngine &Diags) override { 4834 SoftFloat = false; 4835 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4836 if (Features[i] == "+soft-float") 4837 SoftFloat = true; 4838 return true; 4839 } 4840 void getTargetDefines(const LangOptions &Opts, 4841 MacroBuilder &Builder) const override { 4842 DefineStd(Builder, "sparc", Opts); 4843 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4844 4845 if (SoftFloat) 4846 Builder.defineMacro("SOFT_FLOAT", "1"); 4847 } 4848 4849 bool hasFeature(StringRef Feature) const override { 4850 return llvm::StringSwitch<bool>(Feature) 4851 .Case("softfloat", SoftFloat) 4852 .Case("sparc", true) 4853 .Default(false); 4854 } 4855 4856 void getTargetBuiltins(const Builtin::Info *&Records, 4857 unsigned &NumRecords) const override { 4858 // FIXME: Implement! 4859 } 4860 BuiltinVaListKind getBuiltinVaListKind() const override { 4861 return TargetInfo::VoidPtrBuiltinVaList; 4862 } 4863 void getGCCRegNames(const char * const *&Names, 4864 unsigned &NumNames) const override; 4865 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4866 unsigned &NumAliases) const override; 4867 bool validateAsmConstraint(const char *&Name, 4868 TargetInfo::ConstraintInfo &info) const override { 4869 // FIXME: Implement! 4870 return false; 4871 } 4872 const char *getClobbers() const override { 4873 // FIXME: Implement! 4874 return ""; 4875 } 4876 }; 4877 4878 const char * const SparcTargetInfo::GCCRegNames[] = { 4879 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4880 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4881 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4882 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4883 }; 4884 4885 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4886 unsigned &NumNames) const { 4887 Names = GCCRegNames; 4888 NumNames = llvm::array_lengthof(GCCRegNames); 4889 } 4890 4891 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4892 { { "g0" }, "r0" }, 4893 { { "g1" }, "r1" }, 4894 { { "g2" }, "r2" }, 4895 { { "g3" }, "r3" }, 4896 { { "g4" }, "r4" }, 4897 { { "g5" }, "r5" }, 4898 { { "g6" }, "r6" }, 4899 { { "g7" }, "r7" }, 4900 { { "o0" }, "r8" }, 4901 { { "o1" }, "r9" }, 4902 { { "o2" }, "r10" }, 4903 { { "o3" }, "r11" }, 4904 { { "o4" }, "r12" }, 4905 { { "o5" }, "r13" }, 4906 { { "o6", "sp" }, "r14" }, 4907 { { "o7" }, "r15" }, 4908 { { "l0" }, "r16" }, 4909 { { "l1" }, "r17" }, 4910 { { "l2" }, "r18" }, 4911 { { "l3" }, "r19" }, 4912 { { "l4" }, "r20" }, 4913 { { "l5" }, "r21" }, 4914 { { "l6" }, "r22" }, 4915 { { "l7" }, "r23" }, 4916 { { "i0" }, "r24" }, 4917 { { "i1" }, "r25" }, 4918 { { "i2" }, "r26" }, 4919 { { "i3" }, "r27" }, 4920 { { "i4" }, "r28" }, 4921 { { "i5" }, "r29" }, 4922 { { "i6", "fp" }, "r30" }, 4923 { { "i7" }, "r31" }, 4924 }; 4925 4926 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4927 unsigned &NumAliases) const { 4928 Aliases = GCCRegAliases; 4929 NumAliases = llvm::array_lengthof(GCCRegAliases); 4930 } 4931 4932 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4933 class SparcV8TargetInfo : public SparcTargetInfo { 4934 public: 4935 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4936 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 4937 } 4938 4939 void getTargetDefines(const LangOptions &Opts, 4940 MacroBuilder &Builder) const override { 4941 SparcTargetInfo::getTargetDefines(Opts, Builder); 4942 Builder.defineMacro("__sparcv8"); 4943 } 4944 }; 4945 4946 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4947 class SparcV9TargetInfo : public SparcTargetInfo { 4948 public: 4949 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4950 // FIXME: Support Sparc quad-precision long double? 4951 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 4952 // This is an LP64 platform. 4953 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4954 4955 // OpenBSD uses long long for int64_t and intmax_t. 4956 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4957 IntMaxType = SignedLongLong; 4958 UIntMaxType = UnsignedLongLong; 4959 } else { 4960 IntMaxType = SignedLong; 4961 UIntMaxType = UnsignedLong; 4962 } 4963 Int64Type = IntMaxType; 4964 4965 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 4966 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 4967 LongDoubleWidth = 128; 4968 LongDoubleAlign = 128; 4969 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4970 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4971 } 4972 4973 void getTargetDefines(const LangOptions &Opts, 4974 MacroBuilder &Builder) const override { 4975 SparcTargetInfo::getTargetDefines(Opts, Builder); 4976 Builder.defineMacro("__sparcv9"); 4977 Builder.defineMacro("__arch64__"); 4978 // Solaris and its derivative AuroraUX don't need these variants, but the 4979 // BSDs do. 4980 if (getTriple().getOS() != llvm::Triple::Solaris && 4981 getTriple().getOS() != llvm::Triple::AuroraUX) { 4982 Builder.defineMacro("__sparc64__"); 4983 Builder.defineMacro("__sparc_v9__"); 4984 Builder.defineMacro("__sparcv9__"); 4985 } 4986 } 4987 4988 bool setCPU(const std::string &Name) override { 4989 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4990 .Case("v9", true) 4991 .Case("ultrasparc", true) 4992 .Case("ultrasparc3", true) 4993 .Case("niagara", true) 4994 .Case("niagara2", true) 4995 .Case("niagara3", true) 4996 .Case("niagara4", true) 4997 .Default(false); 4998 4999 // No need to store the CPU yet. There aren't any CPU-specific 5000 // macros to define. 5001 return CPUKnown; 5002 } 5003 }; 5004 5005 } // end anonymous namespace. 5006 5007 namespace { 5008 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 5009 public: 5010 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 5011 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 5012 SizeType = UnsignedInt; 5013 PtrDiffType = SignedInt; 5014 } 5015 }; 5016 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5017 public: 5018 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5019 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5020 SizeType = UnsignedInt; 5021 PtrDiffType = SignedInt; 5022 } 5023 }; 5024 } // end anonymous namespace. 5025 5026 namespace { 5027 class SystemZTargetInfo : public TargetInfo { 5028 static const char *const GCCRegNames[]; 5029 5030 public: 5031 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5032 TLSSupported = true; 5033 IntWidth = IntAlign = 32; 5034 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5035 PointerWidth = PointerAlign = 64; 5036 LongDoubleWidth = 128; 5037 LongDoubleAlign = 64; 5038 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5039 MinGlobalAlign = 16; 5040 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5041 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5042 } 5043 void getTargetDefines(const LangOptions &Opts, 5044 MacroBuilder &Builder) const override { 5045 Builder.defineMacro("__s390__"); 5046 Builder.defineMacro("__s390x__"); 5047 Builder.defineMacro("__zarch__"); 5048 Builder.defineMacro("__LONG_DOUBLE_128__"); 5049 } 5050 void getTargetBuiltins(const Builtin::Info *&Records, 5051 unsigned &NumRecords) const override { 5052 // FIXME: Implement. 5053 Records = nullptr; 5054 NumRecords = 0; 5055 } 5056 5057 void getGCCRegNames(const char *const *&Names, 5058 unsigned &NumNames) const override; 5059 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5060 unsigned &NumAliases) const override { 5061 // No aliases. 5062 Aliases = nullptr; 5063 NumAliases = 0; 5064 } 5065 bool validateAsmConstraint(const char *&Name, 5066 TargetInfo::ConstraintInfo &info) const override; 5067 const char *getClobbers() const override { 5068 // FIXME: Is this really right? 5069 return ""; 5070 } 5071 BuiltinVaListKind getBuiltinVaListKind() const override { 5072 return TargetInfo::SystemZBuiltinVaList; 5073 } 5074 bool setCPU(const std::string &Name) override { 5075 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5076 .Case("z10", true) 5077 .Case("z196", true) 5078 .Case("zEC12", true) 5079 .Default(false); 5080 5081 // No need to store the CPU yet. There aren't any CPU-specific 5082 // macros to define. 5083 return CPUKnown; 5084 } 5085 }; 5086 5087 const char *const SystemZTargetInfo::GCCRegNames[] = { 5088 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5089 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5090 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5091 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5092 }; 5093 5094 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5095 unsigned &NumNames) const { 5096 Names = GCCRegNames; 5097 NumNames = llvm::array_lengthof(GCCRegNames); 5098 } 5099 5100 bool SystemZTargetInfo:: 5101 validateAsmConstraint(const char *&Name, 5102 TargetInfo::ConstraintInfo &Info) const { 5103 switch (*Name) { 5104 default: 5105 return false; 5106 5107 case 'a': // Address register 5108 case 'd': // Data register (equivalent to 'r') 5109 case 'f': // Floating-point register 5110 Info.setAllowsRegister(); 5111 return true; 5112 5113 case 'I': // Unsigned 8-bit constant 5114 case 'J': // Unsigned 12-bit constant 5115 case 'K': // Signed 16-bit constant 5116 case 'L': // Signed 20-bit displacement (on all targets we support) 5117 case 'M': // 0x7fffffff 5118 return true; 5119 5120 case 'Q': // Memory with base and unsigned 12-bit displacement 5121 case 'R': // Likewise, plus an index 5122 case 'S': // Memory with base and signed 20-bit displacement 5123 case 'T': // Likewise, plus an index 5124 Info.setAllowsMemory(); 5125 return true; 5126 } 5127 } 5128 } 5129 5130 namespace { 5131 class MSP430TargetInfo : public TargetInfo { 5132 static const char * const GCCRegNames[]; 5133 public: 5134 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5135 BigEndian = false; 5136 TLSSupported = false; 5137 IntWidth = 16; IntAlign = 16; 5138 LongWidth = 32; LongLongWidth = 64; 5139 LongAlign = LongLongAlign = 16; 5140 PointerWidth = 16; PointerAlign = 16; 5141 SuitableAlign = 16; 5142 SizeType = UnsignedInt; 5143 IntMaxType = SignedLongLong; 5144 UIntMaxType = UnsignedLongLong; 5145 IntPtrType = SignedInt; 5146 PtrDiffType = SignedInt; 5147 SigAtomicType = SignedLong; 5148 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 5149 } 5150 void getTargetDefines(const LangOptions &Opts, 5151 MacroBuilder &Builder) const override { 5152 Builder.defineMacro("MSP430"); 5153 Builder.defineMacro("__MSP430__"); 5154 // FIXME: defines for different 'flavours' of MCU 5155 } 5156 void getTargetBuiltins(const Builtin::Info *&Records, 5157 unsigned &NumRecords) const override { 5158 // FIXME: Implement. 5159 Records = nullptr; 5160 NumRecords = 0; 5161 } 5162 bool hasFeature(StringRef Feature) const override { 5163 return Feature == "msp430"; 5164 } 5165 void getGCCRegNames(const char * const *&Names, 5166 unsigned &NumNames) const override; 5167 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5168 unsigned &NumAliases) const override { 5169 // No aliases. 5170 Aliases = nullptr; 5171 NumAliases = 0; 5172 } 5173 bool validateAsmConstraint(const char *&Name, 5174 TargetInfo::ConstraintInfo &info) const override { 5175 // No target constraints for now. 5176 return false; 5177 } 5178 const char *getClobbers() const override { 5179 // FIXME: Is this really right? 5180 return ""; 5181 } 5182 BuiltinVaListKind getBuiltinVaListKind() const override { 5183 // FIXME: implement 5184 return TargetInfo::CharPtrBuiltinVaList; 5185 } 5186 }; 5187 5188 const char * const MSP430TargetInfo::GCCRegNames[] = { 5189 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5190 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5191 }; 5192 5193 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5194 unsigned &NumNames) const { 5195 Names = GCCRegNames; 5196 NumNames = llvm::array_lengthof(GCCRegNames); 5197 } 5198 } 5199 5200 namespace { 5201 5202 // LLVM and Clang cannot be used directly to output native binaries for 5203 // target, but is used to compile C code to llvm bitcode with correct 5204 // type and alignment information. 5205 // 5206 // TCE uses the llvm bitcode as input and uses it for generating customized 5207 // target processor and program binary. TCE co-design environment is 5208 // publicly available in http://tce.cs.tut.fi 5209 5210 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5211 3, // opencl_global 5212 4, // opencl_local 5213 5, // opencl_constant 5214 0, // cuda_device 5215 0, // cuda_constant 5216 0 // cuda_shared 5217 }; 5218 5219 class TCETargetInfo : public TargetInfo{ 5220 public: 5221 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5222 TLSSupported = false; 5223 IntWidth = 32; 5224 LongWidth = LongLongWidth = 32; 5225 PointerWidth = 32; 5226 IntAlign = 32; 5227 LongAlign = LongLongAlign = 32; 5228 PointerAlign = 32; 5229 SuitableAlign = 32; 5230 SizeType = UnsignedInt; 5231 IntMaxType = SignedLong; 5232 UIntMaxType = UnsignedLong; 5233 IntPtrType = SignedInt; 5234 PtrDiffType = SignedInt; 5235 FloatWidth = 32; 5236 FloatAlign = 32; 5237 DoubleWidth = 32; 5238 DoubleAlign = 32; 5239 LongDoubleWidth = 32; 5240 LongDoubleAlign = 32; 5241 FloatFormat = &llvm::APFloat::IEEEsingle; 5242 DoubleFormat = &llvm::APFloat::IEEEsingle; 5243 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5244 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5245 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5246 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5247 UseAddrSpaceMapMangling = true; 5248 } 5249 5250 void getTargetDefines(const LangOptions &Opts, 5251 MacroBuilder &Builder) const override { 5252 DefineStd(Builder, "tce", Opts); 5253 Builder.defineMacro("__TCE__"); 5254 Builder.defineMacro("__TCE_V1__"); 5255 } 5256 bool hasFeature(StringRef Feature) const override { 5257 return Feature == "tce"; 5258 } 5259 5260 void getTargetBuiltins(const Builtin::Info *&Records, 5261 unsigned &NumRecords) const override {} 5262 const char *getClobbers() const override { 5263 return ""; 5264 } 5265 BuiltinVaListKind getBuiltinVaListKind() const override { 5266 return TargetInfo::VoidPtrBuiltinVaList; 5267 } 5268 void getGCCRegNames(const char * const *&Names, 5269 unsigned &NumNames) const override {} 5270 bool validateAsmConstraint(const char *&Name, 5271 TargetInfo::ConstraintInfo &info) const override{ 5272 return true; 5273 } 5274 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5275 unsigned &NumAliases) const override {} 5276 }; 5277 } 5278 5279 namespace { 5280 class MipsTargetInfoBase : public TargetInfo { 5281 virtual void setDescriptionString() = 0; 5282 5283 static const Builtin::Info BuiltinInfo[]; 5284 std::string CPU; 5285 bool IsMips16; 5286 bool IsMicromips; 5287 bool IsNan2008; 5288 bool IsSingleFloat; 5289 enum MipsFloatABI { 5290 HardFloat, SoftFloat 5291 } FloatABI; 5292 enum DspRevEnum { 5293 NoDSP, DSP1, DSP2 5294 } DspRev; 5295 bool HasMSA; 5296 5297 protected: 5298 bool HasFP64; 5299 std::string ABI; 5300 5301 public: 5302 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5303 const std::string &CPUStr) 5304 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5305 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5306 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 5307 5308 bool isNaN2008Default() const { 5309 return CPU == "mips32r6" || CPU == "mips64r6"; 5310 } 5311 5312 bool isFP64Default() const { 5313 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5314 } 5315 5316 StringRef getABI() const override { return ABI; } 5317 bool setCPU(const std::string &Name) override { 5318 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5319 getTriple().getArch() == llvm::Triple::mipsel; 5320 CPU = Name; 5321 return llvm::StringSwitch<bool>(Name) 5322 .Case("mips1", IsMips32) 5323 .Case("mips2", IsMips32) 5324 .Case("mips3", true) 5325 .Case("mips4", true) 5326 .Case("mips5", true) 5327 .Case("mips32", IsMips32) 5328 .Case("mips32r2", IsMips32) 5329 .Case("mips32r6", IsMips32) 5330 .Case("mips64", true) 5331 .Case("mips64r2", true) 5332 .Case("mips64r6", true) 5333 .Case("octeon", true) 5334 .Default(false); 5335 } 5336 const std::string& getCPU() const { return CPU; } 5337 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5338 // The backend enables certain ABI's by default according to the 5339 // architecture. 5340 // Disable both possible defaults so that we don't end up with multiple 5341 // ABI's selected and trigger an assertion. 5342 Features["o32"] = false; 5343 Features["n64"] = false; 5344 5345 Features[ABI] = true; 5346 if (CPU == "octeon") 5347 Features["mips64r2"] = Features["cnmips"] = true; 5348 else 5349 Features[CPU] = true; 5350 } 5351 5352 void getTargetDefines(const LangOptions &Opts, 5353 MacroBuilder &Builder) const override { 5354 Builder.defineMacro("__mips__"); 5355 Builder.defineMacro("_mips"); 5356 if (Opts.GNUMode) 5357 Builder.defineMacro("mips"); 5358 5359 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5360 5361 switch (FloatABI) { 5362 case HardFloat: 5363 Builder.defineMacro("__mips_hard_float", Twine(1)); 5364 break; 5365 case SoftFloat: 5366 Builder.defineMacro("__mips_soft_float", Twine(1)); 5367 break; 5368 } 5369 5370 if (IsSingleFloat) 5371 Builder.defineMacro("__mips_single_float", Twine(1)); 5372 5373 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5374 Builder.defineMacro("_MIPS_FPSET", 5375 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5376 5377 if (IsMips16) 5378 Builder.defineMacro("__mips16", Twine(1)); 5379 5380 if (IsMicromips) 5381 Builder.defineMacro("__mips_micromips", Twine(1)); 5382 5383 if (IsNan2008) 5384 Builder.defineMacro("__mips_nan2008", Twine(1)); 5385 5386 switch (DspRev) { 5387 default: 5388 break; 5389 case DSP1: 5390 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5391 Builder.defineMacro("__mips_dsp", Twine(1)); 5392 break; 5393 case DSP2: 5394 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5395 Builder.defineMacro("__mips_dspr2", Twine(1)); 5396 Builder.defineMacro("__mips_dsp", Twine(1)); 5397 break; 5398 } 5399 5400 if (HasMSA) 5401 Builder.defineMacro("__mips_msa", Twine(1)); 5402 5403 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5404 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5405 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5406 5407 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5408 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5409 } 5410 5411 void getTargetBuiltins(const Builtin::Info *&Records, 5412 unsigned &NumRecords) const override { 5413 Records = BuiltinInfo; 5414 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5415 } 5416 bool hasFeature(StringRef Feature) const override { 5417 return llvm::StringSwitch<bool>(Feature) 5418 .Case("mips", true) 5419 .Case("fp64", HasFP64) 5420 .Default(false); 5421 } 5422 BuiltinVaListKind getBuiltinVaListKind() const override { 5423 return TargetInfo::VoidPtrBuiltinVaList; 5424 } 5425 void getGCCRegNames(const char * const *&Names, 5426 unsigned &NumNames) const override { 5427 static const char *const GCCRegNames[] = { 5428 // CPU register names 5429 // Must match second column of GCCRegAliases 5430 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5431 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5432 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5433 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5434 // Floating point register names 5435 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5436 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5437 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5438 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5439 // Hi/lo and condition register names 5440 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5441 "$fcc5","$fcc6","$fcc7", 5442 // MSA register names 5443 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5444 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5445 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5446 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5447 // MSA control register names 5448 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5449 "$msarequest", "$msamap", "$msaunmap" 5450 }; 5451 Names = GCCRegNames; 5452 NumNames = llvm::array_lengthof(GCCRegNames); 5453 } 5454 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5455 unsigned &NumAliases) const override = 0; 5456 bool validateAsmConstraint(const char *&Name, 5457 TargetInfo::ConstraintInfo &Info) const override { 5458 switch (*Name) { 5459 default: 5460 return false; 5461 5462 case 'r': // CPU registers. 5463 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5464 case 'y': // Equivalent to "r", backwards compatibility only. 5465 case 'f': // floating-point registers. 5466 case 'c': // $25 for indirect jumps 5467 case 'l': // lo register 5468 case 'x': // hilo register pair 5469 Info.setAllowsRegister(); 5470 return true; 5471 case 'R': // An address that can be used in a non-macro load or store 5472 Info.setAllowsMemory(); 5473 return true; 5474 } 5475 } 5476 5477 const char *getClobbers() const override { 5478 // FIXME: Implement! 5479 return ""; 5480 } 5481 5482 bool handleTargetFeatures(std::vector<std::string> &Features, 5483 DiagnosticsEngine &Diags) override { 5484 IsMips16 = false; 5485 IsMicromips = false; 5486 IsNan2008 = isNaN2008Default(); 5487 IsSingleFloat = false; 5488 FloatABI = HardFloat; 5489 DspRev = NoDSP; 5490 HasFP64 = isFP64Default(); 5491 5492 for (std::vector<std::string>::iterator it = Features.begin(), 5493 ie = Features.end(); it != ie; ++it) { 5494 if (*it == "+single-float") 5495 IsSingleFloat = true; 5496 else if (*it == "+soft-float") 5497 FloatABI = SoftFloat; 5498 else if (*it == "+mips16") 5499 IsMips16 = true; 5500 else if (*it == "+micromips") 5501 IsMicromips = true; 5502 else if (*it == "+dsp") 5503 DspRev = std::max(DspRev, DSP1); 5504 else if (*it == "+dspr2") 5505 DspRev = std::max(DspRev, DSP2); 5506 else if (*it == "+msa") 5507 HasMSA = true; 5508 else if (*it == "+fp64") 5509 HasFP64 = true; 5510 else if (*it == "-fp64") 5511 HasFP64 = false; 5512 else if (*it == "+nan2008") 5513 IsNan2008 = true; 5514 else if (*it == "-nan2008") 5515 IsNan2008 = false; 5516 } 5517 5518 // Remove front-end specific options. 5519 std::vector<std::string>::iterator it = 5520 std::find(Features.begin(), Features.end(), "+soft-float"); 5521 if (it != Features.end()) 5522 Features.erase(it); 5523 5524 setDescriptionString(); 5525 5526 return true; 5527 } 5528 5529 int getEHDataRegisterNumber(unsigned RegNo) const override { 5530 if (RegNo == 0) return 4; 5531 if (RegNo == 1) return 5; 5532 return -1; 5533 } 5534 5535 bool isCLZForZeroUndef() const override { return false; } 5536 }; 5537 5538 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5539 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5540 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5541 ALL_LANGUAGES }, 5542 #include "clang/Basic/BuiltinsMips.def" 5543 }; 5544 5545 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5546 public: 5547 Mips32TargetInfoBase(const llvm::Triple &Triple) 5548 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5549 SizeType = UnsignedInt; 5550 PtrDiffType = SignedInt; 5551 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5552 } 5553 bool setABI(const std::string &Name) override { 5554 if (Name == "o32" || Name == "eabi") { 5555 ABI = Name; 5556 return true; 5557 } 5558 return false; 5559 } 5560 void getTargetDefines(const LangOptions &Opts, 5561 MacroBuilder &Builder) const override { 5562 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5563 5564 Builder.defineMacro("__mips", "32"); 5565 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 5566 5567 const std::string& CPUStr = getCPU(); 5568 if (CPUStr == "mips32") 5569 Builder.defineMacro("__mips_isa_rev", "1"); 5570 else if (CPUStr == "mips32r2") 5571 Builder.defineMacro("__mips_isa_rev", "2"); 5572 5573 if (ABI == "o32") { 5574 Builder.defineMacro("__mips_o32"); 5575 Builder.defineMacro("_ABIO32", "1"); 5576 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5577 } 5578 else if (ABI == "eabi") 5579 Builder.defineMacro("__mips_eabi"); 5580 else 5581 llvm_unreachable("Invalid ABI for Mips32."); 5582 } 5583 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5584 unsigned &NumAliases) const override { 5585 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5586 { { "at" }, "$1" }, 5587 { { "v0" }, "$2" }, 5588 { { "v1" }, "$3" }, 5589 { { "a0" }, "$4" }, 5590 { { "a1" }, "$5" }, 5591 { { "a2" }, "$6" }, 5592 { { "a3" }, "$7" }, 5593 { { "t0" }, "$8" }, 5594 { { "t1" }, "$9" }, 5595 { { "t2" }, "$10" }, 5596 { { "t3" }, "$11" }, 5597 { { "t4" }, "$12" }, 5598 { { "t5" }, "$13" }, 5599 { { "t6" }, "$14" }, 5600 { { "t7" }, "$15" }, 5601 { { "s0" }, "$16" }, 5602 { { "s1" }, "$17" }, 5603 { { "s2" }, "$18" }, 5604 { { "s3" }, "$19" }, 5605 { { "s4" }, "$20" }, 5606 { { "s5" }, "$21" }, 5607 { { "s6" }, "$22" }, 5608 { { "s7" }, "$23" }, 5609 { { "t8" }, "$24" }, 5610 { { "t9" }, "$25" }, 5611 { { "k0" }, "$26" }, 5612 { { "k1" }, "$27" }, 5613 { { "gp" }, "$28" }, 5614 { { "sp","$sp" }, "$29" }, 5615 { { "fp","$fp" }, "$30" }, 5616 { { "ra" }, "$31" } 5617 }; 5618 Aliases = GCCRegAliases; 5619 NumAliases = llvm::array_lengthof(GCCRegAliases); 5620 } 5621 }; 5622 5623 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5624 void setDescriptionString() override { 5625 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5626 } 5627 5628 public: 5629 Mips32EBTargetInfo(const llvm::Triple &Triple) 5630 : Mips32TargetInfoBase(Triple) { 5631 } 5632 void getTargetDefines(const LangOptions &Opts, 5633 MacroBuilder &Builder) const override { 5634 DefineStd(Builder, "MIPSEB", Opts); 5635 Builder.defineMacro("_MIPSEB"); 5636 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5637 } 5638 }; 5639 5640 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5641 void setDescriptionString() override { 5642 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5643 } 5644 5645 public: 5646 Mips32ELTargetInfo(const llvm::Triple &Triple) 5647 : Mips32TargetInfoBase(Triple) { 5648 BigEndian = false; 5649 } 5650 void getTargetDefines(const LangOptions &Opts, 5651 MacroBuilder &Builder) const override { 5652 DefineStd(Builder, "MIPSEL", Opts); 5653 Builder.defineMacro("_MIPSEL"); 5654 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5655 } 5656 }; 5657 5658 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5659 public: 5660 Mips64TargetInfoBase(const llvm::Triple &Triple) 5661 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5662 LongDoubleWidth = LongDoubleAlign = 128; 5663 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5664 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5665 LongDoubleWidth = LongDoubleAlign = 64; 5666 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5667 } 5668 setN64ABITypes(); 5669 SuitableAlign = 128; 5670 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5671 } 5672 5673 void setN64ABITypes() { 5674 LongWidth = LongAlign = 64; 5675 PointerWidth = PointerAlign = 64; 5676 SizeType = UnsignedLong; 5677 PtrDiffType = SignedLong; 5678 } 5679 5680 void setN32ABITypes() { 5681 LongWidth = LongAlign = 32; 5682 PointerWidth = PointerAlign = 32; 5683 SizeType = UnsignedInt; 5684 PtrDiffType = SignedInt; 5685 } 5686 5687 bool setABI(const std::string &Name) override { 5688 if (Name == "n32") { 5689 setN32ABITypes(); 5690 ABI = Name; 5691 return true; 5692 } 5693 if (Name == "n64") { 5694 setN64ABITypes(); 5695 ABI = Name; 5696 return true; 5697 } 5698 return false; 5699 } 5700 5701 void getTargetDefines(const LangOptions &Opts, 5702 MacroBuilder &Builder) const override { 5703 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5704 5705 Builder.defineMacro("__mips", "64"); 5706 Builder.defineMacro("__mips64"); 5707 Builder.defineMacro("__mips64__"); 5708 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 5709 5710 const std::string& CPUStr = getCPU(); 5711 if (CPUStr == "mips64") 5712 Builder.defineMacro("__mips_isa_rev", "1"); 5713 else if (CPUStr == "mips64r2") 5714 Builder.defineMacro("__mips_isa_rev", "2"); 5715 5716 if (ABI == "n32") { 5717 Builder.defineMacro("__mips_n32"); 5718 Builder.defineMacro("_ABIN32", "2"); 5719 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5720 } 5721 else if (ABI == "n64") { 5722 Builder.defineMacro("__mips_n64"); 5723 Builder.defineMacro("_ABI64", "3"); 5724 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5725 } 5726 else 5727 llvm_unreachable("Invalid ABI for Mips64."); 5728 } 5729 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5730 unsigned &NumAliases) const override { 5731 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5732 { { "at" }, "$1" }, 5733 { { "v0" }, "$2" }, 5734 { { "v1" }, "$3" }, 5735 { { "a0" }, "$4" }, 5736 { { "a1" }, "$5" }, 5737 { { "a2" }, "$6" }, 5738 { { "a3" }, "$7" }, 5739 { { "a4" }, "$8" }, 5740 { { "a5" }, "$9" }, 5741 { { "a6" }, "$10" }, 5742 { { "a7" }, "$11" }, 5743 { { "t0" }, "$12" }, 5744 { { "t1" }, "$13" }, 5745 { { "t2" }, "$14" }, 5746 { { "t3" }, "$15" }, 5747 { { "s0" }, "$16" }, 5748 { { "s1" }, "$17" }, 5749 { { "s2" }, "$18" }, 5750 { { "s3" }, "$19" }, 5751 { { "s4" }, "$20" }, 5752 { { "s5" }, "$21" }, 5753 { { "s6" }, "$22" }, 5754 { { "s7" }, "$23" }, 5755 { { "t8" }, "$24" }, 5756 { { "t9" }, "$25" }, 5757 { { "k0" }, "$26" }, 5758 { { "k1" }, "$27" }, 5759 { { "gp" }, "$28" }, 5760 { { "sp","$sp" }, "$29" }, 5761 { { "fp","$fp" }, "$30" }, 5762 { { "ra" }, "$31" } 5763 }; 5764 Aliases = GCCRegAliases; 5765 NumAliases = llvm::array_lengthof(GCCRegAliases); 5766 } 5767 5768 bool hasInt128Type() const override { return true; } 5769 }; 5770 5771 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5772 void setDescriptionString() override { 5773 if (ABI == "n32") 5774 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5775 else 5776 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5777 5778 } 5779 5780 public: 5781 Mips64EBTargetInfo(const llvm::Triple &Triple) 5782 : Mips64TargetInfoBase(Triple) {} 5783 void getTargetDefines(const LangOptions &Opts, 5784 MacroBuilder &Builder) const override { 5785 DefineStd(Builder, "MIPSEB", Opts); 5786 Builder.defineMacro("_MIPSEB"); 5787 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5788 } 5789 }; 5790 5791 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5792 void setDescriptionString() override { 5793 if (ABI == "n32") 5794 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5795 else 5796 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5797 } 5798 public: 5799 Mips64ELTargetInfo(const llvm::Triple &Triple) 5800 : Mips64TargetInfoBase(Triple) { 5801 // Default ABI is n64. 5802 BigEndian = false; 5803 } 5804 void getTargetDefines(const LangOptions &Opts, 5805 MacroBuilder &Builder) const override { 5806 DefineStd(Builder, "MIPSEL", Opts); 5807 Builder.defineMacro("_MIPSEL"); 5808 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5809 } 5810 }; 5811 } // end anonymous namespace. 5812 5813 namespace { 5814 class PNaClTargetInfo : public TargetInfo { 5815 public: 5816 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5817 BigEndian = false; 5818 this->UserLabelPrefix = ""; 5819 this->LongAlign = 32; 5820 this->LongWidth = 32; 5821 this->PointerAlign = 32; 5822 this->PointerWidth = 32; 5823 this->IntMaxType = TargetInfo::SignedLongLong; 5824 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5825 this->Int64Type = TargetInfo::SignedLongLong; 5826 this->DoubleAlign = 64; 5827 this->LongDoubleWidth = 64; 5828 this->LongDoubleAlign = 64; 5829 this->SizeType = TargetInfo::UnsignedInt; 5830 this->PtrDiffType = TargetInfo::SignedInt; 5831 this->IntPtrType = TargetInfo::SignedInt; 5832 this->RegParmMax = 0; // Disallow regparm 5833 } 5834 5835 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5836 } 5837 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 5838 Builder.defineMacro("__le32__"); 5839 Builder.defineMacro("__pnacl__"); 5840 } 5841 void getTargetDefines(const LangOptions &Opts, 5842 MacroBuilder &Builder) const override { 5843 getArchDefines(Opts, Builder); 5844 } 5845 bool hasFeature(StringRef Feature) const override { 5846 return Feature == "pnacl"; 5847 } 5848 void getTargetBuiltins(const Builtin::Info *&Records, 5849 unsigned &NumRecords) const override { 5850 } 5851 BuiltinVaListKind getBuiltinVaListKind() const override { 5852 return TargetInfo::PNaClABIBuiltinVaList; 5853 } 5854 void getGCCRegNames(const char * const *&Names, 5855 unsigned &NumNames) const override; 5856 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5857 unsigned &NumAliases) const override; 5858 bool validateAsmConstraint(const char *&Name, 5859 TargetInfo::ConstraintInfo &Info) const override { 5860 return false; 5861 } 5862 5863 const char *getClobbers() const override { 5864 return ""; 5865 } 5866 }; 5867 5868 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5869 unsigned &NumNames) const { 5870 Names = nullptr; 5871 NumNames = 0; 5872 } 5873 5874 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5875 unsigned &NumAliases) const { 5876 Aliases = nullptr; 5877 NumAliases = 0; 5878 } 5879 } // end anonymous namespace. 5880 5881 namespace { 5882 static const unsigned SPIRAddrSpaceMap[] = { 5883 1, // opencl_global 5884 3, // opencl_local 5885 2, // opencl_constant 5886 0, // cuda_device 5887 0, // cuda_constant 5888 0 // cuda_shared 5889 }; 5890 class SPIRTargetInfo : public TargetInfo { 5891 public: 5892 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5893 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5894 "SPIR target must use unknown OS"); 5895 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5896 "SPIR target must use unknown environment type"); 5897 BigEndian = false; 5898 TLSSupported = false; 5899 LongWidth = LongAlign = 64; 5900 AddrSpaceMap = &SPIRAddrSpaceMap; 5901 UseAddrSpaceMapMangling = true; 5902 // Define available target features 5903 // These must be defined in sorted order! 5904 NoAsmVariants = true; 5905 } 5906 void getTargetDefines(const LangOptions &Opts, 5907 MacroBuilder &Builder) const override { 5908 DefineStd(Builder, "SPIR", Opts); 5909 } 5910 bool hasFeature(StringRef Feature) const override { 5911 return Feature == "spir"; 5912 } 5913 5914 void getTargetBuiltins(const Builtin::Info *&Records, 5915 unsigned &NumRecords) const override {} 5916 const char *getClobbers() const override { 5917 return ""; 5918 } 5919 void getGCCRegNames(const char * const *&Names, 5920 unsigned &NumNames) const override {} 5921 bool validateAsmConstraint(const char *&Name, 5922 TargetInfo::ConstraintInfo &info) const override { 5923 return true; 5924 } 5925 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5926 unsigned &NumAliases) const override {} 5927 BuiltinVaListKind getBuiltinVaListKind() const override { 5928 return TargetInfo::VoidPtrBuiltinVaList; 5929 } 5930 }; 5931 5932 5933 class SPIR32TargetInfo : public SPIRTargetInfo { 5934 public: 5935 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5936 PointerWidth = PointerAlign = 32; 5937 SizeType = TargetInfo::UnsignedInt; 5938 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5939 DescriptionString 5940 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 5941 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5942 } 5943 void getTargetDefines(const LangOptions &Opts, 5944 MacroBuilder &Builder) const override { 5945 DefineStd(Builder, "SPIR32", Opts); 5946 } 5947 }; 5948 5949 class SPIR64TargetInfo : public SPIRTargetInfo { 5950 public: 5951 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5952 PointerWidth = PointerAlign = 64; 5953 SizeType = TargetInfo::UnsignedLong; 5954 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5955 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 5956 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5957 } 5958 void getTargetDefines(const LangOptions &Opts, 5959 MacroBuilder &Builder) const override { 5960 DefineStd(Builder, "SPIR64", Opts); 5961 } 5962 }; 5963 } 5964 5965 namespace { 5966 class XCoreTargetInfo : public TargetInfo { 5967 static const Builtin::Info BuiltinInfo[]; 5968 public: 5969 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5970 BigEndian = false; 5971 NoAsmVariants = true; 5972 LongLongAlign = 32; 5973 SuitableAlign = 32; 5974 DoubleAlign = LongDoubleAlign = 32; 5975 SizeType = UnsignedInt; 5976 PtrDiffType = SignedInt; 5977 IntPtrType = SignedInt; 5978 WCharType = UnsignedChar; 5979 WIntType = UnsignedInt; 5980 UseZeroLengthBitfieldAlignment = true; 5981 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 5982 "-f64:32-a:0:32-n32"; 5983 } 5984 void getTargetDefines(const LangOptions &Opts, 5985 MacroBuilder &Builder) const override { 5986 Builder.defineMacro("__XS1B__"); 5987 } 5988 void getTargetBuiltins(const Builtin::Info *&Records, 5989 unsigned &NumRecords) const override { 5990 Records = BuiltinInfo; 5991 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5992 } 5993 BuiltinVaListKind getBuiltinVaListKind() const override { 5994 return TargetInfo::VoidPtrBuiltinVaList; 5995 } 5996 const char *getClobbers() const override { 5997 return ""; 5998 } 5999 void getGCCRegNames(const char * const *&Names, 6000 unsigned &NumNames) const override { 6001 static const char * const GCCRegNames[] = { 6002 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6003 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6004 }; 6005 Names = GCCRegNames; 6006 NumNames = llvm::array_lengthof(GCCRegNames); 6007 } 6008 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6009 unsigned &NumAliases) const override { 6010 Aliases = nullptr; 6011 NumAliases = 0; 6012 } 6013 bool validateAsmConstraint(const char *&Name, 6014 TargetInfo::ConstraintInfo &Info) const override { 6015 return false; 6016 } 6017 int getEHDataRegisterNumber(unsigned RegNo) const override { 6018 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6019 return (RegNo < 2)? RegNo : -1; 6020 } 6021 }; 6022 6023 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6024 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6025 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6026 ALL_LANGUAGES }, 6027 #include "clang/Basic/BuiltinsXCore.def" 6028 }; 6029 } // end anonymous namespace. 6030 6031 6032 //===----------------------------------------------------------------------===// 6033 // Driver code 6034 //===----------------------------------------------------------------------===// 6035 6036 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6037 llvm::Triple::OSType os = Triple.getOS(); 6038 6039 switch (Triple.getArch()) { 6040 default: 6041 return nullptr; 6042 6043 case llvm::Triple::xcore: 6044 return new XCoreTargetInfo(Triple); 6045 6046 case llvm::Triple::hexagon: 6047 return new HexagonTargetInfo(Triple); 6048 6049 case llvm::Triple::aarch64: 6050 case llvm::Triple::arm64: 6051 if (Triple.isOSDarwin()) 6052 return new DarwinAArch64TargetInfo(Triple); 6053 6054 switch (os) { 6055 case llvm::Triple::Linux: 6056 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6057 case llvm::Triple::NetBSD: 6058 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6059 default: 6060 return new AArch64leTargetInfo(Triple); 6061 } 6062 6063 case llvm::Triple::aarch64_be: 6064 case llvm::Triple::arm64_be: 6065 switch (os) { 6066 case llvm::Triple::Linux: 6067 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6068 case llvm::Triple::NetBSD: 6069 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6070 default: 6071 return new AArch64beTargetInfo(Triple); 6072 } 6073 6074 case llvm::Triple::arm: 6075 case llvm::Triple::thumb: 6076 if (Triple.isOSBinFormatMachO()) 6077 return new DarwinARMTargetInfo(Triple); 6078 6079 switch (os) { 6080 case llvm::Triple::Linux: 6081 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6082 case llvm::Triple::FreeBSD: 6083 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6084 case llvm::Triple::NetBSD: 6085 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6086 case llvm::Triple::OpenBSD: 6087 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6088 case llvm::Triple::Bitrig: 6089 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6090 case llvm::Triple::RTEMS: 6091 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6092 case llvm::Triple::NaCl: 6093 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6094 case llvm::Triple::Win32: 6095 switch (Triple.getEnvironment()) { 6096 default: 6097 return new ARMleTargetInfo(Triple); 6098 case llvm::Triple::Itanium: 6099 return new ItaniumWindowsARMleTargetInfo(Triple); 6100 case llvm::Triple::MSVC: 6101 return new MicrosoftARMleTargetInfo(Triple); 6102 } 6103 default: 6104 return new ARMleTargetInfo(Triple); 6105 } 6106 6107 case llvm::Triple::armeb: 6108 case llvm::Triple::thumbeb: 6109 if (Triple.isOSDarwin()) 6110 return new DarwinARMTargetInfo(Triple); 6111 6112 switch (os) { 6113 case llvm::Triple::Linux: 6114 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6115 case llvm::Triple::FreeBSD: 6116 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6117 case llvm::Triple::NetBSD: 6118 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6119 case llvm::Triple::OpenBSD: 6120 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6121 case llvm::Triple::Bitrig: 6122 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6123 case llvm::Triple::RTEMS: 6124 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6125 case llvm::Triple::NaCl: 6126 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6127 default: 6128 return new ARMbeTargetInfo(Triple); 6129 } 6130 6131 case llvm::Triple::msp430: 6132 return new MSP430TargetInfo(Triple); 6133 6134 case llvm::Triple::mips: 6135 switch (os) { 6136 case llvm::Triple::Linux: 6137 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6138 case llvm::Triple::RTEMS: 6139 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6140 case llvm::Triple::FreeBSD: 6141 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6142 case llvm::Triple::NetBSD: 6143 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6144 default: 6145 return new Mips32EBTargetInfo(Triple); 6146 } 6147 6148 case llvm::Triple::mipsel: 6149 switch (os) { 6150 case llvm::Triple::Linux: 6151 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6152 case llvm::Triple::RTEMS: 6153 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6154 case llvm::Triple::FreeBSD: 6155 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6156 case llvm::Triple::NetBSD: 6157 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6158 case llvm::Triple::NaCl: 6159 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6160 default: 6161 return new Mips32ELTargetInfo(Triple); 6162 } 6163 6164 case llvm::Triple::mips64: 6165 switch (os) { 6166 case llvm::Triple::Linux: 6167 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6168 case llvm::Triple::RTEMS: 6169 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6170 case llvm::Triple::FreeBSD: 6171 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6172 case llvm::Triple::NetBSD: 6173 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6174 case llvm::Triple::OpenBSD: 6175 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6176 default: 6177 return new Mips64EBTargetInfo(Triple); 6178 } 6179 6180 case llvm::Triple::mips64el: 6181 switch (os) { 6182 case llvm::Triple::Linux: 6183 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6184 case llvm::Triple::RTEMS: 6185 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6186 case llvm::Triple::FreeBSD: 6187 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6188 case llvm::Triple::NetBSD: 6189 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6190 case llvm::Triple::OpenBSD: 6191 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6192 default: 6193 return new Mips64ELTargetInfo(Triple); 6194 } 6195 6196 case llvm::Triple::le32: 6197 switch (os) { 6198 case llvm::Triple::NaCl: 6199 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6200 default: 6201 return nullptr; 6202 } 6203 6204 case llvm::Triple::ppc: 6205 if (Triple.isOSDarwin()) 6206 return new DarwinPPC32TargetInfo(Triple); 6207 switch (os) { 6208 case llvm::Triple::Linux: 6209 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6210 case llvm::Triple::FreeBSD: 6211 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6212 case llvm::Triple::NetBSD: 6213 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6214 case llvm::Triple::OpenBSD: 6215 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6216 case llvm::Triple::RTEMS: 6217 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6218 default: 6219 return new PPC32TargetInfo(Triple); 6220 } 6221 6222 case llvm::Triple::ppc64: 6223 if (Triple.isOSDarwin()) 6224 return new DarwinPPC64TargetInfo(Triple); 6225 switch (os) { 6226 case llvm::Triple::Linux: 6227 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6228 case llvm::Triple::Lv2: 6229 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6230 case llvm::Triple::FreeBSD: 6231 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6232 case llvm::Triple::NetBSD: 6233 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6234 default: 6235 return new PPC64TargetInfo(Triple); 6236 } 6237 6238 case llvm::Triple::ppc64le: 6239 switch (os) { 6240 case llvm::Triple::Linux: 6241 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6242 default: 6243 return new PPC64TargetInfo(Triple); 6244 } 6245 6246 case llvm::Triple::nvptx: 6247 return new NVPTX32TargetInfo(Triple); 6248 case llvm::Triple::nvptx64: 6249 return new NVPTX64TargetInfo(Triple); 6250 6251 case llvm::Triple::r600: 6252 return new R600TargetInfo(Triple); 6253 6254 case llvm::Triple::sparc: 6255 switch (os) { 6256 case llvm::Triple::Linux: 6257 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6258 case llvm::Triple::AuroraUX: 6259 return new AuroraUXSparcV8TargetInfo(Triple); 6260 case llvm::Triple::Solaris: 6261 return new SolarisSparcV8TargetInfo(Triple); 6262 case llvm::Triple::NetBSD: 6263 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6264 case llvm::Triple::OpenBSD: 6265 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6266 case llvm::Triple::RTEMS: 6267 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6268 default: 6269 return new SparcV8TargetInfo(Triple); 6270 } 6271 6272 case llvm::Triple::sparcv9: 6273 switch (os) { 6274 case llvm::Triple::Linux: 6275 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6276 case llvm::Triple::AuroraUX: 6277 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 6278 case llvm::Triple::Solaris: 6279 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6280 case llvm::Triple::NetBSD: 6281 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6282 case llvm::Triple::OpenBSD: 6283 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6284 case llvm::Triple::FreeBSD: 6285 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6286 default: 6287 return new SparcV9TargetInfo(Triple); 6288 } 6289 6290 case llvm::Triple::systemz: 6291 switch (os) { 6292 case llvm::Triple::Linux: 6293 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6294 default: 6295 return new SystemZTargetInfo(Triple); 6296 } 6297 6298 case llvm::Triple::tce: 6299 return new TCETargetInfo(Triple); 6300 6301 case llvm::Triple::x86: 6302 if (Triple.isOSDarwin()) 6303 return new DarwinI386TargetInfo(Triple); 6304 6305 switch (os) { 6306 case llvm::Triple::AuroraUX: 6307 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 6308 case llvm::Triple::Linux: 6309 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6310 case llvm::Triple::DragonFly: 6311 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6312 case llvm::Triple::NetBSD: 6313 return new NetBSDI386TargetInfo(Triple); 6314 case llvm::Triple::OpenBSD: 6315 return new OpenBSDI386TargetInfo(Triple); 6316 case llvm::Triple::Bitrig: 6317 return new BitrigI386TargetInfo(Triple); 6318 case llvm::Triple::FreeBSD: 6319 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6320 case llvm::Triple::KFreeBSD: 6321 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6322 case llvm::Triple::Minix: 6323 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6324 case llvm::Triple::Solaris: 6325 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6326 case llvm::Triple::Win32: { 6327 switch (Triple.getEnvironment()) { 6328 default: 6329 return new X86_32TargetInfo(Triple); 6330 case llvm::Triple::Cygnus: 6331 return new CygwinX86_32TargetInfo(Triple); 6332 case llvm::Triple::GNU: 6333 return new MinGWX86_32TargetInfo(Triple); 6334 case llvm::Triple::Itanium: 6335 case llvm::Triple::MSVC: 6336 return new MicrosoftX86_32TargetInfo(Triple); 6337 } 6338 } 6339 case llvm::Triple::Haiku: 6340 return new HaikuX86_32TargetInfo(Triple); 6341 case llvm::Triple::RTEMS: 6342 return new RTEMSX86_32TargetInfo(Triple); 6343 case llvm::Triple::NaCl: 6344 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6345 default: 6346 return new X86_32TargetInfo(Triple); 6347 } 6348 6349 case llvm::Triple::x86_64: 6350 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6351 return new DarwinX86_64TargetInfo(Triple); 6352 6353 switch (os) { 6354 case llvm::Triple::AuroraUX: 6355 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 6356 case llvm::Triple::Linux: 6357 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6358 case llvm::Triple::DragonFly: 6359 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6360 case llvm::Triple::NetBSD: 6361 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6362 case llvm::Triple::OpenBSD: 6363 return new OpenBSDX86_64TargetInfo(Triple); 6364 case llvm::Triple::Bitrig: 6365 return new BitrigX86_64TargetInfo(Triple); 6366 case llvm::Triple::FreeBSD: 6367 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6368 case llvm::Triple::KFreeBSD: 6369 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6370 case llvm::Triple::Solaris: 6371 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6372 case llvm::Triple::Win32: { 6373 switch (Triple.getEnvironment()) { 6374 default: 6375 return new X86_64TargetInfo(Triple); 6376 case llvm::Triple::GNU: 6377 return new MinGWX86_64TargetInfo(Triple); 6378 case llvm::Triple::MSVC: 6379 return new MicrosoftX86_64TargetInfo(Triple); 6380 } 6381 } 6382 case llvm::Triple::NaCl: 6383 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6384 default: 6385 return new X86_64TargetInfo(Triple); 6386 } 6387 6388 case llvm::Triple::spir: { 6389 if (Triple.getOS() != llvm::Triple::UnknownOS || 6390 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6391 return nullptr; 6392 return new SPIR32TargetInfo(Triple); 6393 } 6394 case llvm::Triple::spir64: { 6395 if (Triple.getOS() != llvm::Triple::UnknownOS || 6396 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6397 return nullptr; 6398 return new SPIR64TargetInfo(Triple); 6399 } 6400 } 6401 } 6402 6403 /// CreateTargetInfo - Return the target info object for the specified target 6404 /// triple. 6405 TargetInfo * 6406 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6407 const std::shared_ptr<TargetOptions> &Opts) { 6408 llvm::Triple Triple(Opts->Triple); 6409 6410 // Construct the target 6411 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6412 if (!Target) { 6413 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6414 return nullptr; 6415 } 6416 Target->TargetOpts = Opts; 6417 6418 // Set the target CPU if specified. 6419 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6420 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6421 return nullptr; 6422 } 6423 6424 // Set the target ABI if specified. 6425 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6426 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6427 return nullptr; 6428 } 6429 6430 // Set the fp math unit. 6431 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6432 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6433 return nullptr; 6434 } 6435 6436 // Compute the default target features, we need the target to handle this 6437 // because features may have dependencies on one another. 6438 llvm::StringMap<bool> Features; 6439 Target->getDefaultFeatures(Features); 6440 6441 // Apply the user specified deltas. 6442 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6443 I < N; ++I) { 6444 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6445 // Apply the feature via the target. 6446 bool Enabled = Name[0] == '+'; 6447 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6448 } 6449 6450 // Add the features to the compile options. 6451 // 6452 // FIXME: If we are completely confident that we have the right set, we only 6453 // need to pass the minuses. 6454 Opts->Features.clear(); 6455 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6456 ie = Features.end(); it != ie; ++it) 6457 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6458 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6459 return nullptr; 6460 6461 return Target.release(); 6462 } 6463
