1 #ifndef _ASM_X86_HYPERV_H 2 #define _ASM_X86_HYPERV_H 3 4 #include <linux/types.h> 5 6 /* 7 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 8 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 9 */ 10 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 11 #define HYPERV_CPUID_INTERFACE 0x40000001 12 #define HYPERV_CPUID_VERSION 0x40000002 13 #define HYPERV_CPUID_FEATURES 0x40000003 14 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 15 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 16 17 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 18 #define HYPERV_CPUID_MIN 0x40000005 19 #define HYPERV_CPUID_MAX 0x4000ffff 20 21 /* 22 * Feature identification. EAX indicates which features are available 23 * to the partition based upon the current partition privileges. 24 */ 25 26 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ 27 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0) 28 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ 29 #define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1) 30 31 /* A partition's reference time stamp counter (TSC) page */ 32 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 33 34 /* 35 * There is a single feature flag that signifies the presence of the MSR 36 * that can be used to retrieve both the local APIC Timer frequency as 37 * well as the TSC frequency. 38 */ 39 40 /* Local APIC timer frequency MSR (HV_X64_MSR_APIC_FREQUENCY) is available */ 41 #define HV_X64_MSR_APIC_FREQUENCY_AVAILABLE (1 << 11) 42 43 /* TSC frequency MSR (HV_X64_MSR_TSC_FREQUENCY) is available */ 44 #define HV_X64_MSR_TSC_FREQUENCY_AVAILABLE (1 << 11) 45 46 /* 47 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM 48 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available 49 */ 50 #define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2) 51 /* 52 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through 53 * HV_X64_MSR_STIMER3_COUNT) available 54 */ 55 #define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3) 56 /* 57 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) 58 * are available 59 */ 60 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4) 61 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ 62 #define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5) 63 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ 64 #define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6) 65 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ 66 #define HV_X64_MSR_RESET_AVAILABLE (1 << 7) 67 /* 68 * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, 69 * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, 70 * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available 71 */ 72 #define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8) 73 74 /* 75 * Feature identification: EBX indicates which flags were specified at 76 * partition creation. The format is the same as the partition creation 77 * flag structure defined in section Partition Creation Flags. 78 */ 79 #define HV_X64_CREATE_PARTITIONS (1 << 0) 80 #define HV_X64_ACCESS_PARTITION_ID (1 << 1) 81 #define HV_X64_ACCESS_MEMORY_POOL (1 << 2) 82 #define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3) 83 #define HV_X64_POST_MESSAGES (1 << 4) 84 #define HV_X64_SIGNAL_EVENTS (1 << 5) 85 #define HV_X64_CREATE_PORT (1 << 6) 86 #define HV_X64_CONNECT_PORT (1 << 7) 87 #define HV_X64_ACCESS_STATS (1 << 8) 88 #define HV_X64_DEBUGGING (1 << 11) 89 #define HV_X64_CPU_POWER_MANAGEMENT (1 << 12) 90 #define HV_X64_CONFIGURE_PROFILER (1 << 13) 91 92 /* 93 * Feature identification. EDX indicates which miscellaneous features 94 * are available to the partition. 95 */ 96 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 97 #define HV_X64_MWAIT_AVAILABLE (1 << 0) 98 /* Guest debugging support is available */ 99 #define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1) 100 /* Performance Monitor support is available*/ 101 #define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2) 102 /* Support for physical CPU dynamic partitioning events is available*/ 103 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3) 104 /* 105 * Support for passing hypercall input parameter block via XMM 106 * registers is available 107 */ 108 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4) 109 /* Support for a virtual guest idle state is available */ 110 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5) 111 112 /* 113 * Implementation recommendations. Indicates which behaviors the hypervisor 114 * recommends the OS implement for optimal performance. 115 */ 116 /* 117 * Recommend using hypercall for address space switches rather 118 * than MOV to CR3 instruction 119 */ 120 #define HV_X64_MWAIT_RECOMMENDED (1 << 0) 121 /* Recommend using hypercall for local TLB flushes rather 122 * than INVLPG or MOV to CR3 instructions */ 123 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1) 124 /* 125 * Recommend using hypercall for remote TLB flushes rather 126 * than inter-processor interrupts 127 */ 128 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2) 129 /* 130 * Recommend using MSRs for accessing APIC registers 131 * EOI, ICR and TPR rather than their memory-mapped counterparts 132 */ 133 #define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3) 134 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 135 #define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4) 136 /* 137 * Recommend using relaxed timing for this partition. If used, 138 * the VM should disable any watchdog timeouts that rely on the 139 * timely delivery of external interrupts 140 */ 141 #define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5) 142 143 /* MSR used to identify the guest OS. */ 144 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 145 146 /* MSR used to setup pages used to communicate with the hypervisor. */ 147 #define HV_X64_MSR_HYPERCALL 0x40000001 148 149 /* MSR used to provide vcpu index */ 150 #define HV_X64_MSR_VP_INDEX 0x40000002 151 152 /* MSR used to read the per-partition time reference counter */ 153 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 154 155 /* MSR used to retrieve the TSC frequency */ 156 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 157 158 /* MSR used to retrieve the local APIC timer frequency */ 159 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 160 161 /* Define the virtual APIC registers */ 162 #define HV_X64_MSR_EOI 0x40000070 163 #define HV_X64_MSR_ICR 0x40000071 164 #define HV_X64_MSR_TPR 0x40000072 165 #define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073 166 167 /* Define synthetic interrupt controller model specific registers. */ 168 #define HV_X64_MSR_SCONTROL 0x40000080 169 #define HV_X64_MSR_SVERSION 0x40000081 170 #define HV_X64_MSR_SIEFP 0x40000082 171 #define HV_X64_MSR_SIMP 0x40000083 172 #define HV_X64_MSR_EOM 0x40000084 173 #define HV_X64_MSR_SINT0 0x40000090 174 #define HV_X64_MSR_SINT1 0x40000091 175 #define HV_X64_MSR_SINT2 0x40000092 176 #define HV_X64_MSR_SINT3 0x40000093 177 #define HV_X64_MSR_SINT4 0x40000094 178 #define HV_X64_MSR_SINT5 0x40000095 179 #define HV_X64_MSR_SINT6 0x40000096 180 #define HV_X64_MSR_SINT7 0x40000097 181 #define HV_X64_MSR_SINT8 0x40000098 182 #define HV_X64_MSR_SINT9 0x40000099 183 #define HV_X64_MSR_SINT10 0x4000009A 184 #define HV_X64_MSR_SINT11 0x4000009B 185 #define HV_X64_MSR_SINT12 0x4000009C 186 #define HV_X64_MSR_SINT13 0x4000009D 187 #define HV_X64_MSR_SINT14 0x4000009E 188 #define HV_X64_MSR_SINT15 0x4000009F 189 190 191 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 192 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 193 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 194 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 195 196 /* Declare the various hypercall operations. */ 197 #define HV_X64_HV_NOTIFY_LONG_SPIN_WAIT 0x0008 198 199 #define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001 200 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12 201 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \ 202 (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 203 204 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 205 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 206 207 #define HV_PROCESSOR_POWER_STATE_C0 0 208 #define HV_PROCESSOR_POWER_STATE_C1 1 209 #define HV_PROCESSOR_POWER_STATE_C2 2 210 #define HV_PROCESSOR_POWER_STATE_C3 3 211 212 /* hypercall status code */ 213 #define HV_STATUS_SUCCESS 0 214 #define HV_STATUS_INVALID_HYPERCALL_CODE 2 215 #define HV_STATUS_INVALID_HYPERCALL_INPUT 3 216 #define HV_STATUS_INVALID_ALIGNMENT 4 217 #define HV_STATUS_INSUFFICIENT_BUFFERS 19 218 219 typedef struct _HV_REFERENCE_TSC_PAGE { 220 __u32 tsc_sequence; 221 __u32 res1; 222 __u64 tsc_scale; 223 __s64 tsc_offset; 224 } HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; 225 226 #endif 227
