1 /* 2 * include/linux/spi/spidev.h 3 * 4 * Copyright (C) 2006 SWAPP 5 * Andrea Paterniani <a.paterniani (at) swapp-eng.it> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #ifndef SPIDEV_H 23 #define SPIDEV_H 24 25 #include <linux/types.h> 26 27 /* User space versions of kernel symbols for SPI clocking modes, 28 * matching <linux/spi/spi.h> 29 */ 30 31 #define SPI_CPHA 0x01 32 #define SPI_CPOL 0x02 33 34 #define SPI_MODE_0 (0|0) 35 #define SPI_MODE_1 (0|SPI_CPHA) 36 #define SPI_MODE_2 (SPI_CPOL|0) 37 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) 38 39 #define SPI_CS_HIGH 0x04 40 #define SPI_LSB_FIRST 0x08 41 #define SPI_3WIRE 0x10 42 #define SPI_LOOP 0x20 43 #define SPI_NO_CS 0x40 44 #define SPI_READY 0x80 45 46 /*---------------------------------------------------------------------------*/ 47 48 /* IOCTL commands */ 49 50 #define SPI_IOC_MAGIC 'k' 51 52 /** 53 * struct spi_ioc_transfer - describes a single SPI transfer 54 * @tx_buf: Holds pointer to userspace buffer with transmit data, or null. 55 * If no data is provided, zeroes are shifted out. 56 * @rx_buf: Holds pointer to userspace buffer for receive data, or null. 57 * @len: Length of tx and rx buffers, in bytes. 58 * @speed_hz: Temporary override of the device's bitrate. 59 * @bits_per_word: Temporary override of the device's wordsize. 60 * @delay_usecs: If nonzero, how long to delay after the last bit transfer 61 * before optionally deselecting the device before the next transfer. 62 * @cs_change: True to deselect device before starting the next transfer. 63 * 64 * This structure is mapped directly to the kernel spi_transfer structure; 65 * the fields have the same meanings, except of course that the pointers 66 * are in a different address space (and may be of different sizes in some 67 * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel). 68 * Zero-initialize the structure, including currently unused fields, to 69 * accommodate potential future updates. 70 * 71 * SPI_IOC_MESSAGE gives userspace the equivalent of kernel spi_sync(). 72 * Pass it an array of related transfers, they'll execute together. 73 * Each transfer may be half duplex (either direction) or full duplex. 74 * 75 * struct spi_ioc_transfer mesg[4]; 76 * ... 77 * status = ioctl(fd, SPI_IOC_MESSAGE(4), mesg); 78 * 79 * So for example one transfer might send a nine bit command (right aligned 80 * in a 16-bit word), the next could read a block of 8-bit data before 81 * terminating that command by temporarily deselecting the chip; the next 82 * could send a different nine bit command (re-selecting the chip), and the 83 * last transfer might write some register values. 84 */ 85 struct spi_ioc_transfer { 86 __u64 tx_buf; 87 __u64 rx_buf; 88 89 __u32 len; 90 __u32 speed_hz; 91 92 __u16 delay_usecs; 93 __u8 bits_per_word; 94 __u8 cs_change; 95 __u32 pad; 96 97 /* If the contents of 'struct spi_ioc_transfer' ever change 98 * incompatibly, then the ioctl number (currently 0) must change; 99 * ioctls with constant size fields get a bit more in the way of 100 * error checking than ones (like this) where that field varies. 101 * 102 * NOTE: struct layout is the same in 64bit and 32bit userspace. 103 */ 104 }; 105 106 /* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */ 107 #define SPI_MSGSIZE(N) \ 108 ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ 109 ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) 110 #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) 111 112 113 /* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) */ 114 #define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, __u8) 115 #define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, __u8) 116 117 /* Read / Write SPI bit justification */ 118 #define SPI_IOC_RD_LSB_FIRST _IOR(SPI_IOC_MAGIC, 2, __u8) 119 #define SPI_IOC_WR_LSB_FIRST _IOW(SPI_IOC_MAGIC, 2, __u8) 120 121 /* Read / Write SPI device word length (1..N) */ 122 #define SPI_IOC_RD_BITS_PER_WORD _IOR(SPI_IOC_MAGIC, 3, __u8) 123 #define SPI_IOC_WR_BITS_PER_WORD _IOW(SPI_IOC_MAGIC, 3, __u8) 124 125 /* Read / Write SPI device default max speed hz */ 126 #define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32) 127 #define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32) 128 129 130 131 #endif /* SPIDEV_H */ 132
