1 perf-list(1) 2 ============ 3 4 NAME 5 ---- 6 perf-list - List all symbolic event types 7 8 SYNOPSIS 9 -------- 10 [verse] 11 'perf list' [hw|sw|cache|tracepoint|pmu|event_glob] 12 13 DESCRIPTION 14 ----------- 15 This command displays the symbolic event types which can be selected in the 16 various perf commands with the -e option. 17 18 [[EVENT_MODIFIERS]] 19 EVENT MODIFIERS 20 --------------- 21 22 Events can optionally have a modifer by appending a colon and one or 23 more modifiers. Modifiers allow the user to restrict the events to be 24 counted. The following modifiers exist: 25 26 u - user-space counting 27 k - kernel counting 28 h - hypervisor counting 29 G - guest counting (in KVM guests) 30 H - host counting (not in KVM guests) 31 p - precise level 32 S - read sample value (PERF_SAMPLE_READ) 33 D - pin the event to the PMU 34 35 The 'p' modifier can be used for specifying how precise the instruction 36 address should be. The 'p' modifier can be specified multiple times: 37 38 0 - SAMPLE_IP can have arbitrary skid 39 1 - SAMPLE_IP must have constant skid 40 2 - SAMPLE_IP requested to have 0 skid 41 3 - SAMPLE_IP must have 0 skid 42 43 For Intel systems precise event sampling is implemented with PEBS 44 which supports up to precise-level 2. 45 46 On AMD systems it is implemented using IBS (up to precise-level 2). 47 The precise modifier works with event types 0x76 (cpu-cycles, CPU 48 clocks not halted) and 0xC1 (micro-ops retired). Both events map to 49 IBS execution sampling (IBS op) with the IBS Op Counter Control bit 50 (IbsOpCntCtl) set respectively (see AMD64 Architecture Programmers 51 Manual Volume 2: System Programming, 13.3 Instruction-Based 52 Sampling). Examples to use IBS: 53 54 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles 55 perf record -a -e r076:p ... # same as -e cpu-cycles:p 56 perf record -a -e r0C1:p ... # use ibs op counting micro-ops 57 58 RAW HARDWARE EVENT DESCRIPTOR 59 ----------------------------- 60 Even when an event is not available in a symbolic form within perf right now, 61 it can be encoded in a per processor specific way. 62 63 For instance For x86 CPUs NNN represents the raw register encoding with the 64 layout of IA32_PERFEVTSELx MSRs (see [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout 65 of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmers Manual Volume 2: System Programming], Page 344, 66 Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). 67 68 Note: Only the following bit fields can be set in x86 counter 69 registers: event, umask, edge, inv, cmask. Esp. guest/host only and 70 OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT 71 MODIFIERS>>. 72 73 Example: 74 75 If the Intel docs for a QM720 Core i7 describe an event as: 76 77 Event Umask Event Mask 78 Num. Value Mnemonic Description Comment 79 80 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and 81 delivered by loop stream detector invert to count 82 cycles 83 84 raw encoding of 0x1A8 can be used: 85 86 perf stat -e r1a8 -a sleep 1 87 perf record -e r1a8 ... 88 89 You should refer to the processor specific documentation for getting these 90 details. Some of them are referenced in the SEE ALSO section below. 91 92 OPTIONS 93 ------- 94 95 Without options all known events will be listed. 96 97 To limit the list use: 98 99 . 'hw' or 'hardware' to list hardware events such as cache-misses, etc. 100 101 . 'sw' or 'software' to list software events such as context switches, etc. 102 103 . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc. 104 105 . 'tracepoint' to list all tracepoint events, alternatively use 106 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched, 107 block, etc. 108 109 . 'pmu' to print the kernel supplied PMU events. 110 111 . If none of the above is matched, it will apply the supplied glob to all 112 events, printing the ones that match. 113 114 One or more types can be used at the same time, listing the events for the 115 types specified. 116 117 SEE ALSO 118 -------- 119 linkperf:perf-stat[1], linkperf:perf-top[1], 120 linkperf:perf-record[1], 121 http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], 122 http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmers Manual Volume 2: System Programming] 123
