1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 //===----------------------------------------------------------------------===// 14 // Target-independent interfaces which we are implementing 15 //===----------------------------------------------------------------------===// 16 17 include "llvm/Target/Target.td" 18 19 //===----------------------------------------------------------------------===// 20 // ARM Subtarget state. 21 // 22 23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", 24 "Thumb mode">; 25 26 //===----------------------------------------------------------------------===// 27 // ARM Subtarget features. 28 // 29 30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 31 "Enable VFP2 instructions">; 32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 33 "Enable VFP3 instructions", 34 [FeatureVFP2]>; 35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 36 "Enable NEON instructions", 37 [FeatureVFP3]>; 38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 39 "Enable Thumb2 instructions">; 40 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 41 "Does not support ARM mode execution", 42 [ModeThumb]>; 43 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 44 "Enable half-precision floating point">; 45 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", 46 "Enable VFP4 instructions", 47 [FeatureVFP3, FeatureFP16]>; 48 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", 49 "true", "Enable ARMv8 FP", 50 [FeatureVFP4]>; 51 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 52 "Restrict VFP3 to 16 double registers">; 53 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", 54 "Enable divide instructions">; 55 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 56 "HasHardwareDivideInARM", "true", 57 "Enable divide instructions in ARM mode">; 58 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", 59 "Enable Thumb2 extract and pack instructions">; 60 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 61 "Has data barrier (dmb / dsb) instructions">; 62 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 63 "FP compare + branch is slow">; 64 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 65 "Floating point unit supports single precision only">; 66 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 67 "Enable support for Performance Monitor extensions">; 68 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 69 "Enable support for TrustZone security extensions">; 70 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 71 "Enable support for Cryptography extensions", 72 [FeatureNEON]>; 73 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 74 "Enable support for CRC instructions">; 75 76 // Cyclone has preferred instructions for zeroing VFP registers, which can 77 // execute in 0 cycles. 78 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 79 "Has zero-cycle zeroing instructions">; 80 81 // Some processors have FP multiply-accumulate instructions that don't 82 // play nicely with other VFP / NEON instructions, and it's generally better 83 // to just not use them. 84 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 85 "Disable VFP / NEON MAC instructions">; 86 87 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 88 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 89 "HasVMLxForwarding", "true", 90 "Has multiplier accumulator forwarding">; 91 92 // Some processors benefit from using NEON instructions for scalar 93 // single-precision FP operations. 94 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", 95 "true", 96 "Use NEON for single precision FP">; 97 98 // Disable 32-bit to 16-bit narrowing for experimentation. 99 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 100 "Prefer 32-bit Thumb instrs">; 101 102 /// Some instructions update CPSR partially, which can add false dependency for 103 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 104 /// mapped to a separate physical register. Avoid partial CPSR update for these 105 /// processors. 106 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 107 "AvoidCPSRPartialUpdate", "true", 108 "Avoid CPSR partial update for OOO execution">; 109 110 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 111 "AvoidMOVsShifterOperand", "true", 112 "Avoid movs instructions with shifter operand">; 113 114 // Some processors perform return stack prediction. CodeGen should avoid issue 115 // "normal" call instructions to callees which do not return. 116 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true", 117 "Has return address stack">; 118 119 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M) 120 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true", 121 "Supports v7 DSP instructions in Thumb2">; 122 123 // Multiprocessing extension. 124 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 125 "Supports Multiprocessing extension">; 126 127 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 128 def FeatureVirtualization : SubtargetFeature<"virtualization", 129 "HasVirtualization", "true", 130 "Supports Virtualization extension", 131 [FeatureHWDiv, FeatureHWDivARM]>; 132 133 // M-series ISA 134 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 135 "Is microcontroller profile ('M' series)">; 136 137 // R-series ISA 138 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 139 "Is realtime profile ('R' series)">; 140 141 // A-series ISA 142 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 143 "Is application profile ('A' series)">; 144 145 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 146 // See ARMInstrInfo.td for details. 147 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 148 "NaCl trap">; 149 150 // ARM ISAs. 151 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 152 "Support ARM v4T instructions">; 153 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 154 "Support ARM v5T instructions", 155 [HasV4TOps]>; 156 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 157 "Support ARM v5TE, v5TEj, and v5TExp instructions", 158 [HasV5TOps]>; 159 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 160 "Support ARM v6 instructions", 161 [HasV5TEOps]>; 162 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 163 "Support ARM v6M instructions", 164 [HasV6Ops]>; 165 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 166 "Support ARM v6t2 instructions", 167 [HasV6MOps, FeatureThumb2]>; 168 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 169 "Support ARM v7 instructions", 170 [HasV6T2Ops, FeaturePerfMon]>; 171 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 172 "Support ARM v8 instructions", 173 [HasV7Ops, FeatureVirtualization, 174 FeatureMP]>; 175 176 //===----------------------------------------------------------------------===// 177 // ARM Processors supported. 178 // 179 180 include "ARMSchedule.td" 181 182 // ARM processor families. 183 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 184 "Cortex-A5 ARM processors", 185 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, 186 FeatureVMLxForwarding, FeatureT2XtPk, 187 FeatureTrustZone, FeatureMP]>; 188 def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 189 "Cortex-A7 ARM processors", 190 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, 191 FeatureVMLxForwarding, FeatureT2XtPk, 192 FeatureVFP4, FeatureMP, 193 FeatureHWDiv, FeatureHWDivARM, 194 FeatureTrustZone, FeatureVirtualization]>; 195 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 196 "Cortex-A8 ARM processors", 197 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, 198 FeatureVMLxForwarding, FeatureT2XtPk, 199 FeatureTrustZone]>; 200 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 201 "Cortex-A9 ARM processors", 202 [FeatureVMLxForwarding, 203 FeatureT2XtPk, FeatureFP16, 204 FeatureAvoidPartialCPSR, 205 FeatureTrustZone]>; 206 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 207 "Swift ARM processors", 208 [FeatureNEONForFP, FeatureT2XtPk, 209 FeatureVFP4, FeatureMP, FeatureHWDiv, 210 FeatureHWDivARM, FeatureAvoidPartialCPSR, 211 FeatureAvoidMOVsShOp, 212 FeatureHasSlowFPVMLx, FeatureTrustZone]>; 213 def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 214 "Cortex-A12 ARM processors", 215 [FeatureVMLxForwarding, 216 FeatureT2XtPk, FeatureVFP4, 217 FeatureHWDiv, FeatureHWDivARM, 218 FeatureAvoidPartialCPSR, 219 FeatureVirtualization, 220 FeatureTrustZone]>; 221 222 223 // FIXME: It has not been determined if A15 has these features. 224 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 225 "Cortex-A15 ARM processors", 226 [FeatureT2XtPk, FeatureVFP4, 227 FeatureMP, FeatureHWDiv, FeatureHWDivARM, 228 FeatureAvoidPartialCPSR, 229 FeatureTrustZone, FeatureVirtualization]>; 230 231 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 232 "Cortex-A53 ARM processors", 233 [FeatureHWDiv, FeatureHWDivARM, 234 FeatureTrustZone, FeatureT2XtPk, 235 FeatureCrypto, FeatureCRC]>; 236 237 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 238 "Cortex-A57 ARM processors", 239 [FeatureHWDiv, FeatureHWDivARM, 240 FeatureTrustZone, FeatureT2XtPk, 241 FeatureCrypto, FeatureCRC]>; 242 243 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 244 "Cortex-R5 ARM processors", 245 [FeatureSlowFPBrcc, 246 FeatureHWDiv, FeatureHWDivARM, 247 FeatureHasSlowFPVMLx, 248 FeatureAvoidPartialCPSR, 249 FeatureT2XtPk]>; 250 251 // FIXME: krait has currently the same features as A9 252 // plus VFP4 and hardware division features. 253 def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 254 "Qualcomm ARM processors", 255 [FeatureVMLxForwarding, 256 FeatureT2XtPk, FeatureFP16, 257 FeatureAvoidPartialCPSR, 258 FeatureTrustZone, 259 FeatureVFP4, 260 FeatureHWDiv, 261 FeatureHWDivARM]>; 262 263 264 def FeatureAPCS : SubtargetFeature<"apcs", "TargetABI", "ARM_ABI_APCS", 265 "Use the APCS ABI">; 266 267 def FeatureAAPCS : SubtargetFeature<"aapcs", "TargetABI", "ARM_ABI_AAPCS", 268 "Use the AAPCS ABI">; 269 270 // RenderScript-specific support for 64-bit long types on all targets 271 def FeatureLong64 : SubtargetFeature<"long64", "UseLong64", 272 "true", 273 "long type is forced to be 64-bit">; 274 275 class ProcNoItin<string Name, list<SubtargetFeature> Features> 276 : Processor<Name, NoItineraries, Features>; 277 278 // V4 Processors. 279 def : ProcNoItin<"generic", []>; 280 def : ProcNoItin<"arm8", []>; 281 def : ProcNoItin<"arm810", []>; 282 def : ProcNoItin<"strongarm", []>; 283 def : ProcNoItin<"strongarm110", []>; 284 def : ProcNoItin<"strongarm1100", []>; 285 def : ProcNoItin<"strongarm1110", []>; 286 287 // V4T Processors. 288 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>; 289 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>; 290 def : ProcNoItin<"arm710t", [HasV4TOps]>; 291 def : ProcNoItin<"arm720t", [HasV4TOps]>; 292 def : ProcNoItin<"arm9", [HasV4TOps]>; 293 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>; 294 def : ProcNoItin<"arm920", [HasV4TOps]>; 295 def : ProcNoItin<"arm920t", [HasV4TOps]>; 296 def : ProcNoItin<"arm922t", [HasV4TOps]>; 297 def : ProcNoItin<"arm940t", [HasV4TOps]>; 298 def : ProcNoItin<"ep9312", [HasV4TOps]>; 299 300 // V5T Processors. 301 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>; 302 def : ProcNoItin<"arm1020t", [HasV5TOps]>; 303 304 // V5TE Processors. 305 def : ProcNoItin<"arm9e", [HasV5TEOps]>; 306 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>; 307 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>; 308 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>; 309 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>; 310 def : ProcNoItin<"arm10e", [HasV5TEOps]>; 311 def : ProcNoItin<"arm1020e", [HasV5TEOps]>; 312 def : ProcNoItin<"arm1022e", [HasV5TEOps]>; 313 def : ProcNoItin<"xscale", [HasV5TEOps]>; 314 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>; 315 316 // V6 Processors. 317 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>; 318 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 319 FeatureHasSlowFPVMLx]>; 320 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>; 321 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 322 FeatureHasSlowFPVMLx]>; 323 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>; 324 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 325 FeatureHasSlowFPVMLx]>; 326 327 // V6M Processors. 328 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM, 329 FeatureDB, FeatureMClass]>; 330 331 // V6T2 Processors. 332 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops, 333 FeatureDSPThumb2]>; 334 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2, 335 FeatureHasSlowFPVMLx, 336 FeatureDSPThumb2]>; 337 338 // V7a Processors. 339 // FIXME: A5 has currently the same Schedule model as A8 340 def : ProcessorModel<"cortex-a5", CortexA8Model, 341 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB, 342 FeatureVFP4, FeatureDSPThumb2, 343 FeatureHasRAS, FeatureAClass]>; 344 def : ProcessorModel<"cortex-a7", CortexA8Model, 345 [ProcA7, HasV7Ops, FeatureNEON, FeatureDB, 346 FeatureDSPThumb2, FeatureHasRAS, 347 FeatureAClass]>; 348 def : ProcessorModel<"cortex-a8", CortexA8Model, 349 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB, 350 FeatureDSPThumb2, FeatureHasRAS, 351 FeatureAClass]>; 352 def : ProcessorModel<"cortex-a9", CortexA9Model, 353 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, 354 FeatureDSPThumb2, FeatureHasRAS, 355 FeatureAClass]>; 356 def : ProcessorModel<"cortex-a9-mp", CortexA9Model, 357 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, 358 FeatureDSPThumb2, FeatureMP, 359 FeatureHasRAS, FeatureAClass]>; 360 361 // FIXME: A12 has currently the same Schedule model as A9 362 def : ProcessorModel<"cortex-a12", CortexA9Model, 363 [ProcA12, HasV7Ops, FeatureNEON, FeatureDB, 364 FeatureDSPThumb2, FeatureMP, 365 FeatureHasRAS, FeatureAClass]>; 366 367 // FIXME: A15 has currently the same ProcessorModel as A9. 368 def : ProcessorModel<"cortex-a15", CortexA9Model, 369 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB, 370 FeatureDSPThumb2, FeatureHasRAS, 371 FeatureAClass]>; 372 373 // FIXME: krait has currently the same Schedule model as A9 374 def : ProcessorModel<"krait", CortexA9Model, 375 [ProcKrait, HasV7Ops, 376 FeatureNEON, FeatureDB, 377 FeatureDSPThumb2, FeatureHasRAS, 378 FeatureAClass]>; 379 380 // FIXME: R5 has currently the same ProcessorModel as A8. 381 def : ProcessorModel<"cortex-r5", CortexA8Model, 382 [ProcR5, HasV7Ops, FeatureDB, 383 FeatureVFP3, FeatureDSPThumb2, 384 FeatureHasRAS, FeatureVFPOnlySP, 385 FeatureD16, FeatureRClass]>; 386 387 // V7M Processors. 388 def : ProcNoItin<"cortex-m3", [HasV7Ops, 389 FeatureThumb2, FeatureNoARM, FeatureDB, 390 FeatureHWDiv, FeatureMClass]>; 391 392 // V7EM Processors. 393 def : ProcNoItin<"cortex-m4", [HasV7Ops, 394 FeatureThumb2, FeatureNoARM, FeatureDB, 395 FeatureHWDiv, FeatureDSPThumb2, 396 FeatureT2XtPk, FeatureVFP4, 397 FeatureVFPOnlySP, FeatureD16, 398 FeatureMClass]>; 399 400 // Swift uArch Processors. 401 def : ProcessorModel<"swift", SwiftModel, 402 [ProcSwift, HasV7Ops, FeatureNEON, 403 FeatureDB, FeatureDSPThumb2, 404 FeatureHasRAS, FeatureAClass]>; 405 406 // V8 Processors 407 def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass, 408 FeatureDB, FeatureFPARMv8, 409 FeatureNEON, FeatureDSPThumb2]>; 410 def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass, 411 FeatureDB, FeatureFPARMv8, 412 FeatureNEON, FeatureDSPThumb2]>; 413 414 // Cyclone is very similar to swift 415 def : ProcessorModel<"cyclone", SwiftModel, 416 [ProcSwift, HasV8Ops, HasV7Ops, 417 FeatureCrypto, FeatureFPARMv8, 418 FeatureDB,FeatureDSPThumb2, 419 FeatureHasRAS, FeatureZCZeroing]>; 420 421 //===----------------------------------------------------------------------===// 422 // Register File Description 423 //===----------------------------------------------------------------------===// 424 425 include "ARMRegisterInfo.td" 426 427 include "ARMCallingConv.td" 428 429 //===----------------------------------------------------------------------===// 430 // Instruction Descriptions 431 //===----------------------------------------------------------------------===// 432 433 include "ARMInstrInfo.td" 434 435 def ARMInstrInfo : InstrInfo; 436 437 //===----------------------------------------------------------------------===// 438 // Declare the target which we are implementing 439 //===----------------------------------------------------------------------===// 440 441 def ARM : Target { 442 // Pull in Instruction Info: 443 let InstructionSet = ARMInstrInfo; 444 } 445
