Home | History | Annotate | Download | only in Hexagon
      1 //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This is the top level entry point for the Hexagon target.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 //===----------------------------------------------------------------------===//
     15 // Target-independent interfaces which we are implementing
     16 //===----------------------------------------------------------------------===//
     17 
     18 include "llvm/Target/Target.td"
     19 
     20 //===----------------------------------------------------------------------===//
     21 // Hexagon Subtarget features.
     22 //===----------------------------------------------------------------------===//
     23 
     24 // Hexagon Archtectures
     25 def ArchV2       : SubtargetFeature<"v2", "HexagonArchVersion", "V2",
     26                                     "Hexagon v2">;
     27 def ArchV3       : SubtargetFeature<"v3", "HexagonArchVersion", "V3",
     28                                     "Hexagon v3">;
     29 def ArchV4       : SubtargetFeature<"v4", "HexagonArchVersion", "V4",
     30                                     "Hexagon v4">;
     31 def ArchV5       : SubtargetFeature<"v5", "HexagonArchVersion", "V5",
     32                                     "Hexagon v5">;
     33 
     34 //===----------------------------------------------------------------------===//
     35 // Hexagon Instruction Predicate Definitions.
     36 //===----------------------------------------------------------------------===//
     37 def HasV2T                      : Predicate<"Subtarget.hasV2TOps()">;
     38 def HasV2TOnly                  : Predicate<"Subtarget.hasV2TOpsOnly()">;
     39 def NoV2T                       : Predicate<"!Subtarget.hasV2TOps()">;
     40 def HasV3T                      : Predicate<"Subtarget.hasV3TOps()">;
     41 def HasV3TOnly                  : Predicate<"Subtarget.hasV3TOpsOnly()">;
     42 def NoV3T                       : Predicate<"!Subtarget.hasV3TOps()">;
     43 def HasV4T                      : Predicate<"Subtarget.hasV4TOps()">;
     44 def NoV4T                       : Predicate<"!Subtarget.hasV4TOps()">;
     45 def HasV5T                      : Predicate<"Subtarget.hasV5TOps()">;
     46 def NoV5T                       : Predicate<"!Subtarget.hasV5TOps()">;
     47 def UseMEMOP                    : Predicate<"Subtarget.useMemOps()">;
     48 def IEEERndNearV5T              : Predicate<"Subtarget.modeIEEERndNear()">;
     49 
     50 //===----------------------------------------------------------------------===//
     51 // Classes used for relation maps.
     52 //===----------------------------------------------------------------------===//
     53 // PredRel - Filter class used to relate non-predicated instructions with their
     54 // predicated forms.
     55 class PredRel;
     56 // PredNewRel - Filter class used to relate predicated instructions with their
     57 // predicate-new forms.
     58 class PredNewRel: PredRel;
     59 // ImmRegRel - Filter class used to relate instructions having reg-reg form
     60 // with their reg-imm counterparts.
     61 class ImmRegRel;
     62 // NewValueRel - Filter class used to relate regular store instructions with
     63 // their new-value store form.
     64 class NewValueRel: PredNewRel;
     65 // NewValueRel - Filter class used to relate load/store instructions having
     66 // different addressing modes with each other.
     67 class AddrModeRel: NewValueRel;
     68 
     69 //===----------------------------------------------------------------------===//
     70 // Generate mapping table to relate non-predicate instructions with their
     71 // predicated formats - true and false.
     72 //
     73 
     74 def getPredOpcode : InstrMapping {
     75   let FilterClass = "PredRel";
     76   // Instructions with the same BaseOpcode and isNVStore values form a row.
     77   let RowFields = ["BaseOpcode", "isNVStore", "PNewValue"];
     78   // Instructions with the same predicate sense form a column.
     79   let ColFields = ["PredSense"];
     80   // The key column is the unpredicated instructions.
     81   let KeyCol = [""];
     82   // Value columns are PredSense=true and PredSense=false
     83   let ValueCols = [["true"], ["false"]];
     84 }
     85 
     86 //===----------------------------------------------------------------------===//
     87 // Generate mapping table to relate predicate-true instructions with their
     88 // predicate-false forms
     89 //
     90 def getFalsePredOpcode : InstrMapping {
     91   let FilterClass = "PredRel";
     92   let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"];
     93   let ColFields = ["PredSense"];
     94   let KeyCol = ["true"];
     95   let ValueCols = [["false"]];
     96 }
     97 
     98 //===----------------------------------------------------------------------===//
     99 // Generate mapping table to relate predicate-false instructions with their
    100 // predicate-true forms
    101 //
    102 def getTruePredOpcode : InstrMapping {
    103   let FilterClass = "PredRel";
    104   let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"];
    105   let ColFields = ["PredSense"];
    106   let KeyCol = ["false"];
    107   let ValueCols = [["true"]];
    108 }
    109 
    110 //===----------------------------------------------------------------------===//
    111 // Generate mapping table to relate predicated instructions with their .new
    112 // format.
    113 //
    114 def getPredNewOpcode : InstrMapping {
    115   let FilterClass = "PredNewRel";
    116   let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
    117   let ColFields = ["PNewValue"];
    118   let KeyCol = [""];
    119   let ValueCols = [["new"]];
    120 }
    121 
    122 //===----------------------------------------------------------------------===//
    123 // Generate mapping table to relate .new predicated instructions with their old
    124 // format.
    125 //
    126 def getPredOldOpcode : InstrMapping {
    127   let FilterClass = "PredNewRel";
    128   let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
    129   let ColFields = ["PNewValue"];
    130   let KeyCol = ["new"];
    131   let ValueCols = [[""]];
    132 }
    133 
    134 //===----------------------------------------------------------------------===//
    135 // Generate mapping table to relate store instructions with their new-value
    136 // format.
    137 //
    138 def getNewValueOpcode : InstrMapping {
    139   let FilterClass = "NewValueRel";
    140   let RowFields = ["BaseOpcode", "PredSense", "PNewValue"];
    141   let ColFields = ["NValueST"];
    142   let KeyCol = ["false"];
    143   let ValueCols = [["true"]];
    144 }
    145 
    146 //===----------------------------------------------------------------------===//
    147 // Generate mapping table to relate new-value store instructions with their old
    148 // format.
    149 //
    150 def getNonNVStore : InstrMapping {
    151   let FilterClass = "NewValueRel";
    152   let RowFields = ["BaseOpcode", "PredSense", "PNewValue"];
    153   let ColFields = ["NValueST"];
    154   let KeyCol = ["true"];
    155   let ValueCols = [["false"]];
    156 }
    157 
    158 def getBasedWithImmOffset : InstrMapping {
    159   let FilterClass = "AddrModeRel";
    160   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
    161                    "isMEMri", "isFloat"];
    162   let ColFields = ["addrMode"];
    163   let KeyCol = ["Absolute"];
    164   let ValueCols = [["BaseImmOffset"]];
    165 }
    166 
    167 def getBaseWithRegOffset : InstrMapping {
    168   let FilterClass = "AddrModeRel";
    169   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
    170   let ColFields = ["addrMode"];
    171   let KeyCol = ["BaseImmOffset"];
    172   let ValueCols = [["BaseRegOffset"]];
    173 }
    174 
    175 def getRegForm : InstrMapping {
    176   let FilterClass = "ImmRegRel";
    177   let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
    178   let ColFields = ["InputType"];
    179   let KeyCol = ["imm"];
    180   let ValueCols = [["reg"]];
    181 }
    182 
    183 //===----------------------------------------------------------------------===//
    184 // Register File, Calling Conv, Instruction Descriptions
    185 //===----------------------------------------------------------------------===//
    186 include "HexagonSchedule.td"
    187 include "HexagonRegisterInfo.td"
    188 include "HexagonCallingConv.td"
    189 include "HexagonInstrInfo.td"
    190 include "HexagonIntrinsics.td"
    191 include "HexagonIntrinsicsDerived.td"
    192 
    193 def HexagonInstrInfo : InstrInfo;
    194 
    195 //===----------------------------------------------------------------------===//
    196 // Hexagon processors supported.
    197 //===----------------------------------------------------------------------===//
    198 
    199 class Proc<string Name, SchedMachineModel Model,
    200            list<SubtargetFeature> Features>
    201  : ProcessorModel<Name, Model, Features>;
    202 
    203 def : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>;
    204 def : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>;
    205 
    206 //===----------------------------------------------------------------------===//
    207 // Declare the target which we are implementing
    208 //===----------------------------------------------------------------------===//
    209 
    210 def Hexagon : Target {
    211   // Pull in Instruction Info:
    212   let InstructionSet = HexagonInstrInfo;
    213 }
    214