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      1 //=- HexagonIntrinsicsV3.td - Target Description for Hexagon -*- tablegen -*-=//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file describes the Hexagon V3 Compiler Intrinsics in TableGen format.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 
     15 
     16 
     17 // MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
     18 def Hexagon_M2_vrcmpys_s1:
     19   di_MInst_disi_s1_sat            <"vrcmpys",  int_hexagon_M2_vrcmpys_s1>;
     20 def Hexagon_M2_vrcmpys_acc_s1:
     21   di_MInst_didisi_acc_s1_sat      <"vrcmpys",  int_hexagon_M2_vrcmpys_acc_s1>;
     22 def Hexagon_M2_vrcmpys_s1rp:
     23   si_MInst_disi_s1_rnd_sat        <"vrcmpys",  int_hexagon_M2_vrcmpys_s1rp>;
     24 
     25 
     26 
     27 
     28 /********************************************************************
     29 *            MTYPE/VB                                               *
     30 *********************************************************************/
     31 
     32 // MTYPE / VB / Vector reduce add unsigned bytes.
     33 def Hexagon_M2_vradduh:
     34   si_MInst_didi                   <"vradduh",  int_hexagon_M2_vradduh>;
     35 
     36 
     37 /********************************************************************
     38 *            ALU64/ALU                                              *
     39 *********************************************************************/
     40 
     41 // ALU64 / ALU / Add.
     42 def Hexagon_A2_addsp:
     43   di_ALU64_sidi                   <"add",      int_hexagon_A2_addsp>;
     44 def Hexagon_A2_addpsat:
     45   di_ALU64_didi                   <"add",      int_hexagon_A2_addpsat>;
     46 
     47 def Hexagon_A2_maxp:
     48   di_ALU64_didi                   <"max",      int_hexagon_A2_maxp>;
     49 def Hexagon_A2_maxup:
     50   di_ALU64_didi                   <"maxu",     int_hexagon_A2_maxup>;
     51