1 //===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Declarations that describe the Hexagon register file. 12 //===----------------------------------------------------------------------===// 13 14 let Namespace = "Hexagon" in { 15 16 class HexagonReg<string n> : Register<n> { 17 field bits<5> Num; 18 } 19 20 class HexagonDoubleReg<string n, list<Register> subregs> : 21 RegisterWithSubRegs<n, subregs> { 22 field bits<5> Num; 23 } 24 25 // Registers are identified with 5-bit ID numbers. 26 // Ri - 32-bit integer registers. 27 class Ri<bits<5> num, string n> : HexagonReg<n> { 28 let Num = num; 29 } 30 31 // Rf - 32-bit floating-point registers. 32 class Rf<bits<5> num, string n> : HexagonReg<n> { 33 let Num = num; 34 } 35 36 37 // Rd - 64-bit registers. 38 class Rd<bits<5> num, string n, list<Register> subregs> : 39 HexagonDoubleReg<n, subregs> { 40 let Num = num; 41 let SubRegs = subregs; 42 } 43 44 // Rp - predicate registers 45 class Rp<bits<5> num, string n> : HexagonReg<n> { 46 let Num = num; 47 } 48 49 // Rc - control registers 50 class Rc<bits<5> num, string n> : HexagonReg<n> { 51 let Num = num; 52 } 53 54 // Rj - aliased integer registers 55 class Rj<string n, Ri R>: HexagonReg<n> { 56 let Num = R.Num; 57 let Aliases = [R]; 58 } 59 60 def subreg_loreg : SubRegIndex<32>; 61 def subreg_hireg : SubRegIndex<32, 32>; 62 63 // Integer registers. 64 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>; 65 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>; 66 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; 67 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; 68 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>; 69 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>; 70 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>; 71 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>; 72 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>; 73 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>; 74 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>; 75 def R11 : Ri<11, "r11">, DwarfRegNum<[11]>; 76 def R12 : Ri<12, "r12">, DwarfRegNum<[12]>; 77 def R13 : Ri<13, "r13">, DwarfRegNum<[13]>; 78 def R14 : Ri<14, "r14">, DwarfRegNum<[14]>; 79 def R15 : Ri<15, "r15">, DwarfRegNum<[15]>; 80 def R16 : Ri<16, "r16">, DwarfRegNum<[16]>; 81 def R17 : Ri<17, "r17">, DwarfRegNum<[17]>; 82 def R18 : Ri<18, "r18">, DwarfRegNum<[18]>; 83 def R19 : Ri<19, "r19">, DwarfRegNum<[19]>; 84 def R20 : Ri<20, "r20">, DwarfRegNum<[20]>; 85 def R21 : Ri<21, "r21">, DwarfRegNum<[21]>; 86 def R22 : Ri<22, "r22">, DwarfRegNum<[22]>; 87 def R23 : Ri<23, "r23">, DwarfRegNum<[23]>; 88 def R24 : Ri<24, "r24">, DwarfRegNum<[24]>; 89 def R25 : Ri<25, "r25">, DwarfRegNum<[25]>; 90 def R26 : Ri<26, "r26">, DwarfRegNum<[26]>; 91 def R27 : Ri<27, "r27">, DwarfRegNum<[27]>; 92 def R28 : Ri<28, "r28">, DwarfRegNum<[28]>; 93 def R29 : Ri<29, "r29">, DwarfRegNum<[29]>; 94 def R30 : Ri<30, "r30">, DwarfRegNum<[30]>; 95 def R31 : Ri<31, "r31">, DwarfRegNum<[31]>; 96 97 def SP : Rj<"sp", R29>, DwarfRegNum<[29]>; 98 def FP : Rj<"fp", R30>, DwarfRegNum<[30]>; 99 def LR : Rj<"lr", R31>, DwarfRegNum<[31]>; 100 101 // Aliases of the R* registers used to hold 64-bit int values (doubles). 102 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in { 103 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; 104 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; 105 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; 106 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>; 107 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>; 108 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>; 109 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>; 110 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>; 111 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>; 112 def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>; 113 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>; 114 def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>; 115 def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>; 116 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>; 117 def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>; 118 def D15 : Rd<30, "r31:30", [R30, R31]>, DwarfRegNum<[62]>; 119 } 120 121 // Predicate registers. 122 def P0 : Rp<0, "p0">, DwarfRegNum<[63]>; 123 def P1 : Rp<1, "p1">, DwarfRegNum<[64]>; 124 def P2 : Rp<2, "p2">, DwarfRegNum<[65]>; 125 def P3 : Rp<3, "p3">, DwarfRegNum<[66]>; 126 127 // Control registers. 128 def SA0 : Rc<0, "sa0">, DwarfRegNum<[67]>; 129 def LC0 : Rc<1, "lc0">, DwarfRegNum<[68]>; 130 131 def SA1 : Rc<2, "sa1">, DwarfRegNum<[69]>; 132 def LC1 : Rc<3, "lc1">, DwarfRegNum<[70]>; 133 134 def M0 : Rc<6, "m0">, DwarfRegNum<[71]>; 135 def M1 : Rc<7, "m1">, DwarfRegNum<[72]>; 136 137 def PC : Rc<9, "pc">, DwarfRegNum<[32]>; // is the Dwarf number correct? 138 def GP : Rc<11, "gp">, DwarfRegNum<[33]>; // is the Dwarf number correct? 139 } 140 141 // Register classes. 142 // 143 // FIXME: the register order should be defined in terms of the preferred 144 // allocation order... 145 // 146 def IntRegs : RegisterClass<"Hexagon", [i32,f32], 32, 147 (add (sequence "R%u", 0, 9), 148 (sequence "R%u", 12, 28), 149 R10, R11, R29, R30, R31)> { 150 } 151 152 def DoubleRegs : RegisterClass<"Hexagon", [i64,f64], 64, 153 (add (sequence "D%u", 0, 4), 154 (sequence "D%u", 6, 13), D5, D14, D15)>; 155 156 157 def PredRegs : RegisterClass<"Hexagon", [i1], 32, (add (sequence "P%u", 0, 3))> 158 { 159 let Size = 32; 160 } 161 162 def CRRegs : RegisterClass<"Hexagon", [i32], 32, 163 (add (sequence "LC%u", 0, 1), 164 (sequence "SA%u", 0, 1), 165 (sequence "M%u", 0, 1), PC, GP)> { 166 let Size = 32; 167 } 168
