1 //===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Declarations that describe the MIPS register file 12 //===----------------------------------------------------------------------===// 13 let Namespace = "Mips" in { 14 def sub_32 : SubRegIndex<32>; 15 def sub_64 : SubRegIndex<64>; 16 def sub_lo : SubRegIndex<32>; 17 def sub_hi : SubRegIndex<32, 32>; 18 def sub_dsp16_19 : SubRegIndex<4, 16>; 19 def sub_dsp20 : SubRegIndex<1, 20>; 20 def sub_dsp21 : SubRegIndex<1, 21>; 21 def sub_dsp22 : SubRegIndex<1, 22>; 22 def sub_dsp23 : SubRegIndex<1, 23>; 23 } 24 25 class Unallocatable { 26 bit isAllocatable = 0; 27 } 28 29 // We have banks of 32 registers each. 30 class MipsReg<bits<16> Enc, string n> : Register<n> { 31 let HWEncoding = Enc; 32 let Namespace = "Mips"; 33 } 34 35 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> 36 : RegisterWithSubRegs<n, subregs> { 37 let HWEncoding = Enc; 38 let Namespace = "Mips"; 39 } 40 41 // Mips CPU Registers 42 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; 43 44 // Mips 64-bit CPU Registers 45 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> 46 : MipsRegWithSubRegs<Enc, n, subregs> { 47 let SubRegIndices = [sub_32]; 48 } 49 50 // Mips 32-bit FPU Registers 51 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 52 53 // Mips 64-bit (aliased) FPU Registers 54 class AFPR<bits<16> Enc, string n, list<Register> subregs> 55 : MipsRegWithSubRegs<Enc, n, subregs> { 56 let SubRegIndices = [sub_lo, sub_hi]; 57 let CoveredBySubRegs = 1; 58 } 59 60 class AFPR64<bits<16> Enc, string n, list<Register> subregs> 61 : MipsRegWithSubRegs<Enc, n, subregs> { 62 let SubRegIndices = [sub_lo, sub_hi]; 63 let CoveredBySubRegs = 1; 64 } 65 66 // Mips 128-bit (aliased) MSA Registers 67 class AFPR128<bits<16> Enc, string n, list<Register> subregs> 68 : MipsRegWithSubRegs<Enc, n, subregs> { 69 let SubRegIndices = [sub_64]; 70 } 71 72 // Accumulator Registers 73 class ACCReg<bits<16> Enc, string n, list<Register> subregs> 74 : MipsRegWithSubRegs<Enc, n, subregs> { 75 let SubRegIndices = [sub_lo, sub_hi]; 76 let CoveredBySubRegs = 1; 77 } 78 79 // Mips Hardware Registers 80 class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; 81 82 //===----------------------------------------------------------------------===// 83 // Registers 84 //===----------------------------------------------------------------------===// 85 86 let Namespace = "Mips" in { 87 // General Purpose Registers 88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 89 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 91 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 92 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 93 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 94 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 95 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 96 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 97 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 98 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 99 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 100 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 101 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 102 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 103 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 104 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 105 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 106 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 107 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 108 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 109 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 110 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 111 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 112 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 113 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 114 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 115 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 116 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 117 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 118 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 119 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 120 121 // General Purpose 64-bit Registers 122 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 123 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 124 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 125 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 126 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 127 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 128 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 129 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 130 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 131 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 132 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 133 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 134 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 135 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 136 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 137 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 138 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 139 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 140 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 141 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 142 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 143 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 144 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 145 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 146 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 147 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 148 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 149 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 150 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 151 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 152 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 153 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 154 155 /// Mips Single point precision FPU Registers 156 foreach I = 0-31 in 157 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 158 159 // Higher half of 64-bit FP registers. 160 foreach I = 0-31 in 161 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 162 163 /// Mips Double point precision FPU Registers (aliased 164 /// with the single precision to hold 64 bit values) 165 foreach I = 0-15 in 166 def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1), 167 [!cast<FPR>("F"#!shl(I, 1)), 168 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>; 169 170 /// Mips Double point precision FPU Registers in MFP64 mode. 171 foreach I = 0-31 in 172 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>, 173 DwarfRegNum<[!add(I, 32)]>; 174 175 /// Mips MSA registers 176 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers 177 foreach I = 0-31 in 178 def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>, 179 DwarfRegNum<[!add(I, 32)]>; 180 181 // Hi/Lo registers 182 def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>; 183 def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>; 184 def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>; 185 def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>; 186 def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>; 187 def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>; 188 def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>; 189 def LO3 : MipsReg<3, "ac3">, DwarfRegNum<[181]>; 190 191 let SubRegIndices = [sub_32] in { 192 def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>; 193 def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>; 194 } 195 196 // FP control registers. 197 foreach I = 0-31 in 198 def FCR#I : MipsReg<#I, ""#I>; 199 200 // FP condition code registers. 201 foreach I = 0-7 in 202 def FCC#I : MipsReg<#I, "fcc"#I>; 203 204 // COP2 registers. 205 foreach I = 0-31 in 206 def COP2#I : MipsReg<#I, ""#I>; 207 208 // COP3 registers. 209 foreach I = 0-31 in 210 def COP3#I : MipsReg<#I, ""#I>; 211 212 // PC register 213 def PC : Register<"pc">; 214 215 // Hardware register $29 216 foreach I = 0-31 in 217 def HWR#I : MipsReg<#I, ""#I>; 218 219 // Accum registers 220 foreach I = 0-3 in 221 def AC#I : ACCReg<#I, "ac"#I, 222 [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>; 223 224 def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>; 225 226 // DSP-ASE control register fields. 227 def DSPPos : Register<"">; 228 def DSPSCount : Register<"">; 229 def DSPCarry : Register<"">; 230 def DSPEFI : Register<"">; 231 def DSPOutFlag16_19 : Register<"">; 232 def DSPOutFlag20 : Register<"">; 233 def DSPOutFlag21 : Register<"">; 234 def DSPOutFlag22 : Register<"">; 235 def DSPOutFlag23 : Register<"">; 236 def DSPCCond : Register<"">; 237 238 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22, 239 sub_dsp23] in 240 def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, 241 DSPOutFlag21, DSPOutFlag22, 242 DSPOutFlag23]>; 243 244 // MSA-ASE control registers. 245 def MSAIR : MipsReg<0, "0">; 246 def MSACSR : MipsReg<1, "1">; 247 def MSAAccess : MipsReg<2, "2">; 248 def MSASave : MipsReg<3, "3">; 249 def MSAModify : MipsReg<4, "4">; 250 def MSARequest : MipsReg<5, "5">; 251 def MSAMap : MipsReg<6, "6">; 252 def MSAUnmap : MipsReg<7, "7">; 253 254 // Octeon multiplier and product registers 255 def MPL0 : MipsReg<0, "mpl0">; 256 def MPL1 : MipsReg<1, "mpl1">; 257 def MPL2 : MipsReg<2, "mpl2">; 258 def P0 : MipsReg<0, "p0">; 259 def P1 : MipsReg<1, "p1">; 260 def P2 : MipsReg<2, "p2">; 261 262 } 263 264 //===----------------------------------------------------------------------===// 265 // Register Classes 266 //===----------------------------------------------------------------------===// 267 268 class GPR32Class<list<ValueType> regTypes> : 269 RegisterClass<"Mips", regTypes, 32, (add 270 // Reserved 271 ZERO, AT, 272 // Return Values and Arguments 273 V0, V1, A0, A1, A2, A3, 274 // Not preserved across procedure calls 275 T0, T1, T2, T3, T4, T5, T6, T7, 276 // Callee save 277 S0, S1, S2, S3, S4, S5, S6, S7, 278 // Not preserved across procedure calls 279 T8, T9, 280 // Reserved 281 K0, K1, GP, SP, FP, RA)>; 282 283 def GPR32 : GPR32Class<[i32]>; 284 def DSPR : GPR32Class<[v4i8, v2i16]>; 285 286 def GPR64 : RegisterClass<"Mips", [i64], 64, (add 287 // Reserved 288 ZERO_64, AT_64, 289 // Return Values and Arguments 290 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 291 // Not preserved across procedure calls 292 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 293 // Callee save 294 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 295 // Not preserved across procedure calls 296 T8_64, T9_64, 297 // Reserved 298 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 299 300 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 301 // Return Values and Arguments 302 V0, V1, A0, A1, A2, A3, 303 // Callee save 304 S0, S1)>; 305 306 def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add 307 // Return Values and Arguments 308 V0, V1, A0, A1, A2, A3, 309 // Callee save 310 S0, S1, 311 SP)>; 312 313 def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; 314 315 def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 316 317 // 64bit fp: 318 // * FGR64 - 32 64-bit registers 319 // * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 320 // 321 // 32bit fp: 322 // * FGR32 - 16 32-bit even registers 323 // * FGR32 - 32 32-bit registers (single float only mode) 324 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 325 326 def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>, 327 Unallocatable; 328 329 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 330 // Return Values and Arguments 331 D0, D1, 332 // Not preserved across procedure calls 333 D2, D3, D4, D5, 334 // Return Values and Arguments 335 D6, D7, 336 // Not preserved across procedure calls 337 D8, D9, 338 // Callee save 339 D10, D11, D12, D13, D14, D15)>; 340 341 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 342 343 // Used to reserve odd registers when given -mattr=+nooddspreg 344 def OddSP : RegisterClass<"Mips", [f32], 32, 345 (add (decimate (sequence "F%u", 1, 31), 2), 346 (decimate (sequence "F_HI%u", 1, 31), 2))>, 347 Unallocatable; 348 349 // FP control registers. 350 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, 351 Unallocatable; 352 353 // FP condition code registers. 354 def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, 355 Unallocatable; 356 357 // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers. 358 // This class allows us to represent this in codegen patterns. 359 def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>; 360 361 def MSA128B: RegisterClass<"Mips", [v16i8], 128, 362 (sequence "W%u", 0, 31)>; 363 def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128, 364 (sequence "W%u", 0, 31)>; 365 def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128, 366 (sequence "W%u", 0, 31)>; 367 def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128, 368 (sequence "W%u", 0, 31)>; 369 370 def MSACtrl: RegisterClass<"Mips", [i32], 32, (add 371 MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>; 372 373 // Hi/Lo Registers 374 def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; 375 def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>; 376 def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>; 377 def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>; 378 def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>; 379 def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>; 380 381 // Hardware registers 382 def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>, 383 Unallocatable; 384 385 // Accumulator Registers 386 def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> { 387 let Size = 64; 388 } 389 390 def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { 391 let Size = 128; 392 } 393 394 def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { 395 let Size = 64; 396 } 397 398 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; 399 400 // Coprocessor 2 registers. 401 def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>, 402 Unallocatable; 403 404 // Coprocessor 3 registers. 405 def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>, 406 Unallocatable; 407 408 // Octeon multiplier and product registers 409 def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>, 410 Unallocatable; 411 def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>, 412 Unallocatable; 413 414 // Register Operands. 415 416 class MipsAsmRegOperand : AsmOperandClass { 417 let ParserMethod = "ParseAnyRegister"; 418 } 419 420 def GPR64AsmOperand : MipsAsmRegOperand { 421 let Name = "GPR64AsmReg"; 422 let PredicateMethod = "isGPRAsmReg"; 423 } 424 425 def GPR32AsmOperand : MipsAsmRegOperand { 426 let Name = "GPR32AsmReg"; 427 let PredicateMethod = "isGPRAsmReg"; 428 } 429 430 def ACC64DSPAsmOperand : MipsAsmRegOperand { 431 let Name = "ACC64DSPAsmReg"; 432 let PredicateMethod = "isACCAsmReg"; 433 } 434 435 def HI32DSPAsmOperand : MipsAsmRegOperand { 436 let Name = "HI32DSPAsmReg"; 437 let PredicateMethod = "isACCAsmReg"; 438 } 439 440 def LO32DSPAsmOperand : MipsAsmRegOperand { 441 let Name = "LO32DSPAsmReg"; 442 let PredicateMethod = "isACCAsmReg"; 443 } 444 445 def CCRAsmOperand : MipsAsmRegOperand { 446 let Name = "CCRAsmReg"; 447 } 448 449 def AFGR64AsmOperand : MipsAsmRegOperand { 450 let Name = "AFGR64AsmReg"; 451 let PredicateMethod = "isFGRAsmReg"; 452 } 453 454 def FGR64AsmOperand : MipsAsmRegOperand { 455 let Name = "FGR64AsmReg"; 456 let PredicateMethod = "isFGRAsmReg"; 457 } 458 459 def FGR32AsmOperand : MipsAsmRegOperand { 460 let Name = "FGR32AsmReg"; 461 let PredicateMethod = "isFGRAsmReg"; 462 } 463 464 def FGRH32AsmOperand : MipsAsmRegOperand { 465 let Name = "FGRH32AsmReg"; 466 let PredicateMethod = "isFGRAsmReg"; 467 } 468 469 def FCCRegsAsmOperand : MipsAsmRegOperand { 470 let Name = "FCCAsmReg"; 471 } 472 473 def MSA128AsmOperand : MipsAsmRegOperand { 474 let Name = "MSA128AsmReg"; 475 } 476 477 def MSACtrlAsmOperand : MipsAsmRegOperand { 478 let Name = "MSACtrlAsmReg"; 479 } 480 481 def GPR32Opnd : RegisterOperand<GPR32> { 482 let ParserMatchClass = GPR32AsmOperand; 483 } 484 485 def GPR64Opnd : RegisterOperand<GPR64> { 486 let ParserMatchClass = GPR64AsmOperand; 487 } 488 489 def DSPROpnd : RegisterOperand<DSPR> { 490 let ParserMatchClass = GPR32AsmOperand; 491 } 492 493 def CCROpnd : RegisterOperand<CCR> { 494 let ParserMatchClass = CCRAsmOperand; 495 } 496 497 def HWRegsAsmOperand : MipsAsmRegOperand { 498 let Name = "HWRegsAsmReg"; 499 } 500 501 def COP2AsmOperand : MipsAsmRegOperand { 502 let Name = "COP2AsmReg"; 503 } 504 505 def COP3AsmOperand : MipsAsmRegOperand { 506 let Name = "COP3AsmReg"; 507 } 508 509 def HWRegsOpnd : RegisterOperand<HWRegs> { 510 let ParserMatchClass = HWRegsAsmOperand; 511 } 512 513 def AFGR64Opnd : RegisterOperand<AFGR64> { 514 let ParserMatchClass = AFGR64AsmOperand; 515 } 516 517 def FGR64Opnd : RegisterOperand<FGR64> { 518 let ParserMatchClass = FGR64AsmOperand; 519 } 520 521 def FGR32Opnd : RegisterOperand<FGR32> { 522 let ParserMatchClass = FGR32AsmOperand; 523 } 524 525 def FGRCCOpnd : RegisterOperand<FGRCC> { 526 // The assembler doesn't use register classes so we can re-use 527 // FGR32AsmOperand. 528 let ParserMatchClass = FGR32AsmOperand; 529 } 530 531 def FGRH32Opnd : RegisterOperand<FGRH32> { 532 let ParserMatchClass = FGRH32AsmOperand; 533 } 534 535 def FCCRegsOpnd : RegisterOperand<FCC> { 536 let ParserMatchClass = FCCRegsAsmOperand; 537 } 538 539 def LO32DSPOpnd : RegisterOperand<LO32DSP> { 540 let ParserMatchClass = LO32DSPAsmOperand; 541 } 542 543 def HI32DSPOpnd : RegisterOperand<HI32DSP> { 544 let ParserMatchClass = HI32DSPAsmOperand; 545 } 546 547 def ACC64DSPOpnd : RegisterOperand<ACC64DSP> { 548 let ParserMatchClass = ACC64DSPAsmOperand; 549 } 550 551 def COP2Opnd : RegisterOperand<COP2> { 552 let ParserMatchClass = COP2AsmOperand; 553 } 554 555 def COP3Opnd : RegisterOperand<COP3> { 556 let ParserMatchClass = COP3AsmOperand; 557 } 558 559 def MSA128BOpnd : RegisterOperand<MSA128B> { 560 let ParserMatchClass = MSA128AsmOperand; 561 } 562 563 def MSA128HOpnd : RegisterOperand<MSA128H> { 564 let ParserMatchClass = MSA128AsmOperand; 565 } 566 567 def MSA128WOpnd : RegisterOperand<MSA128W> { 568 let ParserMatchClass = MSA128AsmOperand; 569 } 570 571 def MSA128DOpnd : RegisterOperand<MSA128D> { 572 let ParserMatchClass = MSA128AsmOperand; 573 } 574 575 def MSA128CROpnd : RegisterOperand<MSACtrl> { 576 let ParserMatchClass = MSACtrlAsmOperand; 577 } 578 579
