1 //===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the itinerary class data for the Freescale e500mc 32-bit 11 // Power processor. 12 // 13 // All information is derived from the "e500mc Core Reference Manual", 14 // Freescale Document Number E500MCRM, Rev. 1, 03/2012. 15 // 16 //===----------------------------------------------------------------------===// 17 // Relevant functional units in the Freescale e500mc core: 18 // 19 // * Decode & Dispatch 20 // Can dispatch up to 2 instructions per clock cycle to either the GPR Issue 21 // queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ). 22 def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1 23 def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2 24 25 // * Execute 26 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX. 27 // Some instructions can only execute in SFX0 but not SFX1. 28 // The CFX has a bypass path, allowing non-divide instructions to execute 29 // while a divide instruction is executed. 30 def E500_SFX0 : FuncUnit; // Simple unit 0 31 def E500_SFX1 : FuncUnit; // Simple unit 1 32 def E500_BU : FuncUnit; // Branch unit 33 def E500_CFX_DivBypass 34 : FuncUnit; // CFX divide bypass path 35 def E500_CFX_0 : FuncUnit; // CFX pipeline 36 def E500_LSU_0 : FuncUnit; // LSU pipeline 37 def E500_FPU_0 : FuncUnit; // FPU pipeline 38 39 def E500_GPR_Bypass : Bypass; 40 def E500_FPR_Bypass : Bypass; 41 def E500_CR_Bypass : Bypass; 42 43 def PPCE500mcItineraries : ProcessorItineraries< 44 [E500_DIS0, E500_DIS1, E500_SFX0, E500_SFX1, E500_BU, E500_CFX_DivBypass, 45 E500_CFX_0, E500_LSU_0, E500_FPU_0], 46 [E500_CR_Bypass, E500_GPR_Bypass, E500_FPR_Bypass], [ 47 InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 48 InstrStage<1, [E500_SFX0, E500_SFX1]>], 49 [4, 1, 1], // Latency = 1 50 [E500_GPR_Bypass, 51 E500_GPR_Bypass, E500_GPR_Bypass]>, 52 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 53 InstrStage<1, [E500_SFX0, E500_SFX1]>], 54 [4, 1, 1], // Latency = 1 55 [E500_GPR_Bypass, 56 E500_GPR_Bypass, E500_GPR_Bypass]>, 57 InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 58 InstrStage<1, [E500_SFX0, E500_SFX1]>], 59 [5, 1, 1], // Latency = 1 or 2 60 [E500_CR_Bypass, 61 E500_GPR_Bypass, E500_GPR_Bypass]>, 62 InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 63 InstrStage<1, [E500_CFX_0], 0>, 64 InstrStage<14, [E500_CFX_DivBypass]>], 65 [17, 1, 1], // Latency=4..35, Repeat= 4..35 66 [E500_GPR_Bypass, 67 E500_GPR_Bypass, E500_GPR_Bypass]>, 68 InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 69 InstrStage<8, [E500_FPU_0]>], 70 [11], // Latency = 8 71 [E500_FPR_Bypass]>, 72 InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 73 InstrStage<8, [E500_FPU_0]>], 74 [11, 1, 1], // Latency = 8 75 [NoBypass, NoBypass, NoBypass]>, 76 InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 77 InstrStage<1, [E500_CFX_0]>], 78 [7, 1, 1], // Latency = 4, Repeat rate = 1 79 [E500_GPR_Bypass, 80 E500_GPR_Bypass, E500_GPR_Bypass]>, 81 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 82 InstrStage<1, [E500_CFX_0]>], 83 [7, 1, 1], // Latency = 4, Repeat rate = 1 84 [E500_GPR_Bypass, 85 E500_GPR_Bypass, E500_GPR_Bypass]>, 86 InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 87 InstrStage<1, [E500_CFX_0]>], 88 [7, 1, 1], // Latency = 4, Repeat rate = 1 89 [E500_GPR_Bypass, 90 E500_GPR_Bypass, E500_GPR_Bypass]>, 91 InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 92 InstrStage<1, [E500_SFX0, E500_SFX1]>], 93 [4, 1, 1], // Latency = 1 94 [E500_GPR_Bypass, 95 E500_GPR_Bypass, E500_GPR_Bypass]>, 96 InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 97 InstrStage<1, [E500_SFX0, E500_SFX1]>], 98 [4, 1, 1], // Latency = 1 99 [E500_GPR_Bypass, 100 E500_GPR_Bypass, E500_GPR_Bypass]>, 101 InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 102 InstrStage<2, [E500_SFX0]>], 103 [5, 1], // Latency = 2, Repeat rate = 2 104 [E500_GPR_Bypass, E500_GPR_Bypass]>, 105 InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 106 InstrStage<1, [E500_BU]>], 107 [4, 1], // Latency = 1 108 [NoBypass, E500_GPR_Bypass]>, 109 InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 110 InstrStage<1, [E500_BU]>], 111 [4, 1, 1], // Latency = 1 112 [E500_CR_Bypass, 113 E500_CR_Bypass, E500_CR_Bypass]>, 114 InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 115 InstrStage<1, [E500_BU]>], 116 [4, 1], // Latency = 1 117 [E500_CR_Bypass, E500_CR_Bypass]>, 118 InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 119 InstrStage<1, [E500_SFX0, E500_SFX1]>], 120 [4, 1, 1], // Latency = 1 121 [E500_CR_Bypass, E500_GPR_Bypass]>, 122 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 123 InstrStage<1, [E500_LSU_0]>], 124 [6, 1], // Latency = 3, Repeat rate = 1 125 [E500_GPR_Bypass, E500_GPR_Bypass]>, 126 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 127 InstrStage<1, [E500_LSU_0]>], 128 [6, 1], // Latency = 3 129 [E500_GPR_Bypass, E500_GPR_Bypass]>, 130 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 131 InstrStage<1, [E500_LSU_0]>], 132 [6, 1], // Latency = 3 133 [E500_GPR_Bypass, E500_GPR_Bypass]>, 134 InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 135 InstrStage<1, [E500_LSU_0]>], 136 [6, 1], // Latency = 3 137 [E500_GPR_Bypass, E500_GPR_Bypass]>, 138 InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 139 InstrStage<1, [E500_SFX0, E500_SFX1], 0>, 140 InstrStage<1, [E500_LSU_0]>], 141 [6, 1], // Latency = 3 142 [E500_GPR_Bypass, E500_GPR_Bypass], 143 2>, // 2 micro-ops 144 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 145 InstrStage<1, [E500_SFX0, E500_SFX1], 0>, 146 InstrStage<1, [E500_LSU_0]>], 147 [6, 1], // Latency = 3 148 [E500_GPR_Bypass, E500_GPR_Bypass], 149 2>, // 2 micro-ops 150 InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 151 InstrStage<1, [E500_LSU_0]>], 152 [6, 1], // Latency = 3 153 [NoBypass, E500_GPR_Bypass]>, 154 InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 155 InstrStage<1, [E500_SFX0, E500_SFX1], 0>, 156 InstrStage<1, [E500_LSU_0]>], 157 [6, 1], // Latency = 3 158 [NoBypass, E500_GPR_Bypass], 159 2>, // 2 micro-ops 160 InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 161 InstrStage<1, [E500_LSU_0]>], 162 [6, 1], // Latency = 3 163 [NoBypass, E500_GPR_Bypass]>, 164 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 165 InstrStage<1, [E500_LSU_0]>], 166 [6, 1, 1], // Latency = 3 167 [E500_GPR_Bypass, 168 E500_GPR_Bypass, E500_GPR_Bypass]>, 169 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 170 InstrStage<1, [E500_SFX0, E500_SFX1], 0>, 171 InstrStage<1, [E500_LSU_0]>], 172 [6, 1, 1], // Latency = 3 173 [E500_GPR_Bypass, 174 E500_GPR_Bypass, E500_GPR_Bypass], 175 2>, // 2 micro-ops 176 InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 177 InstrStage<1, [E500_LSU_0]>], 178 [7, 1, 1], // Latency = 4 179 [E500_FPR_Bypass, 180 E500_GPR_Bypass, E500_GPR_Bypass]>, 181 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 182 InstrStage<1, [E500_SFX0, E500_SFX1], 0>, 183 InstrStage<1, [E500_LSU_0]>], 184 [7, 1, 1], // Latency = 4 185 [E500_FPR_Bypass, 186 E500_GPR_Bypass, E500_GPR_Bypass], 187 2>, // 2 micro-ops 188 InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 189 InstrStage<1, [E500_SFX0, E500_SFX1], 0>, 190 InstrStage<1, [E500_LSU_0]>], 191 [7, 1, 1], // Latency = 4 192 [E500_FPR_Bypass, 193 E500_GPR_Bypass, E500_GPR_Bypass], 194 2>, // 2 micro-ops 195 InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 196 InstrStage<1, [E500_LSU_0]>], 197 [6, 1], // Latency = 3 198 [E500_GPR_Bypass, E500_GPR_Bypass]>, 199 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 200 InstrStage<1, [E500_SFX0, E500_SFX1], 0>, 201 InstrStage<1, [E500_LSU_0]>], 202 [6, 1], // Latency = 3 203 [E500_GPR_Bypass, E500_GPR_Bypass]>, 204 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 205 InstrStage<1, [E500_SFX0, E500_SFX1], 0>, 206 InstrStage<1, [E500_LSU_0]>], 207 [6, 1], // Latency = 3 208 [E500_GPR_Bypass, E500_GPR_Bypass]>, 209 InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 210 InstrStage<1, [E500_LSU_0]>], 211 [7, 1], // Latency = r+3 212 [NoBypass, E500_GPR_Bypass]>, 213 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 214 InstrStage<3, [E500_LSU_0]>], 215 [6, 1, 1], // Latency = 3, Repeat rate = 3 216 [E500_GPR_Bypass, 217 E500_GPR_Bypass, E500_GPR_Bypass]>, 218 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 219 InstrStage<1, [E500_LSU_0]>], 220 [6, 1], // Latency = 3 221 [NoBypass, E500_GPR_Bypass]>, 222 InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 223 InstrStage<1, [E500_LSU_0]>]>, 224 InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 225 InstrStage<4, [E500_SFX0]>], 226 [7, 1], 227 [E500_GPR_Bypass, E500_GPR_Bypass]>, 228 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 229 InstrStage<2, [E500_SFX0, E500_SFX1]>], 230 [5, 1], // Latency = 2, Repeat rate = 4 231 [E500_GPR_Bypass, E500_GPR_Bypass]>, 232 InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 233 InstrStage<1, [E500_SFX0]>], 234 [5, 1], 235 [NoBypass, E500_GPR_Bypass]>, 236 InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 237 InstrStage<1, [E500_LSU_0], 0>]>, 238 InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 239 InstrStage<5, [E500_SFX0]>], 240 [8, 1], 241 [E500_GPR_Bypass, E500_CR_Bypass]>, 242 InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 243 InstrStage<5, [E500_SFX0]>], 244 [8, 1], 245 [E500_GPR_Bypass, E500_CR_Bypass]>, 246 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 247 InstrStage<4, [E500_SFX0]>], 248 [7, 1], // Latency = 4, Repeat rate = 4 249 [E500_GPR_Bypass, E500_GPR_Bypass]>, 250 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 251 InstrStage<1, [E500_SFX0, E500_SFX1]>], 252 [4, 1], // Latency = 1, Repeat rate = 1 253 [E500_GPR_Bypass, E500_CR_Bypass]>, 254 InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 255 InstrStage<4, [E500_SFX0]>], 256 [7, 1], // Latency = 4, Repeat rate = 4 257 [NoBypass, E500_GPR_Bypass]>, 258 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 259 InstrStage<1, [E500_SFX0, E500_SFX1]>], 260 [4, 1], // Latency = 1, Repeat rate = 1 261 [E500_CR_Bypass, E500_GPR_Bypass]>, 262 InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 263 InstrStage<1, [E500_SFX0]>], 264 [4, 1], 265 [NoBypass, E500_GPR_Bypass]>, 266 InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 267 InstrStage<2, [E500_FPU_0]>], 268 [11, 1, 1], // Latency = 8, Repeat rate = 2 269 [E500_FPR_Bypass, 270 E500_FPR_Bypass, E500_FPR_Bypass]>, 271 InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 272 InstrStage<4, [E500_FPU_0]>], 273 [13, 1, 1], // Latency = 10, Repeat rate = 4 274 [E500_FPR_Bypass, 275 E500_FPR_Bypass, E500_FPR_Bypass]>, 276 InstrItinData<IIC_FPCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 277 InstrStage<2, [E500_FPU_0]>], 278 [11, 1, 1], // Latency = 8, Repeat rate = 2 279 [E500_CR_Bypass, 280 E500_FPR_Bypass, E500_FPR_Bypass]>, 281 InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 282 InstrStage<68, [E500_FPU_0]>], 283 [71, 1, 1], // Latency = 68, Repeat rate = 68 284 [E500_FPR_Bypass, 285 E500_FPR_Bypass, E500_FPR_Bypass]>, 286 InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 287 InstrStage<38, [E500_FPU_0]>], 288 [41, 1, 1], // Latency = 38, Repeat rate = 38 289 [E500_FPR_Bypass, 290 E500_FPR_Bypass, E500_FPR_Bypass]>, 291 InstrItinData<IIC_FPFused, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 292 InstrStage<4, [E500_FPU_0]>], 293 [13, 1, 1, 1], // Latency = 10, Repeat rate = 4 294 [E500_FPR_Bypass, 295 E500_FPR_Bypass, E500_FPR_Bypass, 296 E500_FPR_Bypass]>, 297 InstrItinData<IIC_FPRes, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, 298 InstrStage<38, [E500_FPU_0]>], 299 [41, 1], // Latency = 38, Repeat rate = 38 300 [E500_FPR_Bypass, E500_FPR_Bypass]> 301 ]>; 302 303 // ===---------------------------------------------------------------------===// 304 // e500mc machine model for scheduling and other instruction cost heuristics. 305 306 def PPCE500mcModel : SchedMachineModel { 307 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. 308 let MinLatency = -1; // OperandCycles are interpreted as MinLatency. 309 let LoadLatency = 5; // Optimistic load latency assuming bypass. 310 // This is overriden by OperandCycles if the 311 // Itineraries are queried instead. 312 313 let Itineraries = PPCE500mcItineraries; 314 } 315
