1 //===-- PPCScheduleG3.td - PPC G3 Scheduling Definitions ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the itinerary class data for the G3 (750) processor. 11 // 12 //===----------------------------------------------------------------------===// 13 14 def G3_BPU : FuncUnit; // Branch unit 15 def G3_SLU : FuncUnit; // Store/load unit 16 def G3_SRU : FuncUnit; // special register unit 17 def G3_IU1 : FuncUnit; // integer unit 1 (simple) 18 def G3_IU2 : FuncUnit; // integer unit 2 (complex) 19 def G3_FPU1 : FuncUnit; // floating point unit 1 20 21 def G3Itineraries : ProcessorItineraries< 22 [G3_IU1, G3_IU2, G3_FPU1, G3_BPU, G3_SRU, G3_SLU], [], [ 23 InstrItinData<IIC_IntSimple , [InstrStage<1, [G3_IU1, G3_IU2]>]>, 24 InstrItinData<IIC_IntGeneral , [InstrStage<1, [G3_IU1, G3_IU2]>]>, 25 InstrItinData<IIC_IntCompare , [InstrStage<1, [G3_IU1, G3_IU2]>]>, 26 InstrItinData<IIC_IntDivW , [InstrStage<19, [G3_IU1]>]>, 27 InstrItinData<IIC_IntMFFS , [InstrStage<1, [G3_FPU1]>]>, 28 InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G3_FPU1]>]>, 29 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G3_IU1]>]>, 30 InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G3_IU1]>]>, 31 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G3_IU1]>]>, 32 InstrItinData<IIC_IntRotate , [InstrStage<1, [G3_IU1, G3_IU2]>]>, 33 InstrItinData<IIC_IntShift , [InstrStage<1, [G3_IU1, G3_IU2]>]>, 34 InstrItinData<IIC_IntTrapW , [InstrStage<2, [G3_IU1, G3_IU2]>]>, 35 InstrItinData<IIC_BrB , [InstrStage<1, [G3_BPU]>]>, 36 InstrItinData<IIC_BrCR , [InstrStage<1, [G3_SRU]>]>, 37 InstrItinData<IIC_BrMCR , [InstrStage<1, [G3_SRU]>]>, 38 InstrItinData<IIC_BrMCRX , [InstrStage<1, [G3_SRU]>]>, 39 InstrItinData<IIC_LdStDCBA , [InstrStage<2, [G3_SLU]>]>, 40 InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G3_SLU]>]>, 41 InstrItinData<IIC_LdStDCBI , [InstrStage<3, [G3_SLU]>]>, 42 InstrItinData<IIC_LdStLoad , [InstrStage<2, [G3_SLU]>]>, 43 InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G3_SLU]>]>, 44 InstrItinData<IIC_LdStLoadUpdX, [InstrStage<2, [G3_SLU]>]>, 45 InstrItinData<IIC_LdStStore , [InstrStage<2, [G3_SLU]>]>, 46 InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [G3_SLU]>]>, 47 InstrItinData<IIC_LdStICBI , [InstrStage<3, [G3_SLU]>]>, 48 InstrItinData<IIC_LdStSTFD , [InstrStage<2, [G3_SLU]>]>, 49 InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G3_SLU]>]>, 50 InstrItinData<IIC_LdStLFD , [InstrStage<2, [G3_SLU]>]>, 51 InstrItinData<IIC_LdStLFDU , [InstrStage<2, [G3_SLU]>]>, 52 InstrItinData<IIC_LdStLFDUX , [InstrStage<2, [G3_SLU]>]>, 53 InstrItinData<IIC_LdStLHA , [InstrStage<2, [G3_SLU]>]>, 54 InstrItinData<IIC_LdStLHAU , [InstrStage<2, [G3_SLU]>]>, 55 InstrItinData<IIC_LdStLHAUX , [InstrStage<2, [G3_SLU]>]>, 56 InstrItinData<IIC_LdStLMW , [InstrStage<34, [G3_SLU]>]>, 57 InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G3_SLU]>]>, 58 InstrItinData<IIC_LdStSTWCX , [InstrStage<8, [G3_SLU]>]>, 59 InstrItinData<IIC_LdStSync , [InstrStage<3, [G3_SLU]>]>, 60 InstrItinData<IIC_SprISYNC , [InstrStage<2, [G3_SRU]>]>, 61 InstrItinData<IIC_SprMFSR , [InstrStage<3, [G3_SRU]>]>, 62 InstrItinData<IIC_SprMTMSR , [InstrStage<1, [G3_SRU]>]>, 63 InstrItinData<IIC_SprMTSR , [InstrStage<2, [G3_SRU]>]>, 64 InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G3_SRU]>]>, 65 InstrItinData<IIC_SprMFCR , [InstrStage<1, [G3_SRU]>]>, 66 InstrItinData<IIC_SprMFMSR , [InstrStage<1, [G3_SRU]>]>, 67 InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G3_SRU]>]>, 68 InstrItinData<IIC_SprMFTB , [InstrStage<3, [G3_SRU]>]>, 69 InstrItinData<IIC_SprMTSPR , [InstrStage<2, [G3_SRU]>]>, 70 InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [G3_SRU]>]>, 71 InstrItinData<IIC_SprRFI , [InstrStage<2, [G3_SRU]>]>, 72 InstrItinData<IIC_SprSC , [InstrStage<2, [G3_SRU]>]>, 73 InstrItinData<IIC_FPGeneral , [InstrStage<1, [G3_FPU1]>]>, 74 InstrItinData<IIC_FPAddSub , [InstrStage<1, [G3_FPU1]>]>, 75 InstrItinData<IIC_FPCompare , [InstrStage<1, [G3_FPU1]>]>, 76 InstrItinData<IIC_FPDivD , [InstrStage<31, [G3_FPU1]>]>, 77 InstrItinData<IIC_FPDivS , [InstrStage<17, [G3_FPU1]>]>, 78 InstrItinData<IIC_FPFused , [InstrStage<2, [G3_FPU1]>]>, 79 InstrItinData<IIC_FPRes , [InstrStage<10, [G3_FPU1]>]> 80 ]>; 81
