1 //===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the itinerary class data for the G4+ (7450) processor. 11 // 12 //===----------------------------------------------------------------------===// 13 14 def G4P_BPU : FuncUnit; // Branch unit 15 def G4P_SLU : FuncUnit; // Store/load unit 16 def G4P_SRU : FuncUnit; // special register unit 17 def G4P_IU1 : FuncUnit; // integer unit 1 (simple) 18 def G4P_IU2 : FuncUnit; // integer unit 2 (complex) 19 def G4P_IU3 : FuncUnit; // integer unit 3 (simple) 20 def G4P_IU4 : FuncUnit; // integer unit 4 (simple) 21 def G4P_FPU1 : FuncUnit; // floating point unit 1 22 def G4P_VPU : FuncUnit; // vector permutation unit 23 def G4P_VIU1 : FuncUnit; // vector integer unit 1 (simple) 24 def G4P_VIU2 : FuncUnit; // vector integer unit 2 (complex) 25 def G4P_VFPU : FuncUnit; // vector floating point unit 26 27 def G4PlusItineraries : ProcessorItineraries< 28 [G4P_IU1, G4P_IU2, G4P_IU3, G4P_IU4, G4P_BPU, G4P_SLU, G4P_FPU1, 29 G4P_VFPU, G4P_VIU1, G4P_VIU2, G4P_VPU], [], [ 30 InstrItinData<IIC_IntSimple , [InstrStage<1, [G4P_IU1, G4P_IU2, 31 G4P_IU3, G4P_IU4]>]>, 32 InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4P_IU1, G4P_IU2, 33 G4P_IU3, G4P_IU4]>]>, 34 InstrItinData<IIC_IntCompare , [InstrStage<1, [G4P_IU1, G4P_IU2, 35 G4P_IU3, G4P_IU4]>]>, 36 InstrItinData<IIC_IntDivW , [InstrStage<23, [G4P_IU2]>]>, 37 InstrItinData<IIC_IntMFFS , [InstrStage<5, [G4P_FPU1]>]>, 38 InstrItinData<IIC_IntMFVSCR , [InstrStage<2, [G4P_VFPU]>]>, 39 InstrItinData<IIC_IntMTFSB0 , [InstrStage<5, [G4P_FPU1]>]>, 40 InstrItinData<IIC_IntMulHW , [InstrStage<4, [G4P_IU2]>]>, 41 InstrItinData<IIC_IntMulHWU , [InstrStage<4, [G4P_IU2]>]>, 42 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4P_IU2]>]>, 43 InstrItinData<IIC_IntRotate , [InstrStage<1, [G4P_IU1, G4P_IU2, 44 G4P_IU3, G4P_IU4]>]>, 45 InstrItinData<IIC_IntShift , [InstrStage<2, [G4P_IU1, G4P_IU2, 46 G4P_IU3, G4P_IU4]>]>, 47 InstrItinData<IIC_IntTrapW , [InstrStage<2, [G4P_IU1, G4P_IU2, 48 G4P_IU3, G4P_IU4]>]>, 49 InstrItinData<IIC_BrB , [InstrStage<1, [G4P_BPU]>]>, 50 InstrItinData<IIC_BrCR , [InstrStage<2, [G4P_IU2]>]>, 51 InstrItinData<IIC_BrMCR , [InstrStage<2, [G4P_IU2]>]>, 52 InstrItinData<IIC_BrMCRX , [InstrStage<2, [G4P_IU2]>]>, 53 InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G4P_SLU]>]>, 54 InstrItinData<IIC_LdStDCBI , [InstrStage<3, [G4P_SLU]>]>, 55 InstrItinData<IIC_LdStLoad , [InstrStage<3, [G4P_SLU]>]>, 56 InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G4P_SLU]>]>, 57 InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G4P_SLU]>]>, 58 InstrItinData<IIC_LdStStore , [InstrStage<3, [G4P_SLU]>]>, 59 InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G4P_SLU]>]>, 60 InstrItinData<IIC_LdStDSS , [InstrStage<3, [G4P_SLU]>]>, 61 InstrItinData<IIC_LdStICBI , [InstrStage<3, [G4P_IU2]>]>, 62 InstrItinData<IIC_LdStSTFD , [InstrStage<3, [G4P_SLU]>]>, 63 InstrItinData<IIC_LdStSTFDU , [InstrStage<3, [G4P_SLU]>]>, 64 InstrItinData<IIC_LdStLFD , [InstrStage<4, [G4P_SLU]>]>, 65 InstrItinData<IIC_LdStLFDU , [InstrStage<4, [G4P_SLU]>]>, 66 InstrItinData<IIC_LdStLFDUX , [InstrStage<4, [G4P_SLU]>]>, 67 InstrItinData<IIC_LdStLHA , [InstrStage<3, [G4P_SLU]>]>, 68 InstrItinData<IIC_LdStLHAU , [InstrStage<3, [G4P_SLU]>]>, 69 InstrItinData<IIC_LdStLHAUX , [InstrStage<3, [G4P_SLU]>]>, 70 InstrItinData<IIC_LdStLMW , [InstrStage<37, [G4P_SLU]>]>, 71 InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G4P_SLU]>]>, 72 InstrItinData<IIC_LdStLWA , [InstrStage<3, [G4P_SLU]>]>, 73 InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G4P_SLU]>]>, 74 InstrItinData<IIC_LdStSTD , [InstrStage<3, [G4P_SLU]>]>, 75 InstrItinData<IIC_LdStSTDCX , [InstrStage<3, [G4P_SLU]>]>, 76 InstrItinData<IIC_LdStSTDU , [InstrStage<3, [G4P_SLU]>]>, 77 InstrItinData<IIC_LdStSTDUX , [InstrStage<3, [G4P_SLU]>]>, 78 InstrItinData<IIC_LdStSTVEBX , [InstrStage<3, [G4P_SLU]>]>, 79 InstrItinData<IIC_LdStSTWCX , [InstrStage<3, [G4P_SLU]>]>, 80 InstrItinData<IIC_LdStSync , [InstrStage<35, [G4P_SLU]>]>, 81 InstrItinData<IIC_SprISYNC , [InstrStage<0, [G4P_IU1, G4P_IU2, 82 G4P_IU3, G4P_IU4]>]>, 83 InstrItinData<IIC_SprMFSR , [InstrStage<4, [G4P_IU2]>]>, 84 InstrItinData<IIC_SprMTMSR , [InstrStage<2, [G4P_IU2]>]>, 85 InstrItinData<IIC_SprMTSR , [InstrStage<2, [G4P_IU2]>]>, 86 InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G4P_SLU]>]>, 87 InstrItinData<IIC_SprMFCR , [InstrStage<2, [G4P_IU2]>]>, 88 InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G4P_IU2]>]>, 89 InstrItinData<IIC_SprMFSPR , [InstrStage<4, [G4P_IU2]>]>, 90 InstrItinData<IIC_SprMFTB , [InstrStage<5, [G4P_IU2]>]>, 91 InstrItinData<IIC_SprMTSPR , [InstrStage<2, [G4P_IU2]>]>, 92 InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [G4P_IU2]>]>, 93 InstrItinData<IIC_SprRFI , [InstrStage<1, [G4P_IU1, G4P_IU2, 94 G4P_IU3, G4P_IU4]>]>, 95 InstrItinData<IIC_SprSC , [InstrStage<0, [G4P_IU1, G4P_IU2, 96 G4P_IU3, G4P_IU4]>]>, 97 InstrItinData<IIC_FPGeneral , [InstrStage<5, [G4P_FPU1]>]>, 98 InstrItinData<IIC_FPAddSub , [InstrStage<5, [G4P_FPU1]>]>, 99 InstrItinData<IIC_FPCompare , [InstrStage<5, [G4P_FPU1]>]>, 100 InstrItinData<IIC_FPDivD , [InstrStage<35, [G4P_FPU1]>]>, 101 InstrItinData<IIC_FPDivS , [InstrStage<21, [G4P_FPU1]>]>, 102 InstrItinData<IIC_FPFused , [InstrStage<5, [G4P_FPU1]>]>, 103 InstrItinData<IIC_FPRes , [InstrStage<14, [G4P_FPU1]>]>, 104 InstrItinData<IIC_VecGeneral , [InstrStage<1, [G4P_VIU1]>]>, 105 InstrItinData<IIC_VecFP , [InstrStage<4, [G4P_VFPU]>]>, 106 InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G4P_VFPU]>]>, 107 InstrItinData<IIC_VecComplex , [InstrStage<4, [G4P_VIU2]>]>, 108 InstrItinData<IIC_VecPerm , [InstrStage<2, [G4P_VPU]>]>, 109 InstrItinData<IIC_VecFPRound , [InstrStage<4, [G4P_VIU1]>]>, 110 InstrItinData<IIC_VecVSL , [InstrStage<2, [G4P_VPU]>]>, 111 InstrItinData<IIC_VecVSR , [InstrStage<2, [G4P_VPU]>]> 112 ]>; 113
