1 ; RUN: llc -march=arm64 < %s | FileCheck %s 2 ; rdar://10232252 3 4 @object = external hidden global i64, section "__DATA, __objc_ivar", align 8 5 6 ; base + offset (imm9) 7 ; CHECK: @t1 8 ; CHECK: ldr xzr, [x{{[0-9]+}}, #8] 9 ; CHECK: ret 10 define void @t1() { 11 %incdec.ptr = getelementptr inbounds i64* @object, i64 1 12 %tmp = load volatile i64* %incdec.ptr, align 8 13 ret void 14 } 15 16 ; base + offset (> imm9) 17 ; CHECK: @t2 18 ; CHECK: sub [[ADDREG:x[0-9]+]], x{{[0-9]+}}, #264 19 ; CHECK: ldr xzr, [ 20 ; CHECK: [[ADDREG]]] 21 ; CHECK: ret 22 define void @t2() { 23 %incdec.ptr = getelementptr inbounds i64* @object, i64 -33 24 %tmp = load volatile i64* %incdec.ptr, align 8 25 ret void 26 } 27 28 ; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes) 29 ; CHECK: @t3 30 ; CHECK: ldr xzr, [x{{[0-9]+}}, #32760] 31 ; CHECK: ret 32 define void @t3() { 33 %incdec.ptr = getelementptr inbounds i64* @object, i64 4095 34 %tmp = load volatile i64* %incdec.ptr, align 8 35 ret void 36 } 37 38 ; base + unsigned offset (> imm12 * size of type in bytes) 39 ; CHECK: @t4 40 ; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, #8, lsl #12 41 ; CHECK: ldr xzr, [ 42 ; CHECK: [[ADDREG]]] 43 ; CHECK: ret 44 define void @t4() { 45 %incdec.ptr = getelementptr inbounds i64* @object, i64 4096 46 %tmp = load volatile i64* %incdec.ptr, align 8 47 ret void 48 } 49 50 ; base + reg 51 ; CHECK: @t5 52 ; CHECK: ldr xzr, [x{{[0-9]+}}, x{{[0-9]+}}, lsl #3] 53 ; CHECK: ret 54 define void @t5(i64 %a) { 55 %incdec.ptr = getelementptr inbounds i64* @object, i64 %a 56 %tmp = load volatile i64* %incdec.ptr, align 8 57 ret void 58 } 59 60 ; base + reg + imm 61 ; CHECK: @t6 62 ; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, x{{[0-9]+}}, lsl #3 63 ; CHECK-NEXT: add [[ADDREG]], [[ADDREG]], #8, lsl #12 64 ; CHECK: ldr xzr, [ 65 ; CHECK: [[ADDREG]]] 66 ; CHECK: ret 67 define void @t6(i64 %a) { 68 %tmp1 = getelementptr inbounds i64* @object, i64 %a 69 %incdec.ptr = getelementptr inbounds i64* %tmp1, i64 4096 70 %tmp = load volatile i64* %incdec.ptr, align 8 71 ret void 72 } 73
