1 ; RUN: llc -mtriple arm64_be < %s -aarch64-load-store-opt=false -o - | FileCheck %s 2 ; RUN: llc -mtriple arm64_be < %s -fast-isel=true -aarch64-load-store-opt=false -o - | FileCheck %s 3 4 ; CHECK-LABEL: test_i64_f64: 5 define i64 @test_i64_f64(double %p) { 6 ; CHECK-NOT: rev 7 %1 = fadd double %p, %p 8 %2 = bitcast double %1 to i64 9 %3 = add i64 %2, %2 10 ret i64 %3 11 } 12 13 ; CHECK-LABEL: test_i64_v1i64: 14 define i64 @test_i64_v1i64(<1 x i64> %p) { 15 ; CHECK-NOT: rev 16 %1 = add <1 x i64> %p, %p 17 %2 = bitcast <1 x i64> %1 to i64 18 %3 = add i64 %2, %2 19 ret i64 %3 20 } 21 22 ; CHECK-LABEL: test_i64_v2f32: 23 define i64 @test_i64_v2f32(<2 x float> %p) { 24 ; CHECK: rev64 v{{[0-9]+}}.2s 25 %1 = fadd <2 x float> %p, %p 26 %2 = bitcast <2 x float> %1 to i64 27 %3 = add i64 %2, %2 28 ret i64 %3 29 } 30 31 ; CHECK-LABEL: test_i64_v2i32: 32 define i64 @test_i64_v2i32(<2 x i32> %p) { 33 ; CHECK: rev64 v{{[0-9]+}}.2s 34 %1 = add <2 x i32> %p, %p 35 %2 = bitcast <2 x i32> %1 to i64 36 %3 = add i64 %2, %2 37 ret i64 %3 38 } 39 40 ; CHECK-LABEL: test_i64_v4i16: 41 define i64 @test_i64_v4i16(<4 x i16> %p) { 42 ; CHECK: rev64 v{{[0-9]+}}.4h 43 %1 = add <4 x i16> %p, %p 44 %2 = bitcast <4 x i16> %1 to i64 45 %3 = add i64 %2, %2 46 ret i64 %3 47 } 48 49 ; CHECK-LABEL: test_i64_v8i8: 50 define i64 @test_i64_v8i8(<8 x i8> %p) { 51 ; CHECK: rev64 v{{[0-9]+}}.8b 52 %1 = add <8 x i8> %p, %p 53 %2 = bitcast <8 x i8> %1 to i64 54 %3 = add i64 %2, %2 55 ret i64 %3 56 } 57 58 ; CHECK-LABEL: test_f64_i64: 59 define double @test_f64_i64(i64 %p) { 60 ; CHECK-NOT: rev 61 %1 = add i64 %p, %p 62 %2 = bitcast i64 %1 to double 63 %3 = fadd double %2, %2 64 ret double %3 65 } 66 67 ; CHECK-LABEL: test_f64_v1i64: 68 define double @test_f64_v1i64(<1 x i64> %p) { 69 ; CHECK-NOT: rev 70 %1 = add <1 x i64> %p, %p 71 %2 = bitcast <1 x i64> %1 to double 72 %3 = fadd double %2, %2 73 ret double %3 74 } 75 76 ; CHECK-LABEL: test_f64_v2f32: 77 define double @test_f64_v2f32(<2 x float> %p) { 78 ; CHECK: rev64 v{{[0-9]+}}.2s 79 %1 = fadd <2 x float> %p, %p 80 %2 = bitcast <2 x float> %1 to double 81 %3 = fadd double %2, %2 82 ret double %3 83 } 84 85 ; CHECK-LABEL: test_f64_v2i32: 86 define double @test_f64_v2i32(<2 x i32> %p) { 87 ; CHECK: rev64 v{{[0-9]+}}.2s 88 %1 = add <2 x i32> %p, %p 89 %2 = bitcast <2 x i32> %1 to double 90 %3 = fadd double %2, %2 91 ret double %3 92 } 93 94 ; CHECK-LABEL: test_f64_v4i16: 95 define double @test_f64_v4i16(<4 x i16> %p) { 96 ; CHECK: rev64 v{{[0-9]+}}.4h 97 %1 = add <4 x i16> %p, %p 98 %2 = bitcast <4 x i16> %1 to double 99 %3 = fadd double %2, %2 100 ret double %3 101 } 102 103 ; CHECK-LABEL: test_f64_v8i8: 104 define double @test_f64_v8i8(<8 x i8> %p) { 105 ; CHECK: rev64 v{{[0-9]+}}.8b 106 %1 = add <8 x i8> %p, %p 107 %2 = bitcast <8 x i8> %1 to double 108 %3 = fadd double %2, %2 109 ret double %3 110 } 111 112 ; CHECK-LABEL: test_v1i64_i64: 113 define <1 x i64> @test_v1i64_i64(i64 %p) { 114 ; CHECK-NOT: rev 115 %1 = add i64 %p, %p 116 %2 = bitcast i64 %1 to <1 x i64> 117 %3 = add <1 x i64> %2, %2 118 ret <1 x i64> %3 119 } 120 121 ; CHECK-LABEL: test_v1i64_f64: 122 define <1 x i64> @test_v1i64_f64(double %p) { 123 ; CHECK-NOT: rev 124 %1 = fadd double %p, %p 125 %2 = bitcast double %1 to <1 x i64> 126 %3 = add <1 x i64> %2, %2 127 ret <1 x i64> %3 128 } 129 130 ; CHECK-LABEL: test_v1i64_v2f32: 131 define <1 x i64> @test_v1i64_v2f32(<2 x float> %p) { 132 ; CHECK: rev64 v{{[0-9]+}}.2s 133 %1 = fadd <2 x float> %p, %p 134 %2 = bitcast <2 x float> %1 to <1 x i64> 135 %3 = add <1 x i64> %2, %2 136 ret <1 x i64> %3 137 } 138 139 ; CHECK-LABEL: test_v1i64_v2i32: 140 define <1 x i64> @test_v1i64_v2i32(<2 x i32> %p) { 141 ; CHECK: rev64 v{{[0-9]+}}.2s 142 %1 = add <2 x i32> %p, %p 143 %2 = bitcast <2 x i32> %1 to <1 x i64> 144 %3 = add <1 x i64> %2, %2 145 ret <1 x i64> %3 146 } 147 148 ; CHECK-LABEL: test_v1i64_v4i16: 149 define <1 x i64> @test_v1i64_v4i16(<4 x i16> %p) { 150 ; CHECK: rev64 v{{[0-9]+}}.4h 151 %1 = add <4 x i16> %p, %p 152 %2 = bitcast <4 x i16> %1 to <1 x i64> 153 %3 = add <1 x i64> %2, %2 154 ret <1 x i64> %3 155 } 156 157 ; CHECK-LABEL: test_v1i64_v8i8: 158 define <1 x i64> @test_v1i64_v8i8(<8 x i8> %p) { 159 ; CHECK: rev64 v{{[0-9]+}}.8b 160 %1 = add <8 x i8> %p, %p 161 %2 = bitcast <8 x i8> %1 to <1 x i64> 162 %3 = add <1 x i64> %2, %2 163 ret <1 x i64> %3 164 } 165 166 ; CHECK-LABEL: test_v2f32_i64: 167 define <2 x float> @test_v2f32_i64(i64 %p) { 168 ; CHECK: rev64 v{{[0-9]+}}.2s 169 %1 = add i64 %p, %p 170 %2 = bitcast i64 %1 to <2 x float> 171 %3 = fadd <2 x float> %2, %2 172 ret <2 x float> %3 173 } 174 175 ; CHECK-LABEL: test_v2f32_f64: 176 define <2 x float> @test_v2f32_f64(double %p) { 177 ; CHECK: rev64 v{{[0-9]+}}.2s 178 %1 = fadd double %p, %p 179 %2 = bitcast double %1 to <2 x float> 180 %3 = fadd <2 x float> %2, %2 181 ret <2 x float> %3 182 } 183 184 ; CHECK-LABEL: test_v2f32_v1i64: 185 define <2 x float> @test_v2f32_v1i64(<1 x i64> %p) { 186 ; CHECK: rev64 v{{[0-9]+}}.2s 187 %1 = add <1 x i64> %p, %p 188 %2 = bitcast <1 x i64> %1 to <2 x float> 189 %3 = fadd <2 x float> %2, %2 190 ret <2 x float> %3 191 } 192 193 ; CHECK-LABEL: test_v2f32_v2i32: 194 define <2 x float> @test_v2f32_v2i32(<2 x i32> %p) { 195 ; CHECK: rev64 v{{[0-9]+}}.2s 196 ; CHECK: rev64 v{{[0-9]+}}.2s 197 %1 = add <2 x i32> %p, %p 198 %2 = bitcast <2 x i32> %1 to <2 x float> 199 %3 = fadd <2 x float> %2, %2 200 ret <2 x float> %3 201 } 202 203 ; CHECK-LABEL: test_v2f32_v4i16: 204 define <2 x float> @test_v2f32_v4i16(<4 x i16> %p) { 205 ; CHECK: rev64 v{{[0-9]+}}.4h 206 ; CHECK: rev64 v{{[0-9]+}}.2s 207 %1 = add <4 x i16> %p, %p 208 %2 = bitcast <4 x i16> %1 to <2 x float> 209 %3 = fadd <2 x float> %2, %2 210 ret <2 x float> %3 211 } 212 213 ; CHECK-LABEL: test_v2f32_v8i8: 214 define <2 x float> @test_v2f32_v8i8(<8 x i8> %p) { 215 ; CHECK: rev64 v{{[0-9]+}}.8b 216 ; CHECK: rev64 v{{[0-9]+}}.2s 217 %1 = add <8 x i8> %p, %p 218 %2 = bitcast <8 x i8> %1 to <2 x float> 219 %3 = fadd <2 x float> %2, %2 220 ret <2 x float> %3 221 } 222 223 ; CHECK-LABEL: test_v2i32_i64: 224 define <2 x i32> @test_v2i32_i64(i64 %p) { 225 ; CHECK: rev64 v{{[0-9]+}}.2s 226 %1 = add i64 %p, %p 227 %2 = bitcast i64 %1 to <2 x i32> 228 %3 = add <2 x i32> %2, %2 229 ret <2 x i32> %3 230 } 231 232 ; CHECK-LABEL: test_v2i32_f64: 233 define <2 x i32> @test_v2i32_f64(double %p) { 234 ; CHECK: rev64 v{{[0-9]+}}.2s 235 %1 = fadd double %p, %p 236 %2 = bitcast double %1 to <2 x i32> 237 %3 = add <2 x i32> %2, %2 238 ret <2 x i32> %3 239 } 240 241 ; CHECK-LABEL: test_v2i32_v1i64: 242 define <2 x i32> @test_v2i32_v1i64(<1 x i64> %p) { 243 ; CHECK: rev64 v{{[0-9]+}}.2s 244 %1 = add <1 x i64> %p, %p 245 %2 = bitcast <1 x i64> %1 to <2 x i32> 246 %3 = add <2 x i32> %2, %2 247 ret <2 x i32> %3 248 } 249 250 ; CHECK-LABEL: test_v2i32_v2f32: 251 define <2 x i32> @test_v2i32_v2f32(<2 x float> %p) { 252 ; CHECK: rev64 v{{[0-9]+}}.2s 253 ; CHECK: rev64 v{{[0-9]+}}.2s 254 %1 = fadd <2 x float> %p, %p 255 %2 = bitcast <2 x float> %1 to <2 x i32> 256 %3 = add <2 x i32> %2, %2 257 ret <2 x i32> %3 258 } 259 260 ; CHECK-LABEL: test_v2i32_v4i16: 261 define <2 x i32> @test_v2i32_v4i16(<4 x i16> %p) { 262 ; CHECK: rev64 v{{[0-9]+}}.4h 263 ; CHECK: rev64 v{{[0-9]+}}.2s 264 %1 = add <4 x i16> %p, %p 265 %2 = bitcast <4 x i16> %1 to <2 x i32> 266 %3 = add <2 x i32> %2, %2 267 ret <2 x i32> %3 268 } 269 270 ; CHECK-LABEL: test_v2i32_v8i8: 271 define <2 x i32> @test_v2i32_v8i8(<8 x i8> %p) { 272 ; CHECK: rev64 v{{[0-9]+}}.8b 273 ; CHECK: rev64 v{{[0-9]+}}.2s 274 %1 = add <8 x i8> %p, %p 275 %2 = bitcast <8 x i8> %1 to <2 x i32> 276 %3 = add <2 x i32> %2, %2 277 ret <2 x i32> %3 278 } 279 280 ; CHECK-LABEL: test_v4i16_i64: 281 define <4 x i16> @test_v4i16_i64(i64 %p) { 282 ; CHECK: rev64 v{{[0-9]+}}.4h 283 %1 = add i64 %p, %p 284 %2 = bitcast i64 %1 to <4 x i16> 285 %3 = add <4 x i16> %2, %2 286 ret <4 x i16> %3 287 } 288 289 ; CHECK-LABEL: test_v4i16_f64: 290 define <4 x i16> @test_v4i16_f64(double %p) { 291 ; CHECK: rev64 v{{[0-9]+}}.4h 292 %1 = fadd double %p, %p 293 %2 = bitcast double %1 to <4 x i16> 294 %3 = add <4 x i16> %2, %2 295 ret <4 x i16> %3 296 } 297 298 ; CHECK-LABEL: test_v4i16_v1i64: 299 define <4 x i16> @test_v4i16_v1i64(<1 x i64> %p) { 300 ; CHECK: rev64 v{{[0-9]+}}.4h 301 %1 = add <1 x i64> %p, %p 302 %2 = bitcast <1 x i64> %1 to <4 x i16> 303 %3 = add <4 x i16> %2, %2 304 ret <4 x i16> %3 305 } 306 307 ; CHECK-LABEL: test_v4i16_v2f32: 308 define <4 x i16> @test_v4i16_v2f32(<2 x float> %p) { 309 ; CHECK: rev64 v{{[0-9]+}}.2s 310 ; CHECK: rev64 v{{[0-9]+}}.4h 311 %1 = fadd <2 x float> %p, %p 312 %2 = bitcast <2 x float> %1 to <4 x i16> 313 %3 = add <4 x i16> %2, %2 314 ret <4 x i16> %3 315 } 316 317 ; CHECK-LABEL: test_v4i16_v2i32: 318 define <4 x i16> @test_v4i16_v2i32(<2 x i32> %p) { 319 ; CHECK: rev64 v{{[0-9]+}}.2s 320 ; CHECK: rev64 v{{[0-9]+}}.4h 321 %1 = add <2 x i32> %p, %p 322 %2 = bitcast <2 x i32> %1 to <4 x i16> 323 %3 = add <4 x i16> %2, %2 324 ret <4 x i16> %3 325 } 326 327 ; CHECK-LABEL: test_v4i16_v8i8: 328 define <4 x i16> @test_v4i16_v8i8(<8 x i8> %p) { 329 ; CHECK: rev64 v{{[0-9]+}}.8b 330 ; CHECK: rev64 v{{[0-9]+}}.4h 331 %1 = add <8 x i8> %p, %p 332 %2 = bitcast <8 x i8> %1 to <4 x i16> 333 %3 = add <4 x i16> %2, %2 334 ret <4 x i16> %3 335 } 336 337 ; CHECK-LABEL: test_v8i8_i64: 338 define <8 x i8> @test_v8i8_i64(i64 %p) { 339 ; CHECK: rev64 v{{[0-9]+}}.8b 340 %1 = add i64 %p, %p 341 %2 = bitcast i64 %1 to <8 x i8> 342 %3 = add <8 x i8> %2, %2 343 ret <8 x i8> %3 344 } 345 346 ; CHECK-LABEL: test_v8i8_f64: 347 define <8 x i8> @test_v8i8_f64(double %p) { 348 ; CHECK: rev64 v{{[0-9]+}}.8b 349 %1 = fadd double %p, %p 350 %2 = bitcast double %1 to <8 x i8> 351 %3 = add <8 x i8> %2, %2 352 ret <8 x i8> %3 353 } 354 355 ; CHECK-LABEL: test_v8i8_v1i64: 356 define <8 x i8> @test_v8i8_v1i64(<1 x i64> %p) { 357 ; CHECK: rev64 v{{[0-9]+}}.8b 358 %1 = add <1 x i64> %p, %p 359 %2 = bitcast <1 x i64> %1 to <8 x i8> 360 %3 = add <8 x i8> %2, %2 361 ret <8 x i8> %3 362 } 363 364 ; CHECK-LABEL: test_v8i8_v2f32: 365 define <8 x i8> @test_v8i8_v2f32(<2 x float> %p) { 366 ; CHECK: rev64 v{{[0-9]+}}.2s 367 ; CHECK: rev64 v{{[0-9]+}}.8b 368 %1 = fadd <2 x float> %p, %p 369 %2 = bitcast <2 x float> %1 to <8 x i8> 370 %3 = add <8 x i8> %2, %2 371 ret <8 x i8> %3 372 } 373 374 ; CHECK-LABEL: test_v8i8_v2i32: 375 define <8 x i8> @test_v8i8_v2i32(<2 x i32> %p) { 376 ; CHECK: rev64 v{{[0-9]+}}.2s 377 ; CHECK: rev64 v{{[0-9]+}}.8b 378 %1 = add <2 x i32> %p, %p 379 %2 = bitcast <2 x i32> %1 to <8 x i8> 380 %3 = add <8 x i8> %2, %2 381 ret <8 x i8> %3 382 } 383 384 ; CHECK-LABEL: test_v8i8_v4i16: 385 define <8 x i8> @test_v8i8_v4i16(<4 x i16> %p) { 386 ; CHECK: rev64 v{{[0-9]+}}.4h 387 ; CHECK: rev64 v{{[0-9]+}}.8b 388 %1 = add <4 x i16> %p, %p 389 %2 = bitcast <4 x i16> %1 to <8 x i8> 390 %3 = add <8 x i8> %2, %2 391 ret <8 x i8> %3 392 } 393 394 ; CHECK-LABEL: test_f128_v2f64: 395 define fp128 @test_f128_v2f64(<2 x double> %p) { 396 ; CHECK: ext 397 %1 = fadd <2 x double> %p, %p 398 %2 = bitcast <2 x double> %1 to fp128 399 %3 = fadd fp128 %2, %2 400 ret fp128 %3 401 } 402 403 ; CHECK-LABEL: test_f128_v2i64: 404 define fp128 @test_f128_v2i64(<2 x i64> %p) { 405 ; CHECK: ext 406 %1 = add <2 x i64> %p, %p 407 %2 = bitcast <2 x i64> %1 to fp128 408 %3 = fadd fp128 %2, %2 409 ret fp128 %3 410 } 411 412 ; CHECK-LABEL: test_f128_v4f32: 413 define fp128 @test_f128_v4f32(<4 x float> %p) { 414 ; CHECK: rev64 v{{[0-9]+}}.4s 415 ; CHECK: ext 416 %1 = fadd <4 x float> %p, %p 417 %2 = bitcast <4 x float> %1 to fp128 418 %3 = fadd fp128 %2, %2 419 ret fp128 %3 420 } 421 422 ; CHECK-LABEL: test_f128_v4i32: 423 define fp128 @test_f128_v4i32(<4 x i32> %p) { 424 ; CHECK: rev64 v{{[0-9]+}}.4s 425 ; CHECK: ext 426 %1 = add <4 x i32> %p, %p 427 %2 = bitcast <4 x i32> %1 to fp128 428 %3 = fadd fp128 %2, %2 429 ret fp128 %3 430 } 431 432 ; CHECK-LABEL: test_f128_v8i16: 433 define fp128 @test_f128_v8i16(<8 x i16> %p) { 434 ; CHECK: rev64 v{{[0-9]+}}.8h 435 ; CHECK: ext 436 %1 = add <8 x i16> %p, %p 437 %2 = bitcast <8 x i16> %1 to fp128 438 %3 = fadd fp128 %2, %2 439 ret fp128 %3 440 } 441 442 ; CHECK-LABEL: test_f128_v16i8: 443 define fp128 @test_f128_v16i8(<16 x i8> %p) { 444 ; CHECK: rev64 v{{[0-9]+}}.16b 445 ; CHECK: ext 446 %1 = add <16 x i8> %p, %p 447 %2 = bitcast <16 x i8> %1 to fp128 448 %3 = fadd fp128 %2, %2 449 ret fp128 %3 450 } 451 452 ; CHECK-LABEL: test_v2f64_f128: 453 define <2 x double> @test_v2f64_f128(fp128 %p) { 454 ; CHECK: ext 455 %1 = fadd fp128 %p, %p 456 %2 = bitcast fp128 %1 to <2 x double> 457 %3 = fadd <2 x double> %2, %2 458 ret <2 x double> %3 459 } 460 461 ; CHECK-LABEL: test_v2f64_v2i64: 462 define <2 x double> @test_v2f64_v2i64(<2 x i64> %p) { 463 ; CHECK: ext 464 ; CHECK: ext 465 %1 = add <2 x i64> %p, %p 466 %2 = bitcast <2 x i64> %1 to <2 x double> 467 %3 = fadd <2 x double> %2, %2 468 ret <2 x double> %3 469 } 470 471 ; CHECK-LABEL: test_v2f64_v4f32: 472 define <2 x double> @test_v2f64_v4f32(<4 x float> %p) { 473 ; CHECK: rev64 v{{[0-9]+}}.4s 474 ; CHECK: ext 475 ; CHECK: ext 476 %1 = fadd <4 x float> %p, %p 477 %2 = bitcast <4 x float> %1 to <2 x double> 478 %3 = fadd <2 x double> %2, %2 479 ret <2 x double> %3 480 } 481 482 ; CHECK-LABEL: test_v2f64_v4i32: 483 define <2 x double> @test_v2f64_v4i32(<4 x i32> %p) { 484 ; CHECK: rev64 v{{[0-9]+}}.4s 485 ; CHECK: ext 486 ; CHECK: ext 487 %1 = add <4 x i32> %p, %p 488 %2 = bitcast <4 x i32> %1 to <2 x double> 489 %3 = fadd <2 x double> %2, %2 490 ret <2 x double> %3 491 } 492 493 ; CHECK-LABEL: test_v2f64_v8i16: 494 define <2 x double> @test_v2f64_v8i16(<8 x i16> %p) { 495 ; CHECK: rev64 v{{[0-9]+}}.8h 496 ; CHECK: ext 497 ; CHECK: ext 498 %1 = add <8 x i16> %p, %p 499 %2 = bitcast <8 x i16> %1 to <2 x double> 500 %3 = fadd <2 x double> %2, %2 501 ret <2 x double> %3 502 } 503 504 ; CHECK-LABEL: test_v2f64_v16i8: 505 define <2 x double> @test_v2f64_v16i8(<16 x i8> %p) { 506 ; CHECK: rev64 v{{[0-9]+}}.16b 507 ; CHECK: ext 508 ; CHECK: ext 509 %1 = add <16 x i8> %p, %p 510 %2 = bitcast <16 x i8> %1 to <2 x double> 511 %3 = fadd <2 x double> %2, %2 512 ret <2 x double> %3 513 } 514 515 ; CHECK-LABEL: test_v2i64_f128: 516 define <2 x i64> @test_v2i64_f128(fp128 %p) { 517 ; CHECK: ext 518 %1 = fadd fp128 %p, %p 519 %2 = bitcast fp128 %1 to <2 x i64> 520 %3 = add <2 x i64> %2, %2 521 ret <2 x i64> %3 522 } 523 524 ; CHECK-LABEL: test_v2i64_v2f64: 525 define <2 x i64> @test_v2i64_v2f64(<2 x double> %p) { 526 ; CHECK: ext 527 ; CHECK: ext 528 %1 = fadd <2 x double> %p, %p 529 %2 = bitcast <2 x double> %1 to <2 x i64> 530 %3 = add <2 x i64> %2, %2 531 ret <2 x i64> %3 532 } 533 534 ; CHECK-LABEL: test_v2i64_v4f32: 535 define <2 x i64> @test_v2i64_v4f32(<4 x float> %p) { 536 ; CHECK: rev64 v{{[0-9]+}}.4s 537 ; CHECK: ext 538 ; CHECK: ext 539 %1 = fadd <4 x float> %p, %p 540 %2 = bitcast <4 x float> %1 to <2 x i64> 541 %3 = add <2 x i64> %2, %2 542 ret <2 x i64> %3 543 } 544 545 ; CHECK-LABEL: test_v2i64_v4i32: 546 define <2 x i64> @test_v2i64_v4i32(<4 x i32> %p) { 547 ; CHECK: rev64 v{{[0-9]+}}.4s 548 ; CHECK: ext 549 ; CHECK: ext 550 %1 = add <4 x i32> %p, %p 551 %2 = bitcast <4 x i32> %1 to <2 x i64> 552 %3 = add <2 x i64> %2, %2 553 ret <2 x i64> %3 554 } 555 556 ; CHECK-LABEL: test_v2i64_v8i16: 557 define <2 x i64> @test_v2i64_v8i16(<8 x i16> %p) { 558 ; CHECK: rev64 v{{[0-9]+}}.8h 559 ; CHECK: ext 560 ; CHECK: ext 561 %1 = add <8 x i16> %p, %p 562 %2 = bitcast <8 x i16> %1 to <2 x i64> 563 %3 = add <2 x i64> %2, %2 564 ret <2 x i64> %3 565 } 566 567 ; CHECK-LABEL: test_v2i64_v16i8: 568 define <2 x i64> @test_v2i64_v16i8(<16 x i8> %p) { 569 ; CHECK: rev64 v{{[0-9]+}}.16b 570 ; CHECK: ext 571 ; CHECK: ext 572 %1 = add <16 x i8> %p, %p 573 %2 = bitcast <16 x i8> %1 to <2 x i64> 574 %3 = add <2 x i64> %2, %2 575 ret <2 x i64> %3 576 } 577 578 ; CHECK-LABEL: test_v4f32_f128: 579 define <4 x float> @test_v4f32_f128(fp128 %p) { 580 ; CHECK: rev64 v{{[0-9]+}}.4s 581 ; CHECK: ext 582 %1 = fadd fp128 %p, %p 583 %2 = bitcast fp128 %1 to <4 x float> 584 %3 = fadd <4 x float> %2, %2 585 ret <4 x float> %3 586 } 587 588 ; CHECK-LABEL: test_v4f32_v2f64: 589 define <4 x float> @test_v4f32_v2f64(<2 x double> %p) { 590 ; CHECK: ext 591 ; CHECK: rev64 v{{[0-9]+}}.4s 592 ; CHECK: ext 593 %1 = fadd <2 x double> %p, %p 594 %2 = bitcast <2 x double> %1 to <4 x float> 595 %3 = fadd <4 x float> %2, %2 596 ret <4 x float> %3 597 } 598 599 ; CHECK-LABEL: test_v4f32_v2i64: 600 define <4 x float> @test_v4f32_v2i64(<2 x i64> %p) { 601 ; CHECK: ext 602 ; CHECK: rev64 v{{[0-9]+}}.4s 603 ; CHECK: ext 604 %1 = add <2 x i64> %p, %p 605 %2 = bitcast <2 x i64> %1 to <4 x float> 606 %3 = fadd <4 x float> %2, %2 607 ret <4 x float> %3 608 } 609 610 ; CHECK-LABEL: test_v4f32_v4i32: 611 define <4 x float> @test_v4f32_v4i32(<4 x i32> %p) { 612 ; CHECK: rev64 v{{[0-9]+}}.4s 613 ; CHECK: ext 614 ; CHECK: rev64 v{{[0-9]+}}.4s 615 ; CHECK: ext 616 %1 = add <4 x i32> %p, %p 617 %2 = bitcast <4 x i32> %1 to <4 x float> 618 %3 = fadd <4 x float> %2, %2 619 ret <4 x float> %3 620 } 621 622 ; CHECK-LABEL: test_v4f32_v8i16: 623 define <4 x float> @test_v4f32_v8i16(<8 x i16> %p) { 624 ; CHECK: rev64 v{{[0-9]+}}.8h 625 ; CHECK: ext 626 ; CHECK: rev64 v{{[0-9]+}}.4s 627 ; CHECK: ext 628 %1 = add <8 x i16> %p, %p 629 %2 = bitcast <8 x i16> %1 to <4 x float> 630 %3 = fadd <4 x float> %2, %2 631 ret <4 x float> %3 632 } 633 634 ; CHECK-LABEL: test_v4f32_v16i8: 635 define <4 x float> @test_v4f32_v16i8(<16 x i8> %p) { 636 ; CHECK: rev64 v{{[0-9]+}}.16b 637 ; CHECK: ext 638 ; CHECK: rev64 v{{[0-9]+}}.4s 639 ; CHECK: ext 640 %1 = add <16 x i8> %p, %p 641 %2 = bitcast <16 x i8> %1 to <4 x float> 642 %3 = fadd <4 x float> %2, %2 643 ret <4 x float> %3 644 } 645 646 ; CHECK-LABEL: test_v4i32_f128: 647 define <4 x i32> @test_v4i32_f128(fp128 %p) { 648 ; CHECK: rev64 v{{[0-9]+}}.4s 649 ; CHECK: ext 650 %1 = fadd fp128 %p, %p 651 %2 = bitcast fp128 %1 to <4 x i32> 652 %3 = add <4 x i32> %2, %2 653 ret <4 x i32> %3 654 } 655 656 ; CHECK-LABEL: test_v4i32_v2f64: 657 define <4 x i32> @test_v4i32_v2f64(<2 x double> %p) { 658 ; CHECK: ext 659 ; CHECK: rev64 v{{[0-9]+}}.4s 660 ; CHECK: ext 661 %1 = fadd <2 x double> %p, %p 662 %2 = bitcast <2 x double> %1 to <4 x i32> 663 %3 = add <4 x i32> %2, %2 664 ret <4 x i32> %3 665 } 666 667 ; CHECK-LABEL: test_v4i32_v2i64: 668 define <4 x i32> @test_v4i32_v2i64(<2 x i64> %p) { 669 ; CHECK: ext 670 ; CHECK: rev64 v{{[0-9]+}}.4s 671 ; CHECK: ext 672 %1 = add <2 x i64> %p, %p 673 %2 = bitcast <2 x i64> %1 to <4 x i32> 674 %3 = add <4 x i32> %2, %2 675 ret <4 x i32> %3 676 } 677 678 ; CHECK-LABEL: test_v4i32_v4f32: 679 define <4 x i32> @test_v4i32_v4f32(<4 x float> %p) { 680 ; CHECK: rev64 v{{[0-9]+}}.4s 681 ; CHECK: ext 682 ; CHECK: rev64 v{{[0-9]+}}.4s 683 ; CHECK: ext 684 %1 = fadd <4 x float> %p, %p 685 %2 = bitcast <4 x float> %1 to <4 x i32> 686 %3 = add <4 x i32> %2, %2 687 ret <4 x i32> %3 688 } 689 690 ; CHECK-LABEL: test_v4i32_v8i16: 691 define <4 x i32> @test_v4i32_v8i16(<8 x i16> %p) { 692 ; CHECK: rev64 v{{[0-9]+}}.8h 693 ; CHECK: ext 694 ; CHECK: rev64 v{{[0-9]+}}.4s 695 ; CHECK: ext 696 %1 = add <8 x i16> %p, %p 697 %2 = bitcast <8 x i16> %1 to <4 x i32> 698 %3 = add <4 x i32> %2, %2 699 ret <4 x i32> %3 700 } 701 702 ; CHECK-LABEL: test_v4i32_v16i8: 703 define <4 x i32> @test_v4i32_v16i8(<16 x i8> %p) { 704 ; CHECK: rev64 v{{[0-9]+}}.16b 705 ; CHECK: ext 706 ; CHECK: rev64 v{{[0-9]+}}.4s 707 ; CHECK: ext 708 %1 = add <16 x i8> %p, %p 709 %2 = bitcast <16 x i8> %1 to <4 x i32> 710 %3 = add <4 x i32> %2, %2 711 ret <4 x i32> %3 712 } 713 714 ; CHECK-LABEL: test_v8i16_f128: 715 define <8 x i16> @test_v8i16_f128(fp128 %p) { 716 ; CHECK: rev64 v{{[0-9]+}}.8h 717 ; CHECK: ext 718 %1 = fadd fp128 %p, %p 719 %2 = bitcast fp128 %1 to <8 x i16> 720 %3 = add <8 x i16> %2, %2 721 ret <8 x i16> %3 722 } 723 724 ; CHECK-LABEL: test_v8i16_v2f64: 725 define <8 x i16> @test_v8i16_v2f64(<2 x double> %p) { 726 ; CHECK: ext 727 ; CHECK: rev64 v{{[0-9]+}}.8h 728 ; CHECK: ext 729 %1 = fadd <2 x double> %p, %p 730 %2 = bitcast <2 x double> %1 to <8 x i16> 731 %3 = add <8 x i16> %2, %2 732 ret <8 x i16> %3 733 } 734 735 ; CHECK-LABEL: test_v8i16_v2i64: 736 define <8 x i16> @test_v8i16_v2i64(<2 x i64> %p) { 737 ; CHECK: ext 738 ; CHECK: rev64 v{{[0-9]+}}.8h 739 ; CHECK: ext 740 %1 = add <2 x i64> %p, %p 741 %2 = bitcast <2 x i64> %1 to <8 x i16> 742 %3 = add <8 x i16> %2, %2 743 ret <8 x i16> %3 744 } 745 746 ; CHECK-LABEL: test_v8i16_v4f32: 747 define <8 x i16> @test_v8i16_v4f32(<4 x float> %p) { 748 ; CHECK: rev64 v{{[0-9]+}}.4s 749 ; CHECK: ext 750 ; CHECK: rev64 v{{[0-9]+}}.8h 751 ; CHECK: ext 752 %1 = fadd <4 x float> %p, %p 753 %2 = bitcast <4 x float> %1 to <8 x i16> 754 %3 = add <8 x i16> %2, %2 755 ret <8 x i16> %3 756 } 757 758 ; CHECK-LABEL: test_v8i16_v4i32: 759 define <8 x i16> @test_v8i16_v4i32(<4 x i32> %p) { 760 ; CHECK: rev64 v{{[0-9]+}}.4s 761 ; CHECK: ext 762 ; CHECK: rev64 v{{[0-9]+}}.8h 763 ; CHECK: ext 764 %1 = add <4 x i32> %p, %p 765 %2 = bitcast <4 x i32> %1 to <8 x i16> 766 %3 = add <8 x i16> %2, %2 767 ret <8 x i16> %3 768 } 769 770 ; CHECK-LABEL: test_v8i16_v16i8: 771 define <8 x i16> @test_v8i16_v16i8(<16 x i8> %p) { 772 ; CHECK: rev64 v{{[0-9]+}}.16b 773 ; CHECK: ext 774 ; CHECK: rev64 v{{[0-9]+}}.8h 775 ; CHECK: ext 776 %1 = add <16 x i8> %p, %p 777 %2 = bitcast <16 x i8> %1 to <8 x i16> 778 %3 = add <8 x i16> %2, %2 779 ret <8 x i16> %3 780 } 781 782 ; CHECK-LABEL: test_v16i8_f128: 783 define <16 x i8> @test_v16i8_f128(fp128 %p) { 784 ; CHECK: rev64 v{{[0-9]+}}.16b 785 ; CHECK: ext 786 %1 = fadd fp128 %p, %p 787 %2 = bitcast fp128 %1 to <16 x i8> 788 %3 = add <16 x i8> %2, %2 789 ret <16 x i8> %3 790 } 791 792 ; CHECK-LABEL: test_v16i8_v2f64: 793 define <16 x i8> @test_v16i8_v2f64(<2 x double> %p) { 794 ; CHECK: ext 795 ; CHECK: rev64 v{{[0-9]+}}.16b 796 ; CHECK: ext 797 %1 = fadd <2 x double> %p, %p 798 %2 = bitcast <2 x double> %1 to <16 x i8> 799 %3 = add <16 x i8> %2, %2 800 ret <16 x i8> %3 801 } 802 803 ; CHECK-LABEL: test_v16i8_v2i64: 804 define <16 x i8> @test_v16i8_v2i64(<2 x i64> %p) { 805 ; CHECK: ext 806 ; CHECK: rev64 v{{[0-9]+}}.16b 807 ; CHECK: ext 808 %1 = add <2 x i64> %p, %p 809 %2 = bitcast <2 x i64> %1 to <16 x i8> 810 %3 = add <16 x i8> %2, %2 811 ret <16 x i8> %3 812 } 813 814 ; CHECK-LABEL: test_v16i8_v4f32: 815 define <16 x i8> @test_v16i8_v4f32(<4 x float> %p) { 816 ; CHECK: rev64 v{{[0-9]+}}.4s 817 ; CHECK: ext 818 ; CHECK: rev64 v{{[0-9]+}}.16b 819 ; CHECK: ext 820 %1 = fadd <4 x float> %p, %p 821 %2 = bitcast <4 x float> %1 to <16 x i8> 822 %3 = add <16 x i8> %2, %2 823 ret <16 x i8> %3 824 } 825 826 ; CHECK-LABEL: test_v16i8_v4i32: 827 define <16 x i8> @test_v16i8_v4i32(<4 x i32> %p) { 828 ; CHECK: rev64 v{{[0-9]+}}.4s 829 ; CHECK: ext 830 ; CHECK: rev64 v{{[0-9]+}}.16b 831 ; CHECK: ext 832 %1 = add <4 x i32> %p, %p 833 %2 = bitcast <4 x i32> %1 to <16 x i8> 834 %3 = add <16 x i8> %2, %2 835 ret <16 x i8> %3 836 } 837 838 ; CHECK-LABEL: test_v16i8_v8i16: 839 define <16 x i8> @test_v16i8_v8i16(<8 x i16> %p) { 840 ; CHECK: rev64 v{{[0-9]+}}.8h 841 ; CHECK: ext 842 ; CHECK: rev64 v{{[0-9]+}}.16b 843 ; CHECK: ext 844 %1 = add <8 x i16> %p, %p 845 %2 = bitcast <8 x i16> %1 to <16 x i8> 846 %3 = add <16 x i8> %2, %2 847 ret <16 x i8> %3 848 } 849
