1 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math %s -o - \ 2 ; RUN: | FileCheck %s 3 4 ; rdar://7461510 5 ; rdar://10964603 6 7 ; Disable this optimization unless we know one of them is zero. 8 define arm_apcscc i32 @t1(float* %a, float* %b) nounwind { 9 entry: 10 ; CHECK-LABEL: t1: 11 ; CHECK: vldr [[S0:s[0-9]+]], 12 ; CHECK: vldr [[S1:s[0-9]+]], 13 ; CHECK: vcmpe.f32 [[S1]], [[S0]] 14 ; CHECK: vmrs APSR_nzcv, fpscr 15 ; CHECK: beq 16 %0 = load float* %a 17 %1 = load float* %b 18 %2 = fcmp une float %0, %1 19 br i1 %2, label %bb1, label %bb2 20 21 bb1: 22 %3 = call i32 @bar() 23 ret i32 %3 24 25 bb2: 26 %4 = call i32 @foo() 27 ret i32 %4 28 } 29 30 ; If one side is zero, the other size sign bit is masked off to allow 31 ; +0.0 == -0.0 32 define arm_apcscc i32 @t2(double* %a, double* %b) nounwind { 33 entry: 34 ; CHECK-LABEL: t2: 35 ; CHECK-NOT: vldr 36 ; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0] 37 ; CHECK-NOT: b LBB 38 ; CHECK: bfc [[REG2]], #31, #1 39 ; CHECK: cmp [[REG1]], #0 40 ; CHECK: cmpeq [[REG2]], #0 41 ; CHECK-NOT: vcmpe.f32 42 ; CHECK-NOT: vmrs 43 ; CHECK: bne 44 %0 = load double* %a 45 %1 = fcmp oeq double %0, 0.000000e+00 46 br i1 %1, label %bb1, label %bb2 47 48 bb1: 49 %2 = call i32 @bar() 50 ret i32 %2 51 52 bb2: 53 %3 = call i32 @foo() 54 ret i32 %3 55 } 56 57 define arm_apcscc i32 @t3(float* %a, float* %b) nounwind { 58 entry: 59 ; CHECK-LABEL: t3: 60 ; CHECK-NOT: vldr 61 ; CHECK: ldr [[REG3:(r[0-9]+)]], [r0] 62 ; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648 63 ; CHECK: tst [[REG3]], [[REG4]] 64 ; CHECK-NOT: vcmpe.f32 65 ; CHECK-NOT: vmrs 66 ; CHECK: bne 67 %0 = load float* %a 68 %1 = fcmp oeq float %0, 0.000000e+00 69 br i1 %1, label %bb1, label %bb2 70 71 bb1: 72 %2 = call i32 @bar() 73 ret i32 %2 74 75 bb2: 76 %3 = call i32 @foo() 77 ret i32 %3 78 } 79 80 declare i32 @bar() 81 declare i32 @foo() 82
