1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC 2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC 3 ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC 4 5 ; FUNC-LABEL: @u32_mad24 6 ; EG: MULADD_UINT24 7 ; SI: V_MAD_U32_U24 8 9 define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 10 entry: 11 %0 = shl i32 %a, 8 12 %a_24 = lshr i32 %0, 8 13 %1 = shl i32 %b, 8 14 %b_24 = lshr i32 %1, 8 15 %2 = mul i32 %a_24, %b_24 16 %3 = add i32 %2, %c 17 store i32 %3, i32 addrspace(1)* %out 18 ret void 19 } 20 21 ; FUNC-LABEL: @i16_mad24 22 ; The order of A and B does not matter. 23 ; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] 24 ; The result must be sign-extended 25 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x 26 ; EG: 16 27 ; SI: V_MAD_U32_U24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} 28 ; SI: V_BFE_I32 v{{[0-9]}}, [[MAD]], 0, 16 29 30 define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) { 31 entry: 32 %0 = mul i16 %a, %b 33 %1 = add i16 %0, %c 34 %2 = sext i16 %1 to i32 35 store i32 %2, i32 addrspace(1)* %out 36 ret void 37 } 38 39 ; FUNC-LABEL: @i8_mad24 40 ; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]] 41 ; The result must be sign-extended 42 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x 43 ; EG: 8 44 ; SI: V_MAD_U32_U24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} 45 ; SI: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 8 46 47 define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) { 48 entry: 49 %0 = mul i8 %a, %b 50 %1 = add i8 %0, %c 51 %2 = sext i8 %1 to i32 52 store i32 %2, i32 addrspace(1)* %out 53 ret void 54 } 55 56 ; This tests for a bug where the mad_u24 pattern matcher would call 57 ; SimplifyDemandedBits on the first operand of the mul instruction 58 ; assuming that the pattern would be matched to a 24-bit mad. This 59 ; led to some instructions being incorrectly erased when the entire 60 ; 24-bit mad pattern wasn't being matched. 61 62 ; Check that the select instruction is not deleted. 63 ; FUNC-LABEL: @i24_i32_i32_mad 64 ; EG: CNDE_INT 65 ; SI: V_CNDMASK 66 define void @i24_i32_i32_mad(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) { 67 entry: 68 %0 = ashr i32 %a, 8 69 %1 = icmp ne i32 %c, 0 70 %2 = select i1 %1, i32 %0, i32 34 71 %3 = mul i32 %2, %c 72 %4 = add i32 %3, %d 73 store i32 %4, i32 addrspace(1)* %out 74 ret void 75 } 76
