1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s 2 ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s 3 4 ;EG-CHECK: @lshr_v2i32 5 ;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 6 ;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 7 8 ;SI-CHECK: @lshr_v2i32 9 ;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 10 ;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 11 12 define void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 13 %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 14 %a = load <2 x i32> addrspace(1) * %in 15 %b = load <2 x i32> addrspace(1) * %b_ptr 16 %result = lshr <2 x i32> %a, %b 17 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 18 ret void 19 } 20 21 22 ;EG-CHECK: @lshr_v4i32 23 ;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 24 ;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 25 ;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 26 ;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 27 28 ;SI-CHECK: @lshr_v4i32 29 ;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 30 ;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 31 ;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 32 ;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 33 34 define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 35 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 36 %a = load <4 x i32> addrspace(1) * %in 37 %b = load <4 x i32> addrspace(1) * %b_ptr 38 %result = lshr <4 x i32> %a, %b 39 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 40 ret void 41 } 42 43 ;EG-CHECK: @lshr_i64 44 ;EG-CHECK: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] 45 ;EG-CHECK: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} 46 ;EG-CHECK: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 47 ;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 48 ;EG-CHECK-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]] 49 ;EG-CHECK-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}} 50 ;EG-CHECK-DAG: LSHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}} 51 ;EG-CHECK-DAG: LSHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}} 52 ;EG-CHECK-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 53 ;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} 54 ;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0 55 56 ;SI-CHECK: @lshr_i64 57 ;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 58 59 define void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 60 %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1 61 %a = load i64 addrspace(1) * %in 62 %b = load i64 addrspace(1) * %b_ptr 63 %result = lshr i64 %a, %b 64 store i64 %result, i64 addrspace(1)* %out 65 ret void 66 } 67 68 ;EG-CHECK: @lshr_v2i64 69 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 70 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 71 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]] 72 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]] 73 ;EG-CHECK-DAG: LSHL {{.*}}, 1 74 ;EG-CHECK-DAG: LSHL {{.*}}, 1 75 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]] 76 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]] 77 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]] 78 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]] 79 ;EG-CHECK-DAG: OR_INT 80 ;EG-CHECK-DAG: OR_INT 81 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 82 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 83 ;EG-CHECK-DAG: LSHR 84 ;EG-CHECK-DAG: LSHR 85 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 86 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 87 ;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0 88 ;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0 89 ;EG-CHECK-DAG: CNDE_INT 90 ;EG-CHECK-DAG: CNDE_INT 91 92 ;SI-CHECK: @lshr_v2i64 93 ;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 94 ;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 95 96 define void @lshr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { 97 %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1 98 %a = load <2 x i64> addrspace(1) * %in 99 %b = load <2 x i64> addrspace(1) * %b_ptr 100 %result = lshr <2 x i64> %a, %b 101 store <2 x i64> %result, <2 x i64> addrspace(1)* %out 102 ret void 103 } 104 105 106 ;EG-CHECK: @lshr_v4i64 107 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 108 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 109 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] 110 ;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] 111 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]] 112 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]] 113 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHC]] 114 ;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHD]] 115 ;EG-CHECK-DAG: LSHL {{.*}}, 1 116 ;EG-CHECK-DAG: LSHL {{.*}}, 1 117 ;EG-CHECK-DAG: LSHL {{.*}}, 1 118 ;EG-CHECK-DAG: LSHL {{.*}}, 1 119 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]] 120 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]] 121 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHC]] 122 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHD]] 123 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]] 124 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]] 125 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHC]] 126 ;EG-CHECK-DAG: LSHR {{.*}}, [[SHD]] 127 ;EG-CHECK-DAG: OR_INT 128 ;EG-CHECK-DAG: OR_INT 129 ;EG-CHECK-DAG: OR_INT 130 ;EG-CHECK-DAG: OR_INT 131 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 132 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 133 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal 134 ;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal 135 ;EG-CHECK-DAG: LSHR 136 ;EG-CHECK-DAG: LSHR 137 ;EG-CHECK-DAG: LSHR 138 ;EG-CHECK-DAG: LSHR 139 ;EG-CHECK-DAG: LSHR 140 ;EG-CHECK-DAG: LSHR 141 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 142 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 143 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal 144 ;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal 145 ;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0 146 ;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0 147 ;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0 148 ;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0 149 ;EG-CHECK-DAG: CNDE_INT 150 ;EG-CHECK-DAG: CNDE_INT 151 ;EG-CHECK-DAG: CNDE_INT 152 ;EG-CHECK-DAG: CNDE_INT 153 154 ;SI-CHECK: @lshr_v4i64 155 ;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 156 ;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 157 ;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 158 ;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 159 160 define void @lshr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { 161 %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1 162 %a = load <4 x i64> addrspace(1) * %in 163 %b = load <4 x i64> addrspace(1) * %b_ptr 164 %result = lshr <4 x i64> %a, %b 165 store <4 x i64> %result, <4 x i64> addrspace(1)* %out 166 ret void 167 } 168
