1 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 2 3 ; SI-LABEL: @uint_to_fp_f64_i32 4 ; SI: V_CVT_F64_U32_e32 5 ; SI: S_ENDPGM 6 define void @uint_to_fp_f64_i32(double addrspace(1)* %out, i32 %in) { 7 %cast = uitofp i32 %in to double 8 store double %cast, double addrspace(1)* %out, align 8 9 ret void 10 } 11 12 ; SI-LABEL: @uint_to_fp_i1_f64: 13 ; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], 14 ; FIXME: We should the VGPR sources for V_CNDMASK are copied from SGPRs, 15 ; we should be able to fold the SGPRs into the V_CNDMASK instructions. 16 ; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] 17 ; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]] 18 ; SI: BUFFER_STORE_DWORDX2 19 ; SI: S_ENDPGM 20 define void @uint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) { 21 %cmp = icmp eq i32 %in, 0 22 %fp = uitofp i1 %cmp to double 23 store double %fp, double addrspace(1)* %out, align 4 24 ret void 25 } 26 27 ; SI-LABEL: @uint_to_fp_i1_f64_load: 28 ; SI: V_CNDMASK_B32_e64 [[IRESULT:v[0-9]]], 0, 1 29 ; SI-NEXT: V_CVT_F64_U32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]] 30 ; SI: BUFFER_STORE_DWORDX2 [[RESULT]] 31 ; SI: S_ENDPGM 32 define void @uint_to_fp_i1_f64_load(double addrspace(1)* %out, i1 %in) { 33 %fp = uitofp i1 %in to double 34 store double %fp, double addrspace(1)* %out, align 8 35 ret void 36 } 37
