1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s 2 ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s 3 4 ;EG-CHECK: @xor_v2i32 5 ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 6 ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 7 8 ;SI-CHECK: @xor_v2i32 9 ;SI-CHECK: V_XOR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 10 ;SI-CHECK: V_XOR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 11 12 13 define void @xor_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) { 14 %a = load <2 x i32> addrspace(1) * %in0 15 %b = load <2 x i32> addrspace(1) * %in1 16 %result = xor <2 x i32> %a, %b 17 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 18 ret void 19 } 20 21 ;EG-CHECK: @xor_v4i32 22 ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 23 ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 24 ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 25 ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 26 27 ;SI-CHECK: @xor_v4i32 28 ;SI-CHECK: V_XOR_B32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} 29 ;SI-CHECK: V_XOR_B32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} 30 ;SI-CHECK: V_XOR_B32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} 31 ;SI-CHECK: V_XOR_B32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} 32 33 define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) { 34 %a = load <4 x i32> addrspace(1) * %in0 35 %b = load <4 x i32> addrspace(1) * %in1 36 %result = xor <4 x i32> %a, %b 37 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 38 ret void 39 } 40 41 ;EG-CHECK: @xor_i1 42 ;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}} 43 44 ;SI-CHECK: @xor_i1 45 ;SI-CHECK: S_XOR_B64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] 46 47 define void @xor_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) { 48 %a = load float addrspace(1) * %in0 49 %b = load float addrspace(1) * %in1 50 %acmp = fcmp oge float %a, 0.000000e+00 51 %bcmp = fcmp oge float %b, 0.000000e+00 52 %xor = xor i1 %acmp, %bcmp 53 %result = select i1 %xor, float %a, float %b 54 store float %result, float addrspace(1)* %out 55 ret void 56 } 57 58 ; SI-CHECK-LABEL: @vector_xor_i32 59 ; SI-CHECK: V_XOR_B32_e32 60 define void @vector_xor_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) { 61 %a = load i32 addrspace(1)* %in0 62 %b = load i32 addrspace(1)* %in1 63 %result = xor i32 %a, %b 64 store i32 %result, i32 addrspace(1)* %out 65 ret void 66 } 67 68 ; SI-CHECK-LABEL: @scalar_xor_i32 69 ; SI-CHECK: S_XOR_B32 70 define void @scalar_xor_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { 71 %result = xor i32 %a, %b 72 store i32 %result, i32 addrspace(1)* %out 73 ret void 74 } 75 76 ; SI-CHECK-LABEL: @scalar_not_i32 77 ; SI-CHECK: S_NOT_B32 78 define void @scalar_not_i32(i32 addrspace(1)* %out, i32 %a) { 79 %result = xor i32 %a, -1 80 store i32 %result, i32 addrspace(1)* %out 81 ret void 82 } 83 84 ; SI-CHECK-LABEL: @vector_not_i32 85 ; SI-CHECK: V_NOT_B32 86 define void @vector_not_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) { 87 %a = load i32 addrspace(1)* %in0 88 %b = load i32 addrspace(1)* %in1 89 %result = xor i32 %a, -1 90 store i32 %result, i32 addrspace(1)* %out 91 ret void 92 } 93 94 ; SI-CHECK-LABEL: @vector_xor_i64 95 ; SI-CHECK: V_XOR_B32_e32 96 ; SI-CHECK: V_XOR_B32_e32 97 ; SI-CHECK: S_ENDPGM 98 define void @vector_xor_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 addrspace(1)* %in1) { 99 %a = load i64 addrspace(1)* %in0 100 %b = load i64 addrspace(1)* %in1 101 %result = xor i64 %a, %b 102 store i64 %result, i64 addrspace(1)* %out 103 ret void 104 } 105 106 ; SI-CHECK-LABEL: @scalar_xor_i64 107 ; SI-CHECK: S_XOR_B64 108 ; SI-CHECK: S_ENDPGM 109 define void @scalar_xor_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { 110 %result = xor i64 %a, %b 111 store i64 %result, i64 addrspace(1)* %out 112 ret void 113 } 114 115 ; SI-CHECK-LABEL: @scalar_not_i64 116 ; SI-CHECK: S_NOT_B64 117 define void @scalar_not_i64(i64 addrspace(1)* %out, i64 %a) { 118 %result = xor i64 %a, -1 119 store i64 %result, i64 addrspace(1)* %out 120 ret void 121 } 122 123 ; SI-CHECK-LABEL: @vector_not_i64 124 ; SI-CHECK: V_NOT_B32 125 ; SI-CHECK: V_NOT_B32 126 define void @vector_not_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 addrspace(1)* %in1) { 127 %a = load i64 addrspace(1)* %in0 128 %b = load i64 addrspace(1)* %in1 129 %result = xor i64 %a, -1 130 store i64 %result, i64 addrspace(1)* %out 131 ret void 132 } 133 134 ; Test that we have a pattern to match xor inside a branch. 135 ; Note that in the future the backend may be smart enough to 136 ; use an SALU instruction for this. 137 138 ; SI-CHECK-LABEL: @xor_cf 139 ; SI-CHECK: V_XOR 140 ; SI-CHECK: V_XOR 141 define void @xor_cf(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b) { 142 entry: 143 %0 = icmp eq i64 %a, 0 144 br i1 %0, label %if, label %else 145 146 if: 147 %1 = xor i64 %a, %b 148 br label %endif 149 150 else: 151 %2 = load i64 addrspace(1)* %in 152 br label %endif 153 154 endif: 155 %3 = phi i64 [%1, %if], [%2, %else] 156 store i64 %3, i64 addrspace(1)* %out 157 ret void 158 } 159
