1 ; RUN: llc < %s -march=sparcv9 | FileCheck %s 2 3 target datalayout = "E-i64:64-n32:64-S128" 4 target triple = "sparc64-sun-sparc" 5 6 ; CHECK-LABEL: test_and_spill 7 ; CHECK: and %i0, %i1, [[R:%[gilo][0-7]]] 8 ; CHECK: stx [[R]], [%fp+{{.+}}] 9 ; CHECK: ldx [%fp+{{.+}}, %i0 10 define i64 @test_and_spill(i64 %a, i64 %b) { 11 entry: 12 %r0 = and i64 %a, %b 13 %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0) 14 ret i64 %r0 15 } 16 17 ; CHECK-LABEL: test_or_spill 18 ; CHECK: or %i0, %i1, [[R:%[gilo][0-7]]] 19 ; CHECK: stx [[R]], [%fp+{{.+}}] 20 ; CHECK: ldx [%fp+{{.+}}, %i0 21 define i64 @test_or_spill(i64 %a, i64 %b) { 22 entry: 23 %r0 = or i64 %a, %b 24 %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0) 25 ret i64 %r0 26 } 27 28 ; CHECK-LABEL: test_xor_spill 29 ; CHECK: xor %i0, %i1, [[R:%[gilo][0-7]]] 30 ; CHECK: stx [[R]], [%fp+{{.+}}] 31 ; CHECK: ldx [%fp+{{.+}}, %i0 32 define i64 @test_xor_spill(i64 %a, i64 %b) { 33 entry: 34 %r0 = xor i64 %a, %b 35 %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0) 36 ret i64 %r0 37 } 38 39 40 ; CHECK-LABEL: test_add_spill 41 ; CHECK: add %i0, %i1, [[R:%[gilo][0-7]]] 42 ; CHECK: stx [[R]], [%fp+{{.+}}] 43 ; CHECK: ldx [%fp+{{.+}}, %i0 44 define i64 @test_add_spill(i64 %a, i64 %b) { 45 entry: 46 %r0 = add i64 %a, %b 47 %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0) 48 ret i64 %r0 49 } 50 51 ; CHECK-LABEL: test_sub_spill 52 ; CHECK: sub %i0, %i1, [[R:%[gilo][0-7]]] 53 ; CHECK: stx [[R]], [%fp+{{.+}}] 54 ; CHECK: ldx [%fp+{{.+}}, %i0 55 define i64 @test_sub_spill(i64 %a, i64 %b) { 56 entry: 57 %r0 = sub i64 %a, %b 58 %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0) 59 ret i64 %r0 60 } 61 62 ; CHECK-LABEL: test_andi_spill 63 ; CHECK: and %i0, 1729, [[R:%[gilo][0-7]]] 64 ; CHECK: stx [[R]], [%fp+{{.+}}] 65 ; CHECK: ldx [%fp+{{.+}}, %i0 66 define i64 @test_andi_spill(i64 %a) { 67 entry: 68 %r0 = and i64 %a, 1729 69 %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0) 70 ret i64 %r0 71 } 72 73 ; CHECK-LABEL: test_ori_spill 74 ; CHECK: or %i0, 1729, [[R:%[gilo][0-7]]] 75 ; CHECK: stx [[R]], [%fp+{{.+}}] 76 ; CHECK: ldx [%fp+{{.+}}, %i0 77 define i64 @test_ori_spill(i64 %a) { 78 entry: 79 %r0 = or i64 %a, 1729 80 %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0) 81 ret i64 %r0 82 } 83 84 ; CHECK-LABEL: test_xori_spill 85 ; CHECK: xor %i0, 1729, [[R:%[gilo][0-7]]] 86 ; CHECK: stx [[R]], [%fp+{{.+}}] 87 ; CHECK: ldx [%fp+{{.+}}, %i0 88 define i64 @test_xori_spill(i64 %a) { 89 entry: 90 %r0 = xor i64 %a, 1729 91 %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0) 92 ret i64 %r0 93 } 94 95 ; CHECK-LABEL: test_addi_spill 96 ; CHECK: add %i0, 1729, [[R:%[gilo][0-7]]] 97 ; CHECK: stx [[R]], [%fp+{{.+}}] 98 ; CHECK: ldx [%fp+{{.+}}, %i0 99 define i64 @test_addi_spill(i64 %a) { 100 entry: 101 %r0 = add i64 %a, 1729 102 %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0) 103 ret i64 %r0 104 } 105 106 ; CHECK-LABEL: test_subi_spill 107 ; CHECK: add %i0, -1729, [[R:%[gilo][0-7]]] 108 ; CHECK: stx [[R]], [%fp+{{.+}}] 109 ; CHECK: ldx [%fp+{{.+}}, %i0 110 define i64 @test_subi_spill(i64 %a) { 111 entry: 112 %r0 = sub i64 %a, 1729 113 %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0) 114 ret i64 %r0 115 } 116 117
