1 /* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude (at) gmail.com> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 22 23 #ifndef R300_CHIPSET_H 24 #define R300_CHIPSET_H 25 26 #include "pipe/p_compiler.h" 27 28 /* these are sizes in dwords */ 29 #define R300_HIZ_LIMIT 10240 30 #define RV530_HIZ_LIMIT 15360 31 32 /* rv3xx have only one pipe */ 33 #define PIPE_ZMASK_SIZE 4096 34 #define RV3xx_ZMASK_SIZE 5120 35 36 /* The size of a compressed tile. Each compressed tile takes 2 bits 37 * in the ZMASK RAM, so there is always 16 tiles per one dword. */ 38 enum r300_zmask_compression { 39 R300_ZCOMP_4X4 = 4, 40 R300_ZCOMP_8X8 = 8 41 }; 42 43 /* Structure containing all the possible information about a specific Radeon 44 * in the R3xx, R4xx, and R5xx families. */ 45 struct r300_capabilities { 46 /* Chipset family */ 47 int family; 48 /* The number of vertex floating-point units */ 49 unsigned num_vert_fpus; 50 /* The number of texture units. */ 51 unsigned num_tex_units; 52 /* Whether or not TCL is physically present */ 53 boolean has_tcl; 54 /* Some chipsets do not have HiZ RAM - other have varying amounts. */ 55 int hiz_ram; 56 /* Some chipsets have zmask ram per pipe some don't. */ 57 int zmask_ram; 58 /* Compression mode for ZMASK. */ 59 enum r300_zmask_compression z_compress; 60 /* Whether or not this is RV350 or newer, including all r400 and r500 61 * chipsets. The differences compared to the oldest r300 chips are: 62 * - Blend LTE/GTE thresholds 63 * - Better MACRO_SWITCH in texture tiling 64 * - Half float vertex 65 * - More HyperZ optimizations */ 66 boolean is_rv350; 67 /* Whether or not this is R400. The differences compared their rv350 68 * cousins are: 69 * - Extended fragment shader registers 70 * - 3DC texture compression (RGTC2) */ 71 boolean is_r400; 72 /* Whether or not this is an RV515 or newer; R500s have many differences 73 * that require extra consideration, compared to their rv350 cousins: 74 * - Extra bit of width and height on texture sizes 75 * - Blend color is split across two registers 76 * - Universal Shader (US) block used for fragment shaders 77 * - FP16 blending and multisampling 78 * - Full RGTC texture compression 79 * - 24-bit depth textures 80 * - Stencil back-face reference value 81 * - Ability to render up to 2^24 - 1 vertices with signed index offset */ 82 boolean is_r500; 83 /* Whether or not the second pixel pipe is accessed with the high bit */ 84 boolean high_second_pipe; 85 /* DXTC texture swizzling. */ 86 boolean dxtc_swizzle; 87 /* Whether R500_US_FORMAT0_0 exists (R520-only and depends on DRM). */ 88 boolean has_us_format; 89 }; 90 91 /* Enumerations for legibility and telling which card we're running on. */ 92 enum { 93 CHIP_FAMILY_R300 = 0, /* R3xx-based cores. */ 94 CHIP_FAMILY_R350, 95 CHIP_FAMILY_RV350, 96 CHIP_FAMILY_RV370, 97 CHIP_FAMILY_RV380, 98 CHIP_FAMILY_RS400, 99 CHIP_FAMILY_RC410, 100 CHIP_FAMILY_RS480, 101 CHIP_FAMILY_R420, /* R4xx-based cores. */ 102 CHIP_FAMILY_R423, 103 CHIP_FAMILY_R430, 104 CHIP_FAMILY_R480, 105 CHIP_FAMILY_R481, 106 CHIP_FAMILY_RV410, 107 CHIP_FAMILY_RS600, 108 CHIP_FAMILY_RS690, 109 CHIP_FAMILY_RS740, 110 CHIP_FAMILY_RV515, /* R5xx-based cores. */ 111 CHIP_FAMILY_R520, 112 CHIP_FAMILY_RV530, 113 CHIP_FAMILY_R580, 114 CHIP_FAMILY_RV560, 115 CHIP_FAMILY_RV570 116 }; 117 118 void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps); 119 120 #endif /* R300_CHIPSET_H */ 121
