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      1 /*
      2  * Tiny Code Generator for QEMU
      3  *
      4  * Copyright (c) 2008 Fabrice Bellard
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a copy
      7  * of this software and associated documentation files (the "Software"), to deal
      8  * in the Software without restriction, including without limitation the rights
      9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10  * copies of the Software, and to permit persons to whom the Software is
     11  * furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22  * THE SOFTWARE.
     23  */
     24 
     25 /*
     26  * DEF(name, oargs, iargs, cargs, flags)
     27  */
     28 
     29 /* predefined ops */
     30 DEF(end, 0, 0, 0, TCG_OPF_NOT_PRESENT) /* must be kept first */
     31 DEF(nop, 0, 0, 0, TCG_OPF_NOT_PRESENT)
     32 DEF(nop1, 0, 0, 1, TCG_OPF_NOT_PRESENT)
     33 DEF(nop2, 0, 0, 2, TCG_OPF_NOT_PRESENT)
     34 DEF(nop3, 0, 0, 3, TCG_OPF_NOT_PRESENT)
     35 
     36 /* variable number of parameters */
     37 DEF(nopn, 0, 0, 1, TCG_OPF_NOT_PRESENT)
     38 
     39 DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
     40 DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
     41 
     42 /* variable number of parameters */
     43 DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER)
     44 
     45 DEF(br, 0, 0, 1, TCG_OPF_BB_END)
     46 
     47 #define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
     48 #if TCG_TARGET_REG_BITS == 32
     49 # define IMPL64  TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
     50 #else
     51 # define IMPL64  TCG_OPF_64BIT
     52 #endif
     53 
     54 DEF(mov_i32, 1, 1, 0, 0)
     55 DEF(movi_i32, 1, 0, 1, 0)
     56 DEF(setcond_i32, 1, 2, 1, 0)
     57 DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
     58 /* load/store */
     59 DEF(ld8u_i32, 1, 1, 1, 0)
     60 DEF(ld8s_i32, 1, 1, 1, 0)
     61 DEF(ld16u_i32, 1, 1, 1, 0)
     62 DEF(ld16s_i32, 1, 1, 1, 0)
     63 DEF(ld_i32, 1, 1, 1, 0)
     64 DEF(st8_i32, 0, 2, 1, 0)
     65 DEF(st16_i32, 0, 2, 1, 0)
     66 DEF(st_i32, 0, 2, 1, 0)
     67 /* arith */
     68 DEF(add_i32, 1, 2, 0, 0)
     69 DEF(sub_i32, 1, 2, 0, 0)
     70 DEF(mul_i32, 1, 2, 0, 0)
     71 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
     72 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
     73 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
     74 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
     75 DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
     76 DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
     77 DEF(and_i32, 1, 2, 0, 0)
     78 DEF(or_i32, 1, 2, 0, 0)
     79 DEF(xor_i32, 1, 2, 0, 0)
     80 /* shifts/rotates */
     81 DEF(shl_i32, 1, 2, 0, 0)
     82 DEF(shr_i32, 1, 2, 0, 0)
     83 DEF(sar_i32, 1, 2, 0, 0)
     84 DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
     85 DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
     86 DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
     87 
     88 DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
     89 
     90 DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
     91 DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
     92 DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
     93 DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
     94 DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
     95 DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
     96 DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
     97 DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
     98 
     99 DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
    100 DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
    101 DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
    102 DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
    103 DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
    104 DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
    105 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
    106 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
    107 DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
    108 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
    109 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
    110 DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
    111 DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
    112 
    113 DEF(mov_i64, 1, 1, 0, IMPL64)
    114 DEF(movi_i64, 1, 0, 1, IMPL64)
    115 DEF(setcond_i64, 1, 2, 1, IMPL64)
    116 DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
    117 /* load/store */
    118 DEF(ld8u_i64, 1, 1, 1, IMPL64)
    119 DEF(ld8s_i64, 1, 1, 1, IMPL64)
    120 DEF(ld16u_i64, 1, 1, 1, IMPL64)
    121 DEF(ld16s_i64, 1, 1, 1, IMPL64)
    122 DEF(ld32u_i64, 1, 1, 1, IMPL64)
    123 DEF(ld32s_i64, 1, 1, 1, IMPL64)
    124 DEF(ld_i64, 1, 1, 1, IMPL64)
    125 DEF(st8_i64, 0, 2, 1, IMPL64)
    126 DEF(st16_i64, 0, 2, 1, IMPL64)
    127 DEF(st32_i64, 0, 2, 1, IMPL64)
    128 DEF(st_i64, 0, 2, 1, IMPL64)
    129 /* arith */
    130 DEF(add_i64, 1, 2, 0, IMPL64)
    131 DEF(sub_i64, 1, 2, 0, IMPL64)
    132 DEF(mul_i64, 1, 2, 0, IMPL64)
    133 DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
    134 DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
    135 DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
    136 DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
    137 DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
    138 DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
    139 DEF(and_i64, 1, 2, 0, IMPL64)
    140 DEF(or_i64, 1, 2, 0, IMPL64)
    141 DEF(xor_i64, 1, 2, 0, IMPL64)
    142 /* shifts/rotates */
    143 DEF(shl_i64, 1, 2, 0, IMPL64)
    144 DEF(shr_i64, 1, 2, 0, IMPL64)
    145 DEF(sar_i64, 1, 2, 0, IMPL64)
    146 DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
    147 DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
    148 DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
    149 
    150 DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
    151 DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
    152 DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
    153 DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
    154 DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
    155 DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
    156 DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
    157 DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
    158 DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
    159 DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
    160 DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
    161 DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
    162 DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
    163 DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
    164 DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
    165 DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
    166 DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
    167 
    168 DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
    169 DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
    170 DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
    171 DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
    172 DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64))
    173 DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
    174 
    175 /* QEMU specific */
    176 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
    177 DEF(debug_insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
    178 #else
    179 DEF(debug_insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
    180 #endif
    181 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
    182 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
    183 
    184 #define IMPL_NEW_LDST \
    185     (TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS \
    186      | IMPL(TCG_TARGET_HAS_new_ldst))
    187 
    188 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
    189 DEF(qemu_ld_i32, 1, 1, 2, IMPL_NEW_LDST)
    190 DEF(qemu_st_i32, 0, 2, 2, IMPL_NEW_LDST)
    191 # if TCG_TARGET_REG_BITS == 64
    192 DEF(qemu_ld_i64, 1, 1, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
    193 DEF(qemu_st_i64, 0, 2, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
    194 # else
    195 DEF(qemu_ld_i64, 2, 1, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
    196 DEF(qemu_st_i64, 0, 3, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
    197 # endif
    198 #else
    199 DEF(qemu_ld_i32, 1, 2, 2, IMPL_NEW_LDST)
    200 DEF(qemu_st_i32, 0, 3, 2, IMPL_NEW_LDST)
    201 DEF(qemu_ld_i64, 2, 2, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
    202 DEF(qemu_st_i64, 0, 4, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
    203 #endif
    204 
    205 #undef IMPL_NEW_LDST
    206 
    207 #define IMPL_OLD_LDST \
    208     (TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS \
    209      | IMPL(!TCG_TARGET_HAS_new_ldst))
    210 
    211 #if TCG_TARGET_REG_BITS == 32
    212 #if TARGET_LONG_BITS == 32
    213 DEF(qemu_ld8u, 1, 1, 1, IMPL_OLD_LDST)
    214 #else
    215 DEF(qemu_ld8u, 1, 2, 1, IMPL_OLD_LDST)
    216 #endif
    217 #if TARGET_LONG_BITS == 32
    218 DEF(qemu_ld8s, 1, 1, 1, IMPL_OLD_LDST)
    219 #else
    220 DEF(qemu_ld8s, 1, 2, 1, IMPL_OLD_LDST)
    221 #endif
    222 #if TARGET_LONG_BITS == 32
    223 DEF(qemu_ld16u, 1, 1, 1, IMPL_OLD_LDST)
    224 #else
    225 DEF(qemu_ld16u, 1, 2, 1, IMPL_OLD_LDST)
    226 #endif
    227 #if TARGET_LONG_BITS == 32
    228 DEF(qemu_ld16s, 1, 1, 1, IMPL_OLD_LDST)
    229 #else
    230 DEF(qemu_ld16s, 1, 2, 1, IMPL_OLD_LDST)
    231 #endif
    232 #if TARGET_LONG_BITS == 32
    233 DEF(qemu_ld32, 1, 1, 1, IMPL_OLD_LDST)
    234 #else
    235 DEF(qemu_ld32, 1, 2, 1, IMPL_OLD_LDST)
    236 #endif
    237 #if TARGET_LONG_BITS == 32
    238 DEF(qemu_ld64, 2, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    239 #else
    240 DEF(qemu_ld64, 2, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    241 #endif
    242 
    243 #if TARGET_LONG_BITS == 32
    244 DEF(qemu_st8, 0, 2, 1, IMPL_OLD_LDST)
    245 #else
    246 DEF(qemu_st8, 0, 3, 1, IMPL_OLD_LDST)
    247 #endif
    248 #if TARGET_LONG_BITS == 32
    249 DEF(qemu_st16, 0, 2, 1, IMPL_OLD_LDST)
    250 #else
    251 DEF(qemu_st16, 0, 3, 1, IMPL_OLD_LDST)
    252 #endif
    253 #if TARGET_LONG_BITS == 32
    254 DEF(qemu_st32, 0, 2, 1, IMPL_OLD_LDST)
    255 #else
    256 DEF(qemu_st32, 0, 3, 1, IMPL_OLD_LDST)
    257 #endif
    258 #if TARGET_LONG_BITS == 32
    259 DEF(qemu_st64, 0, 3, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    260 #else
    261 DEF(qemu_st64, 0, 4, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    262 #endif
    263 
    264 #else /* TCG_TARGET_REG_BITS == 32 */
    265 
    266 DEF(qemu_ld8u, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    267 DEF(qemu_ld8s, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    268 DEF(qemu_ld16u, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    269 DEF(qemu_ld16s, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    270 DEF(qemu_ld32, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    271 DEF(qemu_ld32u, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    272 DEF(qemu_ld32s, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    273 DEF(qemu_ld64, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    274 
    275 DEF(qemu_st8, 0, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    276 DEF(qemu_st16, 0, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    277 DEF(qemu_st32, 0, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    278 DEF(qemu_st64, 0, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
    279 
    280 #endif /* TCG_TARGET_REG_BITS != 32 */
    281 
    282 #undef IMPL_OLD_LDST
    283 
    284 #undef IMPL
    285 #undef IMPL64
    286 #undef DEF
    287