1 VIXL Supported Instruction List 2 =============================== 3 4 This is a list of the AArch64 instructions supported by the VIXL assembler, 5 disassembler and simulator. The simulator may not support all floating point 6 operations to the precision required by AArch64 - please check the simulator 7 source code for details. 8 9 AArch64 integer instructions 10 ---------------------------- 11 12 ### adc ### 13 14 Add with carry bit. 15 16 void adc(const Register& rd, 17 const Register& rn, 18 const Operand& operand) 19 20 21 ### adcs ### 22 23 Add with carry bit and update status flags. 24 25 void adcs(const Register& rd, 26 const Register& rn, 27 const Operand& operand) 28 29 30 ### add ### 31 32 Add. 33 34 void add(const Register& rd, 35 const Register& rn, 36 const Operand& operand) 37 38 39 ### adds ### 40 41 Add and update status flags. 42 43 void adds(const Register& rd, 44 const Register& rn, 45 const Operand& operand) 46 47 48 ### adr ### 49 50 Calculate the address of a PC offset. 51 52 void adr(const Register& rd, int imm21) 53 54 55 ### adr ### 56 57 Calculate the address of a label. 58 59 void adr(const Register& rd, Label* label) 60 61 62 ### and ### 63 64 Bitwise and (A & B). 65 66 void and_(const Register& rd, 67 const Register& rn, 68 const Operand& operand) 69 70 71 ### ands ### 72 73 Bitwise and (A & B) and update status flags. 74 75 void ands(const Register& rd, 76 const Register& rn, 77 const Operand& operand) 78 79 80 ### asr ### 81 82 Arithmetic shift right. 83 84 inline void asr(const Register& rd, const Register& rn, unsigned shift) 85 86 87 ### asrv ### 88 89 Arithmetic shift right by variable. 90 91 void asrv(const Register& rd, const Register& rn, const Register& rm) 92 93 94 ### b ### 95 96 Conditional branch to PC offset. 97 98 void b(int imm19, Condition cond) 99 100 101 ### b ### 102 103 Conditional branch to label. 104 105 void b(Label* label, Condition cond) 106 107 108 ### b ### 109 110 Unconditional branch to PC offset. 111 112 void b(int imm26) 113 114 115 ### b ### 116 117 Unconditional branch to label. 118 119 void b(Label* label) 120 121 122 ### bfi ### 123 124 Bitfield insert. 125 126 inline void bfi(const Register& rd, 127 const Register& rn, 128 unsigned lsb, 129 unsigned width) 130 131 132 ### bfm ### 133 134 Bitfield move. 135 136 void bfm(const Register& rd, 137 const Register& rn, 138 unsigned immr, 139 unsigned imms) 140 141 142 ### bfxil ### 143 144 Bitfield extract and insert low. 145 146 inline void bfxil(const Register& rd, 147 const Register& rn, 148 unsigned lsb, 149 unsigned width) 150 151 152 ### bic ### 153 154 Bit clear (A & ~B). 155 156 void bic(const Register& rd, 157 const Register& rn, 158 const Operand& operand) 159 160 161 ### bics ### 162 163 Bit clear (A & ~B) and update status flags. 164 165 void bics(const Register& rd, 166 const Register& rn, 167 const Operand& operand) 168 169 170 ### bl ### 171 172 Branch with link to PC offset. 173 174 void bl(int imm26) 175 176 177 ### bl ### 178 179 Branch with link to label. 180 181 void bl(Label* label) 182 183 184 ### blr ### 185 186 Branch with link to register. 187 188 void blr(const Register& xn) 189 190 191 ### br ### 192 193 Branch to register. 194 195 void br(const Register& xn) 196 197 198 ### brk ### 199 200 Monitor debug-mode breakpoint. 201 202 void brk(int code) 203 204 205 ### cbnz ### 206 207 Compare and branch to PC offset if not zero. 208 209 void cbnz(const Register& rt, int imm19) 210 211 212 ### cbnz ### 213 214 Compare and branch to label if not zero. 215 216 void cbnz(const Register& rt, Label* label) 217 218 219 ### cbz ### 220 221 Compare and branch to PC offset if zero. 222 223 void cbz(const Register& rt, int imm19) 224 225 226 ### cbz ### 227 228 Compare and branch to label if zero. 229 230 void cbz(const Register& rt, Label* label) 231 232 233 ### ccmn ### 234 235 Conditional compare negative. 236 237 void ccmn(const Register& rn, 238 const Operand& operand, 239 StatusFlags nzcv, 240 Condition cond) 241 242 243 ### ccmp ### 244 245 Conditional compare. 246 247 void ccmp(const Register& rn, 248 const Operand& operand, 249 StatusFlags nzcv, 250 Condition cond) 251 252 253 ### cinc ### 254 255 Conditional increment: rd = cond ? rn + 1 : rn. 256 257 void cinc(const Register& rd, const Register& rn, Condition cond) 258 259 260 ### cinv ### 261 262 Conditional invert: rd = cond ? ~rn : rn. 263 264 void cinv(const Register& rd, const Register& rn, Condition cond) 265 266 267 ### cls ### 268 269 Count leading sign bits. 270 271 void cls(const Register& rd, const Register& rn) 272 273 274 ### clz ### 275 276 Count leading zeroes. 277 278 void clz(const Register& rd, const Register& rn) 279 280 281 ### cmn ### 282 283 Compare negative. 284 285 void cmn(const Register& rn, const Operand& operand) 286 287 288 ### cmp ### 289 290 Compare. 291 292 void cmp(const Register& rn, const Operand& operand) 293 294 295 ### cneg ### 296 297 Conditional negate: rd = cond ? -rn : rn. 298 299 void cneg(const Register& rd, const Register& rn, Condition cond) 300 301 302 ### csel ### 303 304 Conditional select: rd = cond ? rn : rm. 305 306 void csel(const Register& rd, 307 const Register& rn, 308 const Register& rm, 309 Condition cond) 310 311 312 ### cset ### 313 314 Conditional set: rd = cond ? 1 : 0. 315 316 void cset(const Register& rd, Condition cond) 317 318 319 ### csetm ### 320 321 Conditional set mask: rd = cond ? -1 : 0. 322 323 void csetm(const Register& rd, Condition cond) 324 325 326 ### csinc ### 327 328 Conditional select increment: rd = cond ? rn : rm + 1. 329 330 void csinc(const Register& rd, 331 const Register& rn, 332 const Register& rm, 333 Condition cond) 334 335 336 ### csinv ### 337 338 Conditional select inversion: rd = cond ? rn : ~rm. 339 340 void csinv(const Register& rd, 341 const Register& rn, 342 const Register& rm, 343 Condition cond) 344 345 346 ### csneg ### 347 348 Conditional select negation: rd = cond ? rn : -rm. 349 350 void csneg(const Register& rd, 351 const Register& rn, 352 const Register& rm, 353 Condition cond) 354 355 356 ### dmb ### 357 358 Data memory barrier. 359 360 void dmb(BarrierDomain domain, BarrierType type) 361 362 363 ### dsb ### 364 365 Data synchronization barrier. 366 367 void dsb(BarrierDomain domain, BarrierType type) 368 369 370 ### eon ### 371 372 Bitwise enor/xnor (A ^ ~B). 373 374 void eon(const Register& rd, const Register& rn, const Operand& operand) 375 376 377 ### eor ### 378 379 Bitwise eor/xor (A ^ B). 380 381 void eor(const Register& rd, const Register& rn, const Operand& operand) 382 383 384 ### extr ### 385 386 Extract. 387 388 void extr(const Register& rd, 389 const Register& rn, 390 const Register& rm, 391 unsigned lsb) 392 393 394 ### hint ### 395 396 System hint. 397 398 void hint(SystemHint code) 399 400 401 ### hlt ### 402 403 Halting debug-mode breakpoint. 404 405 void hlt(int code) 406 407 408 ### isb ### 409 410 Instruction synchronization barrier. 411 412 void isb() 413 414 415 ### ldnp ### 416 417 Load integer or FP register pair, non-temporal. 418 419 void ldnp(const CPURegister& rt, const CPURegister& rt2, 420 const MemOperand& src) 421 422 423 ### ldp ### 424 425 Load integer or FP register pair. 426 427 void ldp(const CPURegister& rt, const CPURegister& rt2, 428 const MemOperand& src) 429 430 431 ### ldpsw ### 432 433 Load word pair with sign extension. 434 435 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src) 436 437 438 ### ldr ### 439 440 Load double precision floating point literal to FP register. 441 442 void ldr(const FPRegister& ft, double imm) 443 444 445 ### ldr ### 446 447 Load integer or FP register. 448 449 void ldr(const CPURegister& rt, const MemOperand& src) 450 451 452 ### ldr ### 453 454 Load literal to register. 455 456 void ldr(const Register& rt, uint64_t imm) 457 458 459 ### ldr ### 460 461 Load single precision floating point literal to FP register. 462 463 void ldr(const FPRegister& ft, float imm) 464 465 466 ### ldrb ### 467 468 Load byte. 469 470 void ldrb(const Register& rt, const MemOperand& src) 471 472 473 ### ldrh ### 474 475 Load half-word. 476 477 void ldrh(const Register& rt, const MemOperand& src) 478 479 480 ### ldrsb ### 481 482 Load byte with sign extension. 483 484 void ldrsb(const Register& rt, const MemOperand& src) 485 486 487 ### ldrsh ### 488 489 Load half-word with sign extension. 490 491 void ldrsh(const Register& rt, const MemOperand& src) 492 493 494 ### ldrsw ### 495 496 Load word with sign extension. 497 498 void ldrsw(const Register& rt, const MemOperand& src) 499 500 501 ### lsl ### 502 503 Logical shift left. 504 505 inline void lsl(const Register& rd, const Register& rn, unsigned shift) 506 507 508 ### lslv ### 509 510 Logical shift left by variable. 511 512 void lslv(const Register& rd, const Register& rn, const Register& rm) 513 514 515 ### lsr ### 516 517 Logical shift right. 518 519 inline void lsr(const Register& rd, const Register& rn, unsigned shift) 520 521 522 ### lsrv ### 523 524 Logical shift right by variable. 525 526 void lsrv(const Register& rd, const Register& rn, const Register& rm) 527 528 529 ### madd ### 530 531 Multiply and accumulate. 532 533 void madd(const Register& rd, 534 const Register& rn, 535 const Register& rm, 536 const Register& ra) 537 538 539 ### mneg ### 540 541 Negated multiply. 542 543 void mneg(const Register& rd, const Register& rn, const Register& rm) 544 545 546 ### mov ### 547 548 Move register to register. 549 550 void mov(const Register& rd, const Register& rn) 551 552 553 ### movk ### 554 555 Move immediate and keep. 556 557 void movk(const Register& rd, uint64_t imm, int shift = -1) 558 559 560 ### movn ### 561 562 Move inverted immediate. 563 564 void movn(const Register& rd, uint64_t imm, int shift = -1) 565 566 567 ### movz ### 568 569 Move immediate. 570 571 void movz(const Register& rd, uint64_t imm, int shift = -1) 572 573 574 ### mrs ### 575 576 Move to register from system register. 577 578 void mrs(const Register& rt, SystemRegister sysreg) 579 580 581 ### msr ### 582 583 Move from register to system register. 584 585 void msr(SystemRegister sysreg, const Register& rt) 586 587 588 ### msub ### 589 590 Multiply and subtract. 591 592 void msub(const Register& rd, 593 const Register& rn, 594 const Register& rm, 595 const Register& ra) 596 597 598 ### mul ### 599 600 Multiply. 601 602 void mul(const Register& rd, const Register& rn, const Register& rm) 603 604 605 ### mvn ### 606 607 Move inverted operand to register. 608 609 void mvn(const Register& rd, const Operand& operand) 610 611 612 ### neg ### 613 614 Negate. 615 616 void neg(const Register& rd, 617 const Operand& operand) 618 619 620 ### negs ### 621 622 Negate and update status flags. 623 624 void negs(const Register& rd, 625 const Operand& operand) 626 627 628 ### ngc ### 629 630 Negate with carry bit. 631 632 void ngc(const Register& rd, 633 const Operand& operand) 634 635 636 ### ngcs ### 637 638 Negate with carry bit and update status flags. 639 640 void ngcs(const Register& rd, 641 const Operand& operand) 642 643 644 ### nop ### 645 646 No-op. 647 648 void nop() 649 650 651 ### orn ### 652 653 Bitwise nor (A | ~B). 654 655 void orn(const Register& rd, const Register& rn, const Operand& operand) 656 657 658 ### orr ### 659 660 Bitwise or (A | B). 661 662 void orr(const Register& rd, const Register& rn, const Operand& operand) 663 664 665 ### rbit ### 666 667 Bit reverse. 668 669 void rbit(const Register& rd, const Register& rn) 670 671 672 ### ret ### 673 674 Branch to register with return hint. 675 676 void ret(const Register& xn = lr) 677 678 679 ### rev ### 680 681 Reverse bytes. 682 683 void rev(const Register& rd, const Register& rn) 684 685 686 ### rev16 ### 687 688 Reverse bytes in 16-bit half words. 689 690 void rev16(const Register& rd, const Register& rn) 691 692 693 ### rev32 ### 694 695 Reverse bytes in 32-bit words. 696 697 void rev32(const Register& rd, const Register& rn) 698 699 700 ### ror ### 701 702 Rotate right. 703 704 inline void ror(const Register& rd, const Register& rs, unsigned shift) 705 706 707 ### rorv ### 708 709 Rotate right by variable. 710 711 void rorv(const Register& rd, const Register& rn, const Register& rm) 712 713 714 ### sbc ### 715 716 Subtract with carry bit. 717 718 void sbc(const Register& rd, 719 const Register& rn, 720 const Operand& operand) 721 722 723 ### sbcs ### 724 725 Subtract with carry bit and update status flags. 726 727 void sbcs(const Register& rd, 728 const Register& rn, 729 const Operand& operand) 730 731 732 ### sbfiz ### 733 734 Signed bitfield insert with zero at right. 735 736 inline void sbfiz(const Register& rd, 737 const Register& rn, 738 unsigned lsb, 739 unsigned width) 740 741 742 ### sbfm ### 743 744 Signed bitfield move. 745 746 void sbfm(const Register& rd, 747 const Register& rn, 748 unsigned immr, 749 unsigned imms) 750 751 752 ### sbfx ### 753 754 Signed bitfield extract. 755 756 inline void sbfx(const Register& rd, 757 const Register& rn, 758 unsigned lsb, 759 unsigned width) 760 761 762 ### scvtf ### 763 764 Convert signed integer or fixed point to FP. 765 766 void scvtf(const FPRegister& fd, const Register& rn, unsigned fbits = 0) 767 768 769 ### sdiv ### 770 771 Signed integer divide. 772 773 void sdiv(const Register& rd, const Register& rn, const Register& rm) 774 775 776 ### smaddl ### 777 778 Signed long multiply and accumulate: 32 x 32 + 64 -> 64-bit. 779 780 void smaddl(const Register& rd, 781 const Register& rn, 782 const Register& rm, 783 const Register& ra) 784 785 786 ### smsubl ### 787 788 Signed long multiply and subtract: 64 - (32 x 32) -> 64-bit. 789 790 void smsubl(const Register& rd, 791 const Register& rn, 792 const Register& rm, 793 const Register& ra) 794 795 796 ### smulh ### 797 798 Signed multiply high: 64 x 64 -> 64-bit <127:64>. 799 800 void smulh(const Register& xd, const Register& xn, const Register& xm) 801 802 803 ### smull ### 804 805 Signed long multiply: 32 x 32 -> 64-bit. 806 807 void smull(const Register& rd, const Register& rn, const Register& rm) 808 809 810 ### stnp ### 811 812 Store integer or FP register pair, non-temporal. 813 814 void stnp(const CPURegister& rt, const CPURegister& rt2, 815 const MemOperand& dst) 816 817 818 ### stp ### 819 820 Store integer or FP register pair. 821 822 void stp(const CPURegister& rt, const CPURegister& rt2, 823 const MemOperand& dst) 824 825 826 ### str ### 827 828 Store integer or FP register. 829 830 void str(const CPURegister& rt, const MemOperand& dst) 831 832 833 ### strb ### 834 835 Store byte. 836 837 void strb(const Register& rt, const MemOperand& dst) 838 839 840 ### strh ### 841 842 Store half-word. 843 844 void strh(const Register& rt, const MemOperand& dst) 845 846 847 ### sub ### 848 849 Subtract. 850 851 void sub(const Register& rd, 852 const Register& rn, 853 const Operand& operand) 854 855 856 ### subs ### 857 858 Subtract and update status flags. 859 860 void subs(const Register& rd, 861 const Register& rn, 862 const Operand& operand) 863 864 865 ### sxtb ### 866 867 Signed extend byte. 868 869 inline void sxtb(const Register& rd, const Register& rn) 870 871 872 ### sxth ### 873 874 Signed extend halfword. 875 876 inline void sxth(const Register& rd, const Register& rn) 877 878 879 ### sxtw ### 880 881 Signed extend word. 882 883 inline void sxtw(const Register& rd, const Register& rn) 884 885 886 ### tbnz ### 887 888 Test bit and branch to PC offset if not zero. 889 890 void tbnz(const Register& rt, unsigned bit_pos, int imm14) 891 892 893 ### tbnz ### 894 895 Test bit and branch to label if not zero. 896 897 void tbnz(const Register& rt, unsigned bit_pos, Label* label) 898 899 900 ### tbz ### 901 902 Test bit and branch to PC offset if zero. 903 904 void tbz(const Register& rt, unsigned bit_pos, int imm14) 905 906 907 ### tbz ### 908 909 Test bit and branch to label if zero. 910 911 void tbz(const Register& rt, unsigned bit_pos, Label* label) 912 913 914 ### tst ### 915 916 Bit test and set flags. 917 918 void tst(const Register& rn, const Operand& operand) 919 920 921 ### ubfiz ### 922 923 Unsigned bitfield insert with zero at right. 924 925 inline void ubfiz(const Register& rd, 926 const Register& rn, 927 unsigned lsb, 928 unsigned width) 929 930 931 ### ubfm ### 932 933 Unsigned bitfield move. 934 935 void ubfm(const Register& rd, 936 const Register& rn, 937 unsigned immr, 938 unsigned imms) 939 940 941 ### ubfx ### 942 943 Unsigned bitfield extract. 944 945 inline void ubfx(const Register& rd, 946 const Register& rn, 947 unsigned lsb, 948 unsigned width) 949 950 951 ### ucvtf ### 952 953 Convert unsigned integer or fixed point to FP. 954 955 void ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits = 0) 956 957 958 ### udiv ### 959 960 Unsigned integer divide. 961 962 void udiv(const Register& rd, const Register& rn, const Register& rm) 963 964 965 ### umaddl ### 966 967 Unsigned long multiply and accumulate: 32 x 32 + 64 -> 64-bit. 968 969 void umaddl(const Register& rd, 970 const Register& rn, 971 const Register& rm, 972 const Register& ra) 973 974 975 ### umsubl ### 976 977 Unsigned long multiply and subtract: 64 - (32 x 32) -> 64-bit. 978 979 void umsubl(const Register& rd, 980 const Register& rn, 981 const Register& rm, 982 const Register& ra) 983 984 985 ### uxtb ### 986 987 Unsigned extend byte. 988 989 inline void uxtb(const Register& rd, const Register& rn) 990 991 992 ### uxth ### 993 994 Unsigned extend halfword. 995 996 inline void uxth(const Register& rd, const Register& rn) 997 998 999 ### uxtw ### 1000 1001 Unsigned extend word. 1002 1003 inline void uxtw(const Register& rd, const Register& rn) 1004 1005 1006 1007 AArch64 floating point instructions 1008 ----------------------------------- 1009 1010 ### fabs ### 1011 1012 FP absolute. 1013 1014 void fabs(const FPRegister& fd, const FPRegister& fn) 1015 1016 1017 ### fadd ### 1018 1019 FP add. 1020 1021 void fadd(const FPRegister& fd, const FPRegister& fn, const FPRegister& fm) 1022 1023 1024 ### fccmp ### 1025 1026 FP conditional compare. 1027 1028 void fccmp(const FPRegister& fn, 1029 const FPRegister& fm, 1030 StatusFlags nzcv, 1031 Condition cond) 1032 1033 1034 ### fcmp ### 1035 1036 FP compare immediate. 1037 1038 void fcmp(const FPRegister& fn, double value) 1039 1040 1041 ### fcmp ### 1042 1043 FP compare registers. 1044 1045 void fcmp(const FPRegister& fn, const FPRegister& fm) 1046 1047 1048 ### fcsel ### 1049 1050 FP conditional select. 1051 1052 void fcsel(const FPRegister& fd, 1053 const FPRegister& fn, 1054 const FPRegister& fm, 1055 Condition cond) 1056 1057 1058 ### fcvt ### 1059 1060 FP convert between single and double precision. 1061 1062 void fcvt(const FPRegister& fd, const FPRegister& fn) 1063 1064 1065 ### fcvtas ### 1066 1067 Convert FP to signed integer (nearest with ties to away). 1068 1069 void fcvtas(const Register& rd, const FPRegister& fn) 1070 1071 1072 ### fcvtau ### 1073 1074 Convert FP to unsigned integer (nearest with ties to away). 1075 1076 void fcvtau(const Register& rd, const FPRegister& fn) 1077 1078 1079 ### fcvtms ### 1080 1081 Convert FP to signed integer (round towards -infinity). 1082 1083 void fcvtms(const Register& rd, const FPRegister& fn) 1084 1085 1086 ### fcvtmu ### 1087 1088 Convert FP to unsigned integer (round towards -infinity). 1089 1090 void fcvtmu(const Register& rd, const FPRegister& fn) 1091 1092 1093 ### fcvtns ### 1094 1095 Convert FP to signed integer (nearest with ties to even). 1096 1097 void fcvtns(const Register& rd, const FPRegister& fn) 1098 1099 1100 ### fcvtnu ### 1101 1102 Convert FP to unsigned integer (nearest with ties to even). 1103 1104 void fcvtnu(const Register& rd, const FPRegister& fn) 1105 1106 1107 ### fcvtzs ### 1108 1109 Convert FP to signed integer (round towards zero). 1110 1111 void fcvtzs(const Register& rd, const FPRegister& fn) 1112 1113 1114 ### fcvtzu ### 1115 1116 Convert FP to unsigned integer (round towards zero). 1117 1118 void fcvtzu(const Register& rd, const FPRegister& fn) 1119 1120 1121 ### fdiv ### 1122 1123 FP divide. 1124 1125 void fdiv(const FPRegister& fd, const FPRegister& fn, const FPRegister& fm) 1126 1127 1128 ### fmadd ### 1129 1130 FP fused multiply and add. 1131 1132 void fmadd(const FPRegister& fd, 1133 const FPRegister& fn, 1134 const FPRegister& fm, 1135 const FPRegister& fa) 1136 1137 1138 ### fmax ### 1139 1140 FP maximum. 1141 1142 void fmax(const FPRegister& fd, const FPRegister& fn, const FPRegister& fm) 1143 1144 1145 ### fmaxnm ### 1146 1147 FP maximum number. 1148 1149 void fmaxnm(const FPRegister& fd, const FPRegister& fn, const FPRegister& fm) 1150 1151 1152 ### fmin ### 1153 1154 FP minimum. 1155 1156 void fmin(const FPRegister& fd, const FPRegister& fn, const FPRegister& fm) 1157 1158 1159 ### fminnm ### 1160 1161 FP minimum number. 1162 1163 void fminnm(const FPRegister& fd, const FPRegister& fn, const FPRegister& fm) 1164 1165 1166 ### fmov ### 1167 1168 Move FP register to FP register. 1169 1170 void fmov(const FPRegister& fd, const FPRegister& fn) 1171 1172 1173 ### fmov ### 1174 1175 Move FP register to register. 1176 1177 void fmov(const Register& rd, const FPRegister& fn) 1178 1179 1180 ### fmov ### 1181 1182 Move double precision immediate to FP register. 1183 1184 void fmov(const FPRegister& fd, double imm) 1185 1186 1187 ### fmov ### 1188 1189 Move register to FP register. 1190 1191 void fmov(const FPRegister& fd, const Register& rn) 1192 1193 1194 ### fmov ### 1195 1196 Move single precision immediate to FP register. 1197 1198 void fmov(const FPRegister& fd, float imm) 1199 1200 1201 ### fmsub ### 1202 1203 FP fused multiply and subtract. 1204 1205 void fmsub(const FPRegister& fd, 1206 const FPRegister& fn, 1207 const FPRegister& fm, 1208 const FPRegister& fa) 1209 1210 1211 ### fmul ### 1212 1213 FP multiply. 1214 1215 void fmul(const FPRegister& fd, const FPRegister& fn, const FPRegister& fm) 1216 1217 1218 ### fneg ### 1219 1220 FP negate. 1221 1222 void fneg(const FPRegister& fd, const FPRegister& fn) 1223 1224 1225 ### fnmadd ### 1226 1227 FP fused multiply, add and negate. 1228 1229 void fnmadd(const FPRegister& fd, 1230 const FPRegister& fn, 1231 const FPRegister& fm, 1232 const FPRegister& fa) 1233 1234 1235 ### fnmsub ### 1236 1237 FP fused multiply, subtract and negate. 1238 1239 void fnmsub(const FPRegister& fd, 1240 const FPRegister& fn, 1241 const FPRegister& fm, 1242 const FPRegister& fa) 1243 1244 1245 ### frinta ### 1246 1247 FP round to integer (nearest with ties to away). 1248 1249 void frinta(const FPRegister& fd, const FPRegister& fn) 1250 1251 1252 ### frintm ### 1253 1254 FP round to integer (toward minus infinity). 1255 1256 void frintm(const FPRegister& fd, const FPRegister& fn) 1257 1258 1259 ### frintn ### 1260 1261 FP round to integer (nearest with ties to even). 1262 1263 void frintn(const FPRegister& fd, const FPRegister& fn) 1264 1265 1266 ### frintz ### 1267 1268 FP round to integer (towards zero). 1269 1270 void frintz(const FPRegister& fd, const FPRegister& fn) 1271 1272 1273 ### fsqrt ### 1274 1275 FP square root. 1276 1277 void fsqrt(const FPRegister& fd, const FPRegister& fn) 1278 1279 1280 ### fsub ### 1281 1282 FP subtract. 1283 1284 void fsub(const FPRegister& fd, const FPRegister& fn, const FPRegister& fm) 1285 1286 1287 1288 Additional or pseudo instructions 1289 --------------------------------- 1290 1291 ### bind ### 1292 1293 Bind a label to the current PC. 1294 1295 void bind(Label* label) 1296 1297 1298 ### dc32 ### 1299 1300 Emit 32 bits of data into the instruction stream. 1301 1302 inline void dc32(uint32_t data) 1303 1304 1305 ### dc64 ### 1306 1307 Emit 64 bits of data into the instruction stream. 1308 1309 inline void dc64(uint64_t data) 1310 1311 1312 ### dci ### 1313 1314 Emit raw instructions into the instruction stream. 1315 1316 inline void dci(Instr raw_inst) 1317 1318 1319 1320
