Lines Matching refs:lir
33 LIR* CheckSuspendUsingLoad() OVERRIDE;
35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
39 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
40 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
45 LIR* GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest);
46 LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src);
72 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
73 void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
77 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
80 size_t GetInsnSize(LIR* lir) OVERRIDE;
81 bool IsUnconditionalBranch(LIR* lir);
136 LIR* OpUnconditionalBranch(LIR* target);
137 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
138 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
139 LIR* OpCondBranch(ConditionCode cc, LIR* target);
140 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
141 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
142 LIR* OpIT(ConditionCode cond, const char* guide);
143 void OpEndIT(LIR* it);
144 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
145 LIR* OpPcRelLoad(RegStorage reg, LIR* target);
146 LIR* OpReg(OpKind op, RegStorage r_dest_src);
148 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
149 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
150 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
151 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
152 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
153 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
154 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
155 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
156 LIR* OpTestSuspend(LIR* target);
157 LIR* OpVldm(RegStorage r_base, int count);
158 LIR* OpVstm(RegStorage r_base, int count);
162 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,
165 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,
182 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
191 void ConvertShortToLongBranch(LIR* lir);
