1 /* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_ 18 #define ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_ 19 20 #include "dex/compiler_internals.h" 21 #include "mips_lir.h" 22 23 namespace art { 24 25 class MipsMir2Lir FINAL : public Mir2Lir { 26 public: 27 MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 28 29 // Required for target - codegen utilities. 30 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 31 RegLocation rl_dest, int lit); 32 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 33 LIR* CheckSuspendUsingLoad() OVERRIDE; 34 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE; 35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 36 OpSize size, VolatileKind is_volatile) OVERRIDE; 37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 38 OpSize size) OVERRIDE; 39 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 40 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 42 OpSize size, VolatileKind is_volatile) OVERRIDE; 43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 44 OpSize size) OVERRIDE; 45 LIR* GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest); 46 LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src); 47 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); 48 49 // Required for target - register utilities. 50 RegStorage Solo64ToPair64(RegStorage reg); 51 RegStorage TargetReg(SpecialTargetRegister reg); 52 RegStorage GetArgMappingToPhysicalReg(int arg_num); 53 RegLocation GetReturnAlt(); 54 RegLocation GetReturnWideAlt(); 55 RegLocation LocCReturn(); 56 RegLocation LocCReturnRef(); 57 RegLocation LocCReturnDouble(); 58 RegLocation LocCReturnFloat(); 59 RegLocation LocCReturnWide(); 60 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 61 void AdjustSpillMask(); 62 void ClobberCallerSave(); 63 void FreeCallTemps(); 64 void LockCallTemps(); 65 void CompilerInitializeRegAlloc(); 66 67 // Required for target - miscellaneous. 68 void AssembleLIR(); 69 int AssignInsnOffsets(); 70 void AssignOffsets(); 71 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 72 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 73 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 74 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 75 const char* GetTargetInstFmt(int opcode); 76 const char* GetTargetInstName(int opcode); 77 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 78 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 79 uint64_t GetTargetInstFlags(int opcode); 80 size_t GetInsnSize(LIR* lir) OVERRIDE; 81 bool IsUnconditionalBranch(LIR* lir); 82 83 // Get the register class for load/store of a field. 84 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 85 86 // Required for target - Dalvik-level generators. 87 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 88 RegLocation rl_src1, RegLocation rl_src2); 89 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 90 RegLocation rl_index, RegLocation rl_dest, int scale); 91 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 92 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); 93 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 94 RegLocation rl_shift); 95 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 96 RegLocation rl_src2); 97 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 98 RegLocation rl_src2); 99 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 100 RegLocation rl_src2); 101 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 102 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; 103 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 104 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 105 bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long); 106 bool GenInlinedSqrt(CallInfo* info); 107 bool GenInlinedPeek(CallInfo* info, OpSize size); 108 bool GenInlinedPoke(CallInfo* info, OpSize size); 109 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 110 RegLocation rl_src2) OVERRIDE; 111 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 112 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 113 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 114 void GenDivZeroCheckWide(RegStorage reg); 115 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 116 void GenExitSequence(); 117 void GenSpecialExitSequence(); 118 void GenFillArrayData(uint32_t table_offset, RegLocation rl_src); 119 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 120 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 121 void GenSelect(BasicBlock* bb, MIR* mir); 122 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, 123 int32_t true_val, int32_t false_val, RegStorage rs_dest, 124 int dest_reg_class) OVERRIDE; 125 bool GenMemBarrier(MemBarrierKind barrier_kind); 126 void GenMoveException(RegLocation rl_dest); 127 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 128 int first_bit, int second_bit); 129 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 130 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 131 void GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src); 132 void GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src); 133 bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 134 135 // Required for target - single operation generators. 136 LIR* OpUnconditionalBranch(LIR* target); 137 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 138 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 139 LIR* OpCondBranch(ConditionCode cc, LIR* target); 140 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 141 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 142 LIR* OpIT(ConditionCode cond, const char* guide); 143 void OpEndIT(LIR* it); 144 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 145 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 146 LIR* OpReg(OpKind op, RegStorage r_dest_src); 147 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 148 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 149 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 150 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 151 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 152 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 153 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 154 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 155 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 156 LIR* OpTestSuspend(LIR* target); 157 LIR* OpVldm(RegStorage r_base, int count); 158 LIR* OpVstm(RegStorage r_base, int count); 159 void OpRegCopyWide(RegStorage dest, RegStorage src); 160 161 // TODO: collapse r_dest. 162 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, 163 OpSize size); 164 // TODO: collapse r_src. 165 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, 166 OpSize size); 167 void SpillCoreRegs(); 168 void UnSpillCoreRegs(); 169 static const MipsEncodingMap EncodingMap[kMipsLast]; 170 bool InexpensiveConstantInt(int32_t value); 171 bool InexpensiveConstantFloat(int32_t value); 172 bool InexpensiveConstantLong(int64_t value); 173 bool InexpensiveConstantDouble(int64_t value); 174 175 bool WideGPRsAreAliases() OVERRIDE { 176 return false; // Wide GPRs are formed by pairing. 177 } 178 bool WideFPRsAreAliases() OVERRIDE { 179 return false; // Wide FPRs are formed by pairing. 180 } 181 182 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE; 183 184 private: 185 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 186 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 187 RegLocation rl_src2); 188 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 189 RegLocation rl_src2); 190 191 void ConvertShortToLongBranch(LIR* lir); 192 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 193 RegLocation rl_src2, bool is_div, bool check_zero); 194 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div); 195 }; 196 197 } // namespace art 198 199 #endif // ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_ 200
