Lines Matching full:scratch
123 // the instructions emitted in the scratch register.
125 unsigned scratch,
129 // Emit: jmpl %g0+Addr, <scratch>
131 Insts.push_back(JMP_INST(0, LO10(Addr), scratch));
137 // Emit: sethi %hi(Addr), scratch
138 // jmpl scratch+%lo(Addr), scratch
139 // sub scratch, 4, scratch
140 Insts.push_back(SETHI_INST(HI22(Addr), scratch));
141 Insts.push_back(JMP_INST(scratch, LO10(Addr), scratch));
142 Insts.push_back(SUB_INST(scratch, 4, scratch));
147 // Emit: sethi %hix(Addr), scratch)
148 // xor scratch, %lox(Addr), scratch
149 // jmpl scratch+0, scratch
150 // sub scratch, 8, scratch
151 Insts.push_back(SETHI_INST(HIX22(Addr), scratch));
152 Insts.push_back(XOR_INST(scratch, LOX10(Addr), scratch));
153 Insts.push_back(JMP_INST(scratch, 0, scratch));
154 Insts.push_back(SUB_INST(scratch, 8, scratch));
158 // Emit: rd %pc, scratch
159 // ldx [scratch+16], scratch
160 // jmpl scratch+0, scratch
161 // sub scratch, 8, scratch
163 Insts.push_back(RDPC_INST(scratch));
164 Insts.push_back(LDX_INST(scratch, 16, scratch));
165 Insts.push_back(JMP_INST(scratch, 0, scratch));
166 Insts.push_back(SUB_INST(scratch, 8, scratch));
171 // 7 instruction and 2 scratch register
172 // Emit: sethi %hh(Addr), scratch
173 // or scratch, %hm(Addr), scratch
174 // sllx scratch, 32, scratch
176 // or scratch, scratch2, scratch
177 // jmpl scratch+%lo(Addr), scratch
178 // sub scratch, 20, scratch
179 // Insts.push_back(SETHI_INST(HH22(Addr), scratch));
180 // Insts.push_back(OR_INST_I(scratch, HM10(Addr), scratch));
181 // Insts.push_back(SLLX_INST(scratch, 32, scratch));
183 // Insts.push_back(OR_INST_R(scratch, scratch2, scratch));
184 // Insts.push_back(JMP_INST(scratch, LO10(Addr), scratch));
185 // Insts.push_back(SUB_INST(scratch, 20, scratch));
