| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 135 unsigned FrameReg = getFrameRegister(MF);
180 dstReg).addReg(FrameReg).addReg(dstReg);
184 dstReg).addReg(FrameReg).addImm(Offset);
209 resReg).addReg(FrameReg).addReg(resReg);
213 resReg).addReg(FrameReg).addImm(Offset);
222 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
240 TII.get(Hexagon::ADD_rr), ResReg).addReg(FrameReg).
247 TII.get(Hexagon::ADD_ri), ResReg).addReg(FrameReg).
260 dstReg).addReg(FrameReg).addReg(dstReg);
268 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 104 unsigned FrameReg;
107 FrameReg = Mips::SP;
111 FrameReg = Mips::S0;
115 FrameReg = MI.getOperand(OpNo+2).getReg();
117 FrameReg = Mips::SP;
138 !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) {
145 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
149 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
|
| MipsSERegisterInfo.cpp | 132 unsigned FrameReg;
135 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
137 FrameReg = getFrameRegister(MF);
176 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
178 FrameReg = Reg;
193 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
196 FrameReg = Reg;
202 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 63 unsigned Reg, unsigned FrameReg, int Offset ) {
71 .addReg(FrameReg)
78 .addReg(FrameReg)
84 .addReg(FrameReg)
94 unsigned Reg, unsigned FrameReg,
107 .addReg(FrameReg)
114 .addReg(FrameReg)
120 .addReg(FrameReg)
288 unsigned FrameReg = getFrameRegister(MF);
292 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 716 unsigned FrameReg;
718 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
725 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
740 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
743 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
763 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
767 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
771 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
|
| ARMFrameLowering.cpp | 711 unsigned &FrameReg) const {
712 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
717 int FI, unsigned &FrameReg,
727 FrameReg = ARM::SP;
739 FrameReg = RegInfo->getFrameRegister(MF);
744 FrameReg = RegInfo->getBaseRegister();
754 FrameReg = RegInfo->getFrameRegister(MF);
763 FrameReg = RegInfo->getFrameRegister(MF);
776 FrameReg = RegInfo->getFrameRegister(MF);
781 FrameReg = RegInfo->getFrameRegister(MF)
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 532 unsigned FrameReg;
533 return getFrameIndexReference(MF, FI, FrameReg);
542 unsigned &FrameReg) const {
543 return resolveFrameIndexReference(MF, FI, FrameReg);
547 int FI, unsigned &FrameReg,
586 FrameReg = RegInfo->getFrameRegister(MF);
592 FrameReg = RegInfo->getBaseRegister();
594 FrameReg = AArch64::SP;
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
