| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 120 unsigned NumOps = Outs.size();
121 for (unsigned i = 0; i != NumOps; ++i) {
139 unsigned NumOps = ArgVTs.size();
140 for (unsigned i = 0; i != NumOps; ++i) {
|
| MachineRegisterInfo.cpp | 139 unsigned NumOps = MI->getNumOperands();
140 if (!(MO >= MO0 && MO < MO0+NumOps)) {
234 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
243 unsigned NumOps) {
244 assert(Src != Dst && NumOps && "Noop moveOperands");
248 if (Dst >= Src && Dst < Src + NumOps) {
250 Dst += NumOps - 1;
251 Src += NumOps - 1;
280 } while (--NumOps);
|
| MachineInstr.cpp | 555 if (unsigned NumOps = MCID->getNumOperands() +
557 CapOperands = OperandCapacity::get(NumOps);
618 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
621 unsigned NumOps, MachineRegisterInfo *MRI) {
623 return MRI->moveOperands(Dst, Src, NumOps);
628 for (unsigned i = 0; i != NumOps; ++i)
631 for (unsigned i = NumOps; i ; --i)
[all...] |
| MachineVerifier.cpp | 749 unsigned NumOps;
750 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
755 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
[all...] |
| TwoAddressInstructionPass.cpp | 435 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 136 unsigned NumOps = Outs.size();
146 for (; i != NumOps; ++i) {
164 unsigned NumOps = ArgVTs.size();
165 for (unsigned i = 0; i != NumOps; ++i) {
|
| HexagonISelLowering.cpp | 696 unsigned NumOps = Node->getNumOperands();
697 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
698 --NumOps; // Ignore the flag operand.
700 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 173 unsigned NumOps = Desc.getNumOperands();
174 if (NumOps) {
175 bool isTwoAddr = NumOps > 1 &&
180 for (unsigned e = NumOps; i != e; ++i) {
194 for (unsigned e = NumOps; i != e; ++i) {
206 for (; i != NumOps; ++i) {
224 if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e)))
241 for (unsigned e = NumOps; i != e; ++i) {
838 unsigned NumOps = Desc->getNumOperands();
840 if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) == 0
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 210 unsigned NumOps = Node->getNumOperands();
211 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
212 Chain = Node->getOperand(NumOps-1).getNode();
[all...] |
| LegalizeTypes.cpp | 417 for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; ++i)
[all...] |
| ScheduleDAGFast.cpp | 488 unsigned NumOps = Node->getNumOperands();
489 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
490 --NumOps; // Ignore the glue operand.
492 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
676 unsigned NumOps = N->getNumOperands();
677 if (unsigned NumLeft = NumOps) {
683 if (NumLeft == NumOps && Op.getValueType() == MVT::Glue) {
|
| ScheduleDAGRRList.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenInstruction.cpp | 71 unsigned NumOps = 1;
91 NumOps = NumArgs;
116 OperandType, MIOperandNo, NumOps,
118 MIOperandNo += NumOps;
|
| DAGISelMatcherEmitter.cpp | 664 unsigned NumOps = P.getNumOperands();
667 ++NumOps; // Get the chained node too.
670 OS << " Result.resize(NextRes+" << NumOps << ");\n";
685 for (unsigned i = 0; i != NumOps; ++i)
|
| AsmWriterEmitter.cpp | 387 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
388 assert(NumOps <= Inst->Operands.size() &&
391 Inst->Operands.begin()+NumOps);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 700 unsigned NumOps = MCID.getNumOperands();
701 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
702 if (HasCC && MI->getOperand(NumOps-1).isDead())
726 unsigned NumOps = MCID.getNumOperands();
728 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
796 unsigned NumOps = MCID.getNumOperands();
797 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
798 if (HasCC && MI->getOperand(NumOps-1).isDead())
822 unsigned NumOps = MCID.getNumOperands();
824 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 735 unsigned NumOps = Desc.getNumOperands();
885 unsigned RcOperand = NumOps-1;
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Scalarizer.cpp | 565 unsigned NumOps = PHI.getNumOperands();
567 Res[I] = Builder.CreatePHI(VT->getElementType(), NumOps,
570 for (unsigned I = 0; I < NumOps; ++I) {
|
| /external/llvm/lib/Linker/ |
| LinkModules.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 663 unsigned NumOps = OldMI->getNumOperands();
664 for (unsigned I = 1; I < NumOps; ++I) {
682 unsigned NumOps = MI->getNumOperands();
712 for (unsigned I = 2; I < NumOps; ++I)
844 unsigned NumOps = MI->getNumExplicitOperands();
845 if (OpNum == NumOps - 1) {
[all...] |
| /external/llvm/lib/IR/ |
| Instructions.cpp | 144 unsigned NumOps = e + e / 2;
145 if (NumOps < 2) NumOps = 2; // 2 op PHI nodes are VERY common.
150 ReservedSpace = NumOps;
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 566 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
568 for (unsigned i = 0; i < NumOps; ++i, ++I) {
631 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
633 for (unsigned i = 0; i < NumOps; ++i, ++I) {
669 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
670 for (unsigned i = 0; i < NumOps; ++i, ++I) {
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | [all...] |
