| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 83 unsigned NumRegs = RC->getNumRegs();
86 RCI.Order.reset(new MCPhysReg[NumRegs]);
115 RCI.NumRegs = N + CSRAlias.size();
116 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
129 if (StressRA && RCI.NumRegs > StressRA)
130 RCI.NumRegs = StressRA;
134 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
142 for (unsigned I = 0; I != RCI.NumRegs; ++I)
|
| VirtRegMap.cpp | 70 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
71 Virt2PhysMap.resize(NumRegs);
72 Virt2StackSlotMap.resize(NumRegs);
73 Virt2SplitMap.resize(NumRegs);
|
| ExecutionDepsFix.cpp | 136 const unsigned NumRegs;
157 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
261 assert(unsigned(rx) < NumRegs && "Invalid index");
273 assert(unsigned(rx) < NumRegs && "Invalid index");
284 assert(unsigned(rx) < NumRegs && "Invalid index");
316 for (unsigned rx = 0; rx != NumRegs; ++rx)
340 for (unsigned rx = 0; rx != NumRegs; ++rx)
360 LiveRegs = new LiveReg[NumRegs];
363 for (unsigned rx = 0; rx != NumRegs; ++rx) {
394 for (unsigned rx = 0; rx != NumRegs; ++rx)
[all...] |
| LiveVariables.cpp | 426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
505 unsigned NumRegs = TRI->getNumRegs();
506 PhysRegDef = new MachineInstr*[NumRegs];
507 PhysRegUse = new MachineInstr*[NumRegs];
509 std::fill(PhysRegDef, PhysRegDef + NumRegs, nullptr);
510 std::fill(PhysRegUse, PhysRegUse + NumRegs, nullptr);
640 for (unsigned i = 0; i != NumRegs; ++i)
644 std::fill(PhysRegDef, PhysRegDef + NumRegs, nullptr);
645 std::fill(PhysRegUse, PhysRegUse + NumRegs, nullptr)
[all...] |
| MachineLICM.cpp | 500 unsigned NumRegs = TRI->getNumRegs();
501 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop.
502 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once.
537 BitVector TermRegs(NumRegs);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 197 unsigned NumRegs;
202 NumRegs = 16;
206 NumRegs = 8;
210 NumRegs = 4;
218 State.AllocateRegBlock(RegList, NumRegs, PendingHAMembers.size());
|
| Thumb1FrameLowering.cpp | 466 bool NumRegs = false;
479 NumRegs = true;
483 if (NumRegs)
|
| ARMExpandPseudoInsts.cpp | 111 uint8_t NumRegs; // D registers loaded or stored
387 unsigned NumRegs = TableEntry->NumRegs;
398 if (NumRegs > 1 && TableEntry->copyAllListRegs)
400 if (NumRegs > 2 && TableEntry->copyAllListRegs)
402 if (NumRegs > 3 && TableEntry->copyAllListRegs)
452 unsigned NumRegs = TableEntry->NumRegs;
473 if (NumRegs > 1 && TableEntry->copyAllListRegs)
475 if (NumRegs > 2 && TableEntry->copyAllListRegs
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 421 unsigned NumRegs = Regs.size();
422 if (NumRegs <= 1)
432 } else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA) {
434 } else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) {
445 if (NumRegs <= 2)
452 NewBase = Regs[NumRegs-1].first;
509 for (unsigned I = 0; I < NumRegs; ++I)
532 UpdateBaseRegUses(MBB, MBBI, dl, Base, NumRegs, Pred, PredReg);
541 for (unsigned i = 0; i != NumRegs; ++i)
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /art/runtime/verifier/ |
| register_line.h | 164 size_t NumRegs() const {
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 29 unsigned NumRegs;
36 : Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0),
40 return makeArrayRef(Order.get(), NumRegs);
87 return get(RC).NumRegs;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 270 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
271 for (unsigned i = 0; i != NumRegs; ++i) {
|
| SelectionDAGBuilder.cpp | 250 unsigned NumRegs =
253 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
254 NumParts = NumRegs; // Silence a compiler warning.
534 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
539 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
540 NumParts = NumRegs; // Silence a compiler warning.
619 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
621 for (unsigned i = 0; i != NumRegs; ++i)
624 Reg += NumRegs;
682 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT)
[all...] |
| LegalizeDAG.cpp | 340 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
354 for (unsigned i = 1; i < NumRegs; i++) {
461 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
472 for (unsigned i = 1; i < NumRegs; i++) {
[all...] |
| LegalizeIntegerTypes.cpp | 748 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
749 // The argument is passed as NumRegs registers of type RegVT.
751 SmallVector<SDValue, 8> Parts(NumRegs);
752 for (unsigned i = 0; i < NumRegs; ++i) {
765 for (unsigned i = 1; i < NumRegs; ++i) {
[all...] |
| /external/llvm/lib/Target/R600/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 62 unsigned NumRegs;
66 NumRegs = 1;
69 NumRegs = 1;
72 NumRegs = 2;
75 NumRegs = 2;
78 NumRegs = 4;
81 NumRegs = 4;
84 NumRegs = 3;
87 NumRegs = 8;
90 NumRegs = 8
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 156 unsigned NumRegs; // Number of entries in the array
251 NumRegs = NR;
315 assert(RegNo < NumRegs &&
360 return NumRegs;
406 assert(RegNo < NumRegs &&
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 342 unsigned NumRegs; // Number of registers used for this argument.
345 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
|
| MipsISelLowering.cpp | [all...] |
| /external/chromium_org/v8/src/ |
| frames.cc | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
