| /art/compiler/utils/arm64/ |
| managed_register_arm64.cc | 47 return (RegNo() == other.RegNo());
52 int Arm64ManagedRegister::RegNo() const {
75 int low = RegNo();
87 int high = RegNo();
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXRegisterInfo.h | 59 const char *getName(unsigned RegNo) const {
61 O << "reg" << RegNo;
|
| NVPTXAsmPrinter.cpp | 830 unsigned RegNo = MI->getOperand(0).getReg();
832 if (TRI->isVirtualRegister(RegNo)) {
834 getVirtualRegisterName(RegNo));
837 TM.getRegisterInfo()->getName(RegNo));
[all...] |
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 35 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
36 OS << getRegisterName(RegNo);
270 unsigned RegNo;
273 case PPC::CR0: RegNo = 0; break;
274 case PPC::CR1: RegNo = 1; break;
275 case PPC::CR2: RegNo = 2; break;
276 case PPC::CR3: RegNo = 3; break;
277 case PPC::CR4: RegNo = 4; break;
278 case PPC::CR5: RegNo = 5; break;
279 case PPC::CR6: RegNo = 6; break
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| StackMaps.h | 100 unsigned short RegNo;
103 LiveOutReg() : Reg(0), RegNo(0), Size(0) {}
104 LiveOutReg(unsigned short Reg, unsigned short RegNo, unsigned short Size)
105 : Reg(Reg), RegNo(RegNo), Size(Size) {}
110 bool operator< (const LiveOutReg &LO) const { return RegNo < LO.RegNo; }
|
| MachineOperand.h | 144 unsigned RegNo; // For MO_Register.
164 // Register number is in SmallContents.RegNo.
266 return SmallContents.RegNo;
595 Op.SmallContents.RegNo = Reg;
|
| /external/llvm/lib/CodeGen/ |
| StackMaps.cpp | 113 // The physical register number will ultimately be encoded as a DWARF regno.
140 int RegNo = TRI->getDwarfRegNum(Reg, false);
141 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNo < 0; ++SR)
142 RegNo = TRI->getDwarfRegNum(*SR, false);
144 assert(RegNo >= 0 && "Invalid Dwarf register number.");
145 return (unsigned) RegNo;
151 unsigned RegNo = getDwarfRegNum(Reg, TRI);
153 return LiveOutReg(Reg, RegNo, Size);
176 if (I->RegNo != II->RegNo) {
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 514 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
519 return RegNo;
524 return 2 * RegNo;
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 53 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
72 // returns true if Tok is matched to a register and returns register in RegNo.
73 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
429 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
434 RegNo = 0;
439 if (matchRegisterName(Tok, RegNo, regKind)) {
607 unsigned RegNo, RegKind;
608 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
613 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
657 unsigned RegNo;
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86Operand.h | 42 unsigned RegNo;
95 return Reg.RegNo;
340 static unsigned getGR32FromGR64(unsigned RegNo) {
341 switch (RegNo) {
365 unsigned RegNo = getReg();
366 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
367 RegNo = getGR32FromGR64(RegNo);
368 Inst.addOperand(MCOperand::CreateReg(RegNo));
423 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc
[all...] |
| X86AsmParser.cpp | 756 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
831 bool X86AsmParser::ParseRegister(unsigned &RegNo,
833 RegNo = 0;
851 RegNo = MatchRegisterName(Tok.getString());
854 if (RegNo == 0)
855 RegNo = MatchRegisterName(Tok.getString().lower());
863 if (RegNo == X86::RIZ ||
864 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
865 X86II::isX86_64NonExtLowByteReg(RegNo) ||
866 X86II::isX86_64ExtendedReg(RegNo))
[all...] |
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 413 int RegNo = I->second[i];
414 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
417 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 231 unsigned &RegNo, int64_t &IntVal);
233 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
958 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
963 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
967 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
971 RegNo = PPC::VRSAVE;
976 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 270 unsigned RegNo = TRI->getEncodingValue(I->first);
271 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
272 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
286 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
287 UsedRegMask &= ~(1 << (31-RegNo));
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | 607 unsigned RegNo = MI->getOperand(0).getReg();
609 TM.getRegisterInfo()->getName(RegNo));
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/MC/MCParser/ |
| AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 351 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
[all...] |
