1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the target machine instruction set to the code generator. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H 15 #define LLVM_TARGET_TARGETINSTRINFO_H 16 17 #include "llvm/ADT/SmallSet.h" 18 #include "llvm/CodeGen/DFAPacketizer.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 22 namespace llvm { 23 24 class InstrItineraryData; 25 class LiveVariables; 26 class MCAsmInfo; 27 class MachineMemOperand; 28 class MachineRegisterInfo; 29 class MDNode; 30 class MCInst; 31 class MCSchedModel; 32 class MCSymbolRefExpr; 33 class SDNode; 34 class ScheduleHazardRecognizer; 35 class SelectionDAG; 36 class ScheduleDAG; 37 class TargetRegisterClass; 38 class TargetRegisterInfo; 39 class BranchProbability; 40 class TargetSubtargetInfo; 41 42 template<class T> class SmallVectorImpl; 43 44 45 //--------------------------------------------------------------------------- 46 /// 47 /// TargetInstrInfo - Interface to description of machine instruction set 48 /// 49 class TargetInstrInfo : public MCInstrInfo { 50 TargetInstrInfo(const TargetInstrInfo &) LLVM_DELETED_FUNCTION; 51 void operator=(const TargetInstrInfo &) LLVM_DELETED_FUNCTION; 52 public: 53 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1) 54 : CallFrameSetupOpcode(CFSetupOpcode), 55 CallFrameDestroyOpcode(CFDestroyOpcode) { 56 } 57 58 virtual ~TargetInstrInfo(); 59 60 /// getRegClass - Givem a machine instruction descriptor, returns the register 61 /// class constraint for OpNum, or NULL. 62 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, 63 unsigned OpNum, 64 const TargetRegisterInfo *TRI, 65 const MachineFunction &MF) const; 66 67 /// isTriviallyReMaterializable - Return true if the instruction is trivially 68 /// rematerializable, meaning it has no side effects and requires no operands 69 /// that aren't always available. 70 bool isTriviallyReMaterializable(const MachineInstr *MI, 71 AliasAnalysis *AA = nullptr) const { 72 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 73 (MI->getDesc().isRematerializable() && 74 (isReallyTriviallyReMaterializable(MI, AA) || 75 isReallyTriviallyReMaterializableGeneric(MI, AA))); 76 } 77 78 protected: 79 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 80 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 81 /// specify whether the instruction is actually trivially rematerializable, 82 /// taking into consideration its operands. This predicate must return false 83 /// if the instruction has any side effects other than producing a value, or 84 /// if it requres any address registers that are not always available. 85 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 86 AliasAnalysis *AA) const { 87 return false; 88 } 89 90 private: 91 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 92 /// for which the M_REMATERIALIZABLE flag is set and the target hook 93 /// isReallyTriviallyReMaterializable returns false, this function does 94 /// target-independent tests to determine if the instruction is really 95 /// trivially rematerializable. 96 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 97 AliasAnalysis *AA) const; 98 99 public: 100 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 101 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 102 /// targets use pseudo instructions in order to abstract away the difference 103 /// between operating with a frame pointer and operating without, through the 104 /// use of these two instructions. 105 /// 106 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 107 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 108 109 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 110 /// extension instruction. That is, it's like a copy where it's legal for the 111 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 112 /// true, then it's expected the pre-extension value is available as a subreg 113 /// of the result register. This also returns the sub-register index in 114 /// SubIdx. 115 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 116 unsigned &SrcReg, unsigned &DstReg, 117 unsigned &SubIdx) const { 118 return false; 119 } 120 121 /// isLoadFromStackSlot - If the specified machine instruction is a direct 122 /// load from a stack slot, return the virtual or physical register number of 123 /// the destination along with the FrameIndex of the loaded stack slot. If 124 /// not, return 0. This predicate must return 0 if the instruction has 125 /// any side effects other than loading from the stack slot. 126 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 127 int &FrameIndex) const { 128 return 0; 129 } 130 131 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 132 /// stack locations as well. This uses a heuristic so it isn't 133 /// reliable for correctness. 134 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 135 int &FrameIndex) const { 136 return 0; 137 } 138 139 /// hasLoadFromStackSlot - If the specified machine instruction has 140 /// a load from a stack slot, return true along with the FrameIndex 141 /// of the loaded stack slot and the machine mem operand containing 142 /// the reference. If not, return false. Unlike 143 /// isLoadFromStackSlot, this returns true for any instructions that 144 /// loads from the stack. This is just a hint, as some cases may be 145 /// missed. 146 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 147 const MachineMemOperand *&MMO, 148 int &FrameIndex) const; 149 150 /// isStoreToStackSlot - If the specified machine instruction is a direct 151 /// store to a stack slot, return the virtual or physical register number of 152 /// the source reg along with the FrameIndex of the loaded stack slot. If 153 /// not, return 0. This predicate must return 0 if the instruction has 154 /// any side effects other than storing to the stack slot. 155 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 156 int &FrameIndex) const { 157 return 0; 158 } 159 160 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 161 /// stack locations as well. This uses a heuristic so it isn't 162 /// reliable for correctness. 163 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 164 int &FrameIndex) const { 165 return 0; 166 } 167 168 /// hasStoreToStackSlot - If the specified machine instruction has a 169 /// store to a stack slot, return true along with the FrameIndex of 170 /// the loaded stack slot and the machine mem operand containing the 171 /// reference. If not, return false. Unlike isStoreToStackSlot, 172 /// this returns true for any instructions that stores to the 173 /// stack. This is just a hint, as some cases may be missed. 174 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 175 const MachineMemOperand *&MMO, 176 int &FrameIndex) const; 177 178 /// isStackSlotCopy - Return true if the specified machine instruction 179 /// is a copy of one stack slot to another and has no other effect. 180 /// Provide the identity of the two frame indices. 181 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, 182 int &SrcFrameIndex) const { 183 return false; 184 } 185 186 /// Compute the size in bytes and offset within a stack slot of a spilled 187 /// register or subregister. 188 /// 189 /// \param [out] Size in bytes of the spilled value. 190 /// \param [out] Offset in bytes within the stack slot. 191 /// \returns true if both Size and Offset are successfully computed. 192 /// 193 /// Not all subregisters have computable spill slots. For example, 194 /// subregisters registers may not be byte-sized, and a pair of discontiguous 195 /// subregisters has no single offset. 196 /// 197 /// Targets with nontrivial bigendian implementations may need to override 198 /// this, particularly to support spilled vector registers. 199 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, 200 unsigned &Size, unsigned &Offset, 201 const TargetMachine *TM) const; 202 203 /// isAsCheapAsAMove - Return true if the instruction is as cheap as a move 204 /// instruction. 205 /// 206 /// Targets for different archs need to override this, and different 207 /// micro-architectures can also be finely tuned inside. 208 virtual bool isAsCheapAsAMove(const MachineInstr *MI) const { 209 return MI->isAsCheapAsAMove(); 210 } 211 212 /// reMaterialize - Re-issue the specified 'original' instruction at the 213 /// specific location targeting a new destination register. 214 /// The register in Orig->getOperand(0).getReg() will be substituted by 215 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 216 /// SubIdx. 217 virtual void reMaterialize(MachineBasicBlock &MBB, 218 MachineBasicBlock::iterator MI, 219 unsigned DestReg, unsigned SubIdx, 220 const MachineInstr *Orig, 221 const TargetRegisterInfo &TRI) const; 222 223 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 224 /// MachineFunction::CloneMachineInstr(), but the target may update operands 225 /// that are required to be unique. 226 /// 227 /// The instruction must be duplicable as indicated by isNotDuplicable(). 228 virtual MachineInstr *duplicate(MachineInstr *Orig, 229 MachineFunction &MF) const; 230 231 /// convertToThreeAddress - This method must be implemented by targets that 232 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 233 /// may be able to convert a two-address instruction into one or more true 234 /// three-address instructions on demand. This allows the X86 target (for 235 /// example) to convert ADD and SHL instructions into LEA instructions if they 236 /// would require register copies due to two-addressness. 237 /// 238 /// This method returns a null pointer if the transformation cannot be 239 /// performed, otherwise it returns the last new instruction. 240 /// 241 virtual MachineInstr * 242 convertToThreeAddress(MachineFunction::iterator &MFI, 243 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 244 return nullptr; 245 } 246 247 /// commuteInstruction - If a target has any instructions that are 248 /// commutable but require converting to different instructions or making 249 /// non-trivial changes to commute them, this method can overloaded to do 250 /// that. The default implementation simply swaps the commutable operands. 251 /// If NewMI is false, MI is modified in place and returned; otherwise, a 252 /// new machine instruction is created and returned. Do not call this 253 /// method for a non-commutable instruction, but there may be some cases 254 /// where this method fails and returns null. 255 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 256 bool NewMI = false) const; 257 258 /// findCommutedOpIndices - If specified MI is commutable, return the two 259 /// operand indices that would swap value. Return false if the instruction 260 /// is not in a form which this routine understands. 261 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 262 unsigned &SrcOpIdx2) const; 263 264 /// produceSameValue - Return true if two machine instructions would produce 265 /// identical values. By default, this is only true when the two instructions 266 /// are deemed identical except for defs. If this function is called when the 267 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 268 /// aggressive checks. 269 virtual bool produceSameValue(const MachineInstr *MI0, 270 const MachineInstr *MI1, 271 const MachineRegisterInfo *MRI = nullptr) const; 272 273 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 274 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 275 /// implemented for a target). Upon success, this returns false and returns 276 /// with the following information in various cases: 277 /// 278 /// 1. If this block ends with no branches (it just falls through to its succ) 279 /// just return false, leaving TBB/FBB null. 280 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 281 /// the destination block. 282 /// 3. If this block ends with a conditional branch and it falls through to a 283 /// successor block, it sets TBB to be the branch destination block and a 284 /// list of operands that evaluate the condition. These operands can be 285 /// passed to other TargetInstrInfo methods to create new branches. 286 /// 4. If this block ends with a conditional branch followed by an 287 /// unconditional branch, it returns the 'true' destination in TBB, the 288 /// 'false' destination in FBB, and a list of operands that evaluate the 289 /// condition. These operands can be passed to other TargetInstrInfo 290 /// methods to create new branches. 291 /// 292 /// Note that RemoveBranch and InsertBranch must be implemented to support 293 /// cases where this method returns success. 294 /// 295 /// If AllowModify is true, then this routine is allowed to modify the basic 296 /// block (e.g. delete instructions after the unconditional branch). 297 /// 298 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 299 MachineBasicBlock *&FBB, 300 SmallVectorImpl<MachineOperand> &Cond, 301 bool AllowModify = false) const { 302 return true; 303 } 304 305 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 306 /// This is only invoked in cases where AnalyzeBranch returns success. It 307 /// returns the number of instructions that were removed. 308 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 309 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!"); 310 } 311 312 /// InsertBranch - Insert branch code into the end of the specified 313 /// MachineBasicBlock. The operands to this method are the same as those 314 /// returned by AnalyzeBranch. This is only invoked in cases where 315 /// AnalyzeBranch returns success. It returns the number of instructions 316 /// inserted. 317 /// 318 /// It is also invoked by tail merging to add unconditional branches in 319 /// cases where AnalyzeBranch doesn't apply because there was no original 320 /// branch to analyze. At least this much must be implemented, else tail 321 /// merging needs to be disabled. 322 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 323 MachineBasicBlock *FBB, 324 const SmallVectorImpl<MachineOperand> &Cond, 325 DebugLoc DL) const { 326 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!"); 327 } 328 329 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 330 /// after it, replacing it with an unconditional branch to NewDest. This is 331 /// used by the tail merging pass. 332 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 333 MachineBasicBlock *NewDest) const; 334 335 /// getUnconditionalBranch - Get an instruction that performs an unconditional 336 /// branch to the given symbol. 337 virtual void 338 getUnconditionalBranch(MCInst &MI, 339 const MCSymbolRefExpr *BranchTarget) const { 340 llvm_unreachable("Target didn't implement " 341 "TargetInstrInfo::getUnconditionalBranch!"); 342 } 343 344 /// getTrap - Get a machine trap instruction 345 virtual void getTrap(MCInst &MI) const { 346 llvm_unreachable("Target didn't implement TargetInstrInfo::getTrap!"); 347 } 348 349 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 350 /// block at the specified instruction (i.e. instruction would be the start 351 /// of a new basic block). 352 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 353 MachineBasicBlock::iterator MBBI) const { 354 return true; 355 } 356 357 /// isProfitableToIfCvt - Return true if it's profitable to predicate 358 /// instructions with accumulated instruction latency of "NumCycles" 359 /// of the specified basic block, where the probability of the instructions 360 /// being executed is given by Probability, and Confidence is a measure 361 /// of our confidence that it will be properly predicted. 362 virtual 363 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 364 unsigned ExtraPredCycles, 365 const BranchProbability &Probability) const { 366 return false; 367 } 368 369 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 370 /// checks for the case where two basic blocks from true and false path 371 /// of a if-then-else (diamond) are predicated on mutally exclusive 372 /// predicates, where the probability of the true path being taken is given 373 /// by Probability, and Confidence is a measure of our confidence that it 374 /// will be properly predicted. 375 virtual bool 376 isProfitableToIfCvt(MachineBasicBlock &TMBB, 377 unsigned NumTCycles, unsigned ExtraTCycles, 378 MachineBasicBlock &FMBB, 379 unsigned NumFCycles, unsigned ExtraFCycles, 380 const BranchProbability &Probability) const { 381 return false; 382 } 383 384 /// isProfitableToDupForIfCvt - Return true if it's profitable for 385 /// if-converter to duplicate instructions of specified accumulated 386 /// instruction latencies in the specified MBB to enable if-conversion. 387 /// The probability of the instructions being executed is given by 388 /// Probability, and Confidence is a measure of our confidence that it 389 /// will be properly predicted. 390 virtual bool 391 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 392 const BranchProbability &Probability) const { 393 return false; 394 } 395 396 /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate 397 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually 398 /// exclusive predicates. 399 /// e.g. 400 /// subeq r0, r1, #1 401 /// addne r0, r1, #1 402 /// => 403 /// sub r0, r1, #1 404 /// addne r0, r1, #1 405 /// 406 /// This may be profitable is conditional instructions are always executed. 407 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 408 MachineBasicBlock &FMBB) const { 409 return false; 410 } 411 412 /// canInsertSelect - Return true if it is possible to insert a select 413 /// instruction that chooses between TrueReg and FalseReg based on the 414 /// condition code in Cond. 415 /// 416 /// When successful, also return the latency in cycles from TrueReg, 417 /// FalseReg, and Cond to the destination register. In most cases, a select 418 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1 419 /// 420 /// Some x86 implementations have 2-cycle cmov instructions. 421 /// 422 /// @param MBB Block where select instruction would be inserted. 423 /// @param Cond Condition returned by AnalyzeBranch. 424 /// @param TrueReg Virtual register to select when Cond is true. 425 /// @param FalseReg Virtual register to select when Cond is false. 426 /// @param CondCycles Latency from Cond+Branch to select output. 427 /// @param TrueCycles Latency from TrueReg to select output. 428 /// @param FalseCycles Latency from FalseReg to select output. 429 virtual bool canInsertSelect(const MachineBasicBlock &MBB, 430 const SmallVectorImpl<MachineOperand> &Cond, 431 unsigned TrueReg, unsigned FalseReg, 432 int &CondCycles, 433 int &TrueCycles, int &FalseCycles) const { 434 return false; 435 } 436 437 /// insertSelect - Insert a select instruction into MBB before I that will 438 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when 439 /// Cond is false. 440 /// 441 /// This function can only be called after canInsertSelect() returned true. 442 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed 443 /// that the same flags or registers required by Cond are available at the 444 /// insertion point. 445 /// 446 /// @param MBB Block where select instruction should be inserted. 447 /// @param I Insertion point. 448 /// @param DL Source location for debugging. 449 /// @param DstReg Virtual register to be defined by select instruction. 450 /// @param Cond Condition as computed by AnalyzeBranch. 451 /// @param TrueReg Virtual register to copy when Cond is true. 452 /// @param FalseReg Virtual register to copy when Cons is false. 453 virtual void insertSelect(MachineBasicBlock &MBB, 454 MachineBasicBlock::iterator I, DebugLoc DL, 455 unsigned DstReg, 456 const SmallVectorImpl<MachineOperand> &Cond, 457 unsigned TrueReg, unsigned FalseReg) const { 458 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!"); 459 } 460 461 /// analyzeSelect - Analyze the given select instruction, returning true if 462 /// it cannot be understood. It is assumed that MI->isSelect() is true. 463 /// 464 /// When successful, return the controlling condition and the operands that 465 /// determine the true and false result values. 466 /// 467 /// Result = SELECT Cond, TrueOp, FalseOp 468 /// 469 /// Some targets can optimize select instructions, for example by predicating 470 /// the instruction defining one of the operands. Such targets should set 471 /// Optimizable. 472 /// 473 /// @param MI Select instruction to analyze. 474 /// @param Cond Condition controlling the select. 475 /// @param TrueOp Operand number of the value selected when Cond is true. 476 /// @param FalseOp Operand number of the value selected when Cond is false. 477 /// @param Optimizable Returned as true if MI is optimizable. 478 /// @returns False on success. 479 virtual bool analyzeSelect(const MachineInstr *MI, 480 SmallVectorImpl<MachineOperand> &Cond, 481 unsigned &TrueOp, unsigned &FalseOp, 482 bool &Optimizable) const { 483 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction"); 484 return true; 485 } 486 487 /// optimizeSelect - Given a select instruction that was understood by 488 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by 489 /// merging it with one of its operands. Returns NULL on failure. 490 /// 491 /// When successful, returns the new select instruction. The client is 492 /// responsible for deleting MI. 493 /// 494 /// If both sides of the select can be optimized, PreferFalse is used to pick 495 /// a side. 496 /// 497 /// @param MI Optimizable select instruction. 498 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp. 499 /// @returns Optimized instruction or NULL. 500 virtual MachineInstr *optimizeSelect(MachineInstr *MI, 501 bool PreferFalse = false) const { 502 // This function must be implemented if Optimizable is ever set. 503 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!"); 504 } 505 506 /// copyPhysReg - Emit instructions to copy a pair of physical registers. 507 /// 508 /// This function should support copies within any legal register class as 509 /// well as any cross-class copies created during instruction selection. 510 /// 511 /// The source and destination registers may overlap, which may require a 512 /// careful implementation when multiple copy instructions are required for 513 /// large registers. See for example the ARM target. 514 virtual void copyPhysReg(MachineBasicBlock &MBB, 515 MachineBasicBlock::iterator MI, DebugLoc DL, 516 unsigned DestReg, unsigned SrcReg, 517 bool KillSrc) const { 518 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!"); 519 } 520 521 /// storeRegToStackSlot - Store the specified register of the given register 522 /// class to the specified stack frame index. The store instruction is to be 523 /// added to the given machine basic block before the specified machine 524 /// instruction. If isKill is true, the register operand is the last use and 525 /// must be marked kill. 526 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 527 MachineBasicBlock::iterator MI, 528 unsigned SrcReg, bool isKill, int FrameIndex, 529 const TargetRegisterClass *RC, 530 const TargetRegisterInfo *TRI) const { 531 llvm_unreachable("Target didn't implement " 532 "TargetInstrInfo::storeRegToStackSlot!"); 533 } 534 535 /// loadRegFromStackSlot - Load the specified register of the given register 536 /// class from the specified stack frame index. The load instruction is to be 537 /// added to the given machine basic block before the specified machine 538 /// instruction. 539 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 540 MachineBasicBlock::iterator MI, 541 unsigned DestReg, int FrameIndex, 542 const TargetRegisterClass *RC, 543 const TargetRegisterInfo *TRI) const { 544 llvm_unreachable("Target didn't implement " 545 "TargetInstrInfo::loadRegFromStackSlot!"); 546 } 547 548 /// expandPostRAPseudo - This function is called for all pseudo instructions 549 /// that remain after register allocation. Many pseudo instructions are 550 /// created to help register allocation. This is the place to convert them 551 /// into real instructions. The target can edit MI in place, or it can insert 552 /// new instructions and erase MI. The function should return true if 553 /// anything was changed. 554 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 555 return false; 556 } 557 558 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 559 /// slot into the specified machine instruction for the specified operand(s). 560 /// If this is possible, a new instruction is returned with the specified 561 /// operand folded, otherwise NULL is returned. 562 /// The new instruction is inserted before MI, and the client is responsible 563 /// for removing the old instruction. 564 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 565 const SmallVectorImpl<unsigned> &Ops, 566 int FrameIndex) const; 567 568 /// foldMemoryOperand - Same as the previous version except it allows folding 569 /// of any load and store from / to any address, not just from a specific 570 /// stack slot. 571 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 572 const SmallVectorImpl<unsigned> &Ops, 573 MachineInstr* LoadMI) const; 574 575 protected: 576 /// foldMemoryOperandImpl - Target-dependent implementation for 577 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 578 /// take care of adding a MachineMemOperand to the newly created instruction. 579 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 580 MachineInstr* MI, 581 const SmallVectorImpl<unsigned> &Ops, 582 int FrameIndex) const { 583 return nullptr; 584 } 585 586 /// foldMemoryOperandImpl - Target-dependent implementation for 587 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 588 /// take care of adding a MachineMemOperand to the newly created instruction. 589 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 590 MachineInstr* MI, 591 const SmallVectorImpl<unsigned> &Ops, 592 MachineInstr* LoadMI) const { 593 return nullptr; 594 } 595 596 public: 597 /// canFoldMemoryOperand - Returns true for the specified load / store if 598 /// folding is possible. 599 virtual 600 bool canFoldMemoryOperand(const MachineInstr *MI, 601 const SmallVectorImpl<unsigned> &Ops) const; 602 603 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 604 /// a store or a load and a store into two or more instruction. If this is 605 /// possible, returns true as well as the new instructions by reference. 606 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 607 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 608 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 609 return false; 610 } 611 612 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 613 SmallVectorImpl<SDNode*> &NewNodes) const { 614 return false; 615 } 616 617 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 618 /// instruction after load / store are unfolded from an instruction of the 619 /// specified opcode. It returns zero if the specified unfolding is not 620 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 621 /// index of the operand which will hold the register holding the loaded 622 /// value. 623 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 624 bool UnfoldLoad, bool UnfoldStore, 625 unsigned *LoadRegIndex = nullptr) const { 626 return 0; 627 } 628 629 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 630 /// to determine if two loads are loading from the same base address. It 631 /// should only return true if the base pointers are the same and the 632 /// only differences between the two addresses are the offset. It also returns 633 /// the offsets by reference. 634 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 635 int64_t &Offset1, int64_t &Offset2) const { 636 return false; 637 } 638 639 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 640 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 641 /// be scheduled togther. On some targets if two loads are loading from 642 /// addresses in the same cache line, it's better if they are scheduled 643 /// together. This function takes two integers that represent the load offsets 644 /// from the common base address. It returns true if it decides it's desirable 645 /// to schedule the two loads together. "NumLoads" is the number of loads that 646 /// have already been scheduled after Load1. 647 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 648 int64_t Offset1, int64_t Offset2, 649 unsigned NumLoads) const { 650 return false; 651 } 652 653 /// \brief Get the base register and byte offset of a load/store instr. 654 virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt, 655 unsigned &BaseReg, unsigned &Offset, 656 const TargetRegisterInfo *TRI) const { 657 return false; 658 } 659 660 virtual bool enableClusterLoads() const { return false; } 661 662 virtual bool shouldClusterLoads(MachineInstr *FirstLdSt, 663 MachineInstr *SecondLdSt, 664 unsigned NumLoads) const { 665 return false; 666 } 667 668 /// \brief Can this target fuse the given instructions if they are scheduled 669 /// adjacent. 670 virtual bool shouldScheduleAdjacent(MachineInstr* First, 671 MachineInstr *Second) const { 672 return false; 673 } 674 675 /// ReverseBranchCondition - Reverses the branch condition of the specified 676 /// condition list, returning false on success and true if it cannot be 677 /// reversed. 678 virtual 679 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 680 return true; 681 } 682 683 /// insertNoop - Insert a noop into the instruction stream at the specified 684 /// point. 685 virtual void insertNoop(MachineBasicBlock &MBB, 686 MachineBasicBlock::iterator MI) const; 687 688 689 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 690 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 691 // Default to just using 'nop' string. 692 } 693 694 695 /// isPredicated - Returns true if the instruction is already predicated. 696 /// 697 virtual bool isPredicated(const MachineInstr *MI) const { 698 return false; 699 } 700 701 /// isUnpredicatedTerminator - Returns true if the instruction is a 702 /// terminator instruction that has not been predicated. 703 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 704 705 /// PredicateInstruction - Convert the instruction into a predicated 706 /// instruction. It returns true if the operation was successful. 707 virtual 708 bool PredicateInstruction(MachineInstr *MI, 709 const SmallVectorImpl<MachineOperand> &Pred) const; 710 711 /// SubsumesPredicate - Returns true if the first specified predicate 712 /// subsumes the second, e.g. GE subsumes GT. 713 virtual 714 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 715 const SmallVectorImpl<MachineOperand> &Pred2) const { 716 return false; 717 } 718 719 /// DefinesPredicate - If the specified instruction defines any predicate 720 /// or condition code register(s) used for predication, returns true as well 721 /// as the definition predicate(s) by reference. 722 virtual bool DefinesPredicate(MachineInstr *MI, 723 std::vector<MachineOperand> &Pred) const { 724 return false; 725 } 726 727 /// isPredicable - Return true if the specified instruction can be predicated. 728 /// By default, this returns true for every instruction with a 729 /// PredicateOperand. 730 virtual bool isPredicable(MachineInstr *MI) const { 731 return MI->getDesc().isPredicable(); 732 } 733 734 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 735 /// instruction that defines the specified register class. 736 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 737 return true; 738 } 739 740 /// isSchedulingBoundary - Test if the given instruction should be 741 /// considered a scheduling boundary. This primarily includes labels and 742 /// terminators. 743 virtual bool isSchedulingBoundary(const MachineInstr *MI, 744 const MachineBasicBlock *MBB, 745 const MachineFunction &MF) const; 746 747 /// Measure the specified inline asm to determine an approximation of its 748 /// length. 749 virtual unsigned getInlineAsmLength(const char *Str, 750 const MCAsmInfo &MAI) const; 751 752 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to 753 /// use for this target when scheduling the machine instructions before 754 /// register allocation. 755 virtual ScheduleHazardRecognizer* 756 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 757 const ScheduleDAG *DAG) const; 758 759 /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer 760 /// to use for this target when scheduling the machine instructions before 761 /// register allocation. 762 virtual ScheduleHazardRecognizer* 763 CreateTargetMIHazardRecognizer(const InstrItineraryData*, 764 const ScheduleDAG *DAG) const; 765 766 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard 767 /// recognizer to use for this target when scheduling the machine instructions 768 /// after register allocation. 769 virtual ScheduleHazardRecognizer* 770 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 771 const ScheduleDAG *DAG) const; 772 773 /// Provide a global flag for disabling the PreRA hazard recognizer that 774 /// targets may choose to honor. 775 bool usePreRAHazardRecognizer() const; 776 777 /// analyzeCompare - For a comparison instruction, return the source registers 778 /// in SrcReg and SrcReg2 if having two register operands, and the value it 779 /// compares against in CmpValue. Return true if the comparison instruction 780 /// can be analyzed. 781 virtual bool analyzeCompare(const MachineInstr *MI, 782 unsigned &SrcReg, unsigned &SrcReg2, 783 int &Mask, int &Value) const { 784 return false; 785 } 786 787 /// optimizeCompareInstr - See if the comparison instruction can be converted 788 /// into something more efficient. E.g., on ARM most instructions can set the 789 /// flags register, obviating the need for a separate CMP. 790 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, 791 unsigned SrcReg, unsigned SrcReg2, 792 int Mask, int Value, 793 const MachineRegisterInfo *MRI) const { 794 return false; 795 } 796 797 /// optimizeLoadInstr - Try to remove the load by folding it to a register 798 /// operand at the use. We fold the load instructions if and only if the 799 /// def and use are in the same BB. We only look at one load and see 800 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 801 /// defined by the load we are trying to fold. DefMI returns the machine 802 /// instruction that defines FoldAsLoadDefReg, and the function returns 803 /// the machine instruction generated due to folding. 804 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI, 805 const MachineRegisterInfo *MRI, 806 unsigned &FoldAsLoadDefReg, 807 MachineInstr *&DefMI) const { 808 return nullptr; 809 } 810 811 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 812 /// instruction, try to fold the immediate into the use instruction. 813 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, 814 /// then the caller may assume that DefMI has been erased from its parent 815 /// block. The caller may assume that it will not be erased by this 816 /// function otherwise. 817 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 818 unsigned Reg, MachineRegisterInfo *MRI) const { 819 return false; 820 } 821 822 /// getNumMicroOps - Return the number of u-operations the given machine 823 /// instruction will be decoded to on the target cpu. The itinerary's 824 /// IssueWidth is the number of microops that can be dispatched each 825 /// cycle. An instruction with zero microops takes no dispatch resources. 826 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 827 const MachineInstr *MI) const; 828 829 /// isZeroCost - Return true for pseudo instructions that don't consume any 830 /// machine resources in their current form. These are common cases that the 831 /// scheduler should consider free, rather than conservatively handling them 832 /// as instructions with no itinerary. 833 bool isZeroCost(unsigned Opcode) const { 834 return Opcode <= TargetOpcode::COPY; 835 } 836 837 virtual int getOperandLatency(const InstrItineraryData *ItinData, 838 SDNode *DefNode, unsigned DefIdx, 839 SDNode *UseNode, unsigned UseIdx) const; 840 841 /// getOperandLatency - Compute and return the use operand latency of a given 842 /// pair of def and use. 843 /// In most cases, the static scheduling itinerary was enough to determine the 844 /// operand latency. But it may not be possible for instructions with variable 845 /// number of defs / uses. 846 /// 847 /// This is a raw interface to the itinerary that may be directly overriden by 848 /// a target. Use computeOperandLatency to get the best estimate of latency. 849 virtual int getOperandLatency(const InstrItineraryData *ItinData, 850 const MachineInstr *DefMI, unsigned DefIdx, 851 const MachineInstr *UseMI, 852 unsigned UseIdx) const; 853 854 /// computeOperandLatency - Compute and return the latency of the given data 855 /// dependent def and use when the operand indices are already known. 856 unsigned computeOperandLatency(const InstrItineraryData *ItinData, 857 const MachineInstr *DefMI, unsigned DefIdx, 858 const MachineInstr *UseMI, unsigned UseIdx) 859 const; 860 861 /// getInstrLatency - Compute the instruction latency of a given instruction. 862 /// If the instruction has higher cost when predicated, it's returned via 863 /// PredCost. 864 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 865 const MachineInstr *MI, 866 unsigned *PredCost = nullptr) const; 867 868 virtual unsigned getPredicationCost(const MachineInstr *MI) const; 869 870 virtual int getInstrLatency(const InstrItineraryData *ItinData, 871 SDNode *Node) const; 872 873 /// Return the default expected latency for a def based on it's opcode. 874 unsigned defaultDefLatency(const MCSchedModel *SchedModel, 875 const MachineInstr *DefMI) const; 876 877 int computeDefOperandLatency(const InstrItineraryData *ItinData, 878 const MachineInstr *DefMI) const; 879 880 /// isHighLatencyDef - Return true if this opcode has high latency to its 881 /// result. 882 virtual bool isHighLatencyDef(int opc) const { return false; } 883 884 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 885 /// and an use in the current loop, return true if the target considered 886 /// it 'high'. This is used by optimization passes such as machine LICM to 887 /// determine whether it makes sense to hoist an instruction out even in 888 /// high register pressure situation. 889 virtual 890 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 891 const MachineRegisterInfo *MRI, 892 const MachineInstr *DefMI, unsigned DefIdx, 893 const MachineInstr *UseMI, unsigned UseIdx) const { 894 return false; 895 } 896 897 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 898 /// if the target considered it 'low'. 899 virtual 900 bool hasLowDefLatency(const InstrItineraryData *ItinData, 901 const MachineInstr *DefMI, unsigned DefIdx) const; 902 903 /// verifyInstruction - Perform target specific instruction verification. 904 virtual 905 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const { 906 return true; 907 } 908 909 /// getExecutionDomain - Return the current execution domain and bit mask of 910 /// possible domains for instruction. 911 /// 912 /// Some micro-architectures have multiple execution domains, and multiple 913 /// opcodes that perform the same operation in different domains. For 914 /// example, the x86 architecture provides the por, orps, and orpd 915 /// instructions that all do the same thing. There is a latency penalty if a 916 /// register is written in one domain and read in another. 917 /// 918 /// This function returns a pair (domain, mask) containing the execution 919 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain 920 /// function can be used to change the opcode to one of the domains in the 921 /// bit mask. Instructions whose execution domain can't be changed should 922 /// return a 0 mask. 923 /// 924 /// The execution domain numbers don't have any special meaning except domain 925 /// 0 is used for instructions that are not associated with any interesting 926 /// execution domain. 927 /// 928 virtual std::pair<uint16_t, uint16_t> 929 getExecutionDomain(const MachineInstr *MI) const { 930 return std::make_pair(0, 0); 931 } 932 933 /// setExecutionDomain - Change the opcode of MI to execute in Domain. 934 /// 935 /// The bit (1 << Domain) must be set in the mask returned from 936 /// getExecutionDomain(MI). 937 /// 938 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {} 939 940 941 /// getPartialRegUpdateClearance - Returns the preferred minimum clearance 942 /// before an instruction with an unwanted partial register update. 943 /// 944 /// Some instructions only write part of a register, and implicitly need to 945 /// read the other parts of the register. This may cause unwanted stalls 946 /// preventing otherwise unrelated instructions from executing in parallel in 947 /// an out-of-order CPU. 948 /// 949 /// For example, the x86 instruction cvtsi2ss writes its result to bits 950 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so 951 /// the instruction needs to wait for the old value of the register to become 952 /// available: 953 /// 954 /// addps %xmm1, %xmm0 955 /// movaps %xmm0, (%rax) 956 /// cvtsi2ss %rbx, %xmm0 957 /// 958 /// In the code above, the cvtsi2ss instruction needs to wait for the addps 959 /// instruction before it can issue, even though the high bits of %xmm0 960 /// probably aren't needed. 961 /// 962 /// This hook returns the preferred clearance before MI, measured in 963 /// instructions. Other defs of MI's operand OpNum are avoided in the last N 964 /// instructions before MI. It should only return a positive value for 965 /// unwanted dependencies. If the old bits of the defined register have 966 /// useful values, or if MI is determined to otherwise read the dependency, 967 /// the hook should return 0. 968 /// 969 /// The unwanted dependency may be handled by: 970 /// 971 /// 1. Allocating the same register for an MI def and use. That makes the 972 /// unwanted dependency identical to a required dependency. 973 /// 974 /// 2. Allocating a register for the def that has no defs in the previous N 975 /// instructions. 976 /// 977 /// 3. Calling breakPartialRegDependency() with the same arguments. This 978 /// allows the target to insert a dependency breaking instruction. 979 /// 980 virtual unsigned 981 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 982 const TargetRegisterInfo *TRI) const { 983 // The default implementation returns 0 for no partial register dependency. 984 return 0; 985 } 986 987 /// \brief Return the minimum clearance before an instruction that reads an 988 /// unused register. 989 /// 990 /// For example, AVX instructions may copy part of an register operand into 991 /// the unused high bits of the destination register. 992 /// 993 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14 994 /// 995 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a 996 /// false dependence on any previous write to %xmm0. 997 /// 998 /// This hook works similarly to getPartialRegUpdateClearance, except that it 999 /// does not take an operand index. Instead sets \p OpNum to the index of the 1000 /// unused register. 1001 virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, 1002 const TargetRegisterInfo *TRI) const { 1003 // The default implementation returns 0 for no undef register dependency. 1004 return 0; 1005 } 1006 1007 /// breakPartialRegDependency - Insert a dependency-breaking instruction 1008 /// before MI to eliminate an unwanted dependency on OpNum. 1009 /// 1010 /// If it wasn't possible to avoid a def in the last N instructions before MI 1011 /// (see getPartialRegUpdateClearance), this hook will be called to break the 1012 /// unwanted dependency. 1013 /// 1014 /// On x86, an xorps instruction can be used as a dependency breaker: 1015 /// 1016 /// addps %xmm1, %xmm0 1017 /// movaps %xmm0, (%rax) 1018 /// xorps %xmm0, %xmm0 1019 /// cvtsi2ss %rbx, %xmm0 1020 /// 1021 /// An <imp-kill> operand should be added to MI if an instruction was 1022 /// inserted. This ties the instructions together in the post-ra scheduler. 1023 /// 1024 virtual void 1025 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 1026 const TargetRegisterInfo *TRI) const {} 1027 1028 /// Create machine specific model for scheduling. 1029 virtual DFAPacketizer* 1030 CreateTargetScheduleState(const TargetMachine*, const ScheduleDAG*) const { 1031 return nullptr; 1032 } 1033 1034 private: 1035 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 1036 }; 1037 1038 } // End llvm namespace 1039 1040 #endif 1041
