1 /* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #include "codegen_x86.h" 18 #include "dex/quick/mir_to_lir-inl.h" 19 #include "x86_lir.h" 20 21 namespace art { 22 23 #define MAX_ASSEMBLER_RETRIES 50 24 25 const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = { 26 { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4, false }, "data", "0x!0d" }, 27 { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0, false }, "int 3", "" }, 28 { kX86Nop, kNop, NO_OPERAND, { 0, 0, 0x90, 0, 0, 0, 0, 0, false }, "nop", "" }, 29 30 #define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \ 31 rm8_r8, rm32_r32, \ 32 r8_rm8, r32_rm32, \ 33 ax8_i8, ax32_i32, \ 34 rm8_i8, rm8_i8_modrm, \ 35 rm32_i32, rm32_i32_modrm, \ 36 rm32_i8, rm32_i8_modrm) \ 37 { kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8MR", "[!0r+!1d],!2r" }, \ 38 { kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 39 { kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8TR", "fs:[!0d],!1r" }, \ 40 { kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RR", "!0r,!1r" }, \ 41 { kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RM", "!0r,[!1r+!2d]" }, \ 42 { kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 43 { kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RT", "!0r,fs:[!1d]" }, \ 44 { kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1, true }, #opname "8RI", "!0r,!1d" }, \ 45 { kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, false}, #opname "8MI", "[!0r+!1d],!2d" }, \ 46 { kX86 ## opname ## 8AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, false}, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 47 { kX86 ## opname ## 8TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, false}, #opname "8TI", "fs:[!0d],!1d" }, \ 48 \ 49 { kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16MR", "[!0r+!1d],!2r" }, \ 50 { kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 51 { kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16TR", "fs:[!0d],!1r" }, \ 52 { kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RR", "!0r,!1r" }, \ 53 { kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RM", "!0r,[!1r+!2d]" }, \ 54 { kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 55 { kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RT", "!0r,fs:[!1d]" }, \ 56 { kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2, false }, #opname "16RI", "!0r,!1d" }, \ 57 { kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16MI", "[!0r+!1d],!2d" }, \ 58 { kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 59 { kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16TI", "fs:[!0d],!1d" }, \ 60 { kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16RI8", "!0r,!1d" }, \ 61 { kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16MI8", "[!0r+!1d],!2d" }, \ 62 { kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 63 { kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16TI8", "fs:[!0d],!1d" }, \ 64 \ 65 { kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32MR", "[!0r+!1d],!2r" }, \ 66 { kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 67 { kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32TR", "fs:[!0d],!1r" }, \ 68 { kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RR", "!0r,!1r" }, \ 69 { kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RM", "!0r,[!1r+!2d]" }, \ 70 { kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 71 { kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RT", "!0r,fs:[!1d]" }, \ 72 { kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "32RI", "!0r,!1d" }, \ 73 { kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32MI", "[!0r+!1d],!2d" }, \ 74 { kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 75 { kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32TI", "fs:[!0d],!1d" }, \ 76 { kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32RI8", "!0r,!1d" }, \ 77 { kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32MI8", "[!0r+!1d],!2d" }, \ 78 { kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 79 { kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32TI8", "fs:[!0d],!1d" }, \ 80 \ 81 { kX86 ## opname ## 64MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64MR", "[!0r+!1d],!2r" }, \ 82 { kX86 ## opname ## 64AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 83 { kX86 ## opname ## 64TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64TR", "fs:[!0d],!1r" }, \ 84 { kX86 ## opname ## 64RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RR", "!0r,!1r" }, \ 85 { kX86 ## opname ## 64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RM", "!0r,[!1r+!2d]" }, \ 86 { kX86 ## opname ## 64RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 87 { kX86 ## opname ## 64RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RT", "!0r,fs:[!1d]" }, \ 88 { kX86 ## opname ## 64RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "64RI", "!0r,!1d" }, \ 89 { kX86 ## opname ## 64MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64MI", "[!0r+!1d],!2d" }, \ 90 { kX86 ## opname ## 64AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 91 { kX86 ## opname ## 64TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64TI", "fs:[!0d],!1d" }, \ 92 { kX86 ## opname ## 64RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64RI8", "!0r,!1d" }, \ 93 { kX86 ## opname ## 64MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64MI8", "[!0r+!1d],!2d" }, \ 94 { kX86 ## opname ## 64AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 95 { kX86 ## opname ## 64TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64TI8", "fs:[!0d],!1d" } 96 97 ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0, 98 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */, 99 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */, 100 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */, 101 0x80, 0x0 /* RegMem8/imm8 */, 102 0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */), 103 ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0, 104 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */, 105 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */, 106 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */, 107 0x80, 0x1 /* RegMem8/imm8 */, 108 0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */), 109 ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, 110 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */, 111 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */, 112 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */, 113 0x80, 0x2 /* RegMem8/imm8 */, 114 0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */), 115 ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, 116 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */, 117 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */, 118 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */, 119 0x80, 0x3 /* RegMem8/imm8 */, 120 0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */), 121 ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0, 122 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */, 123 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */, 124 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */, 125 0x80, 0x4 /* RegMem8/imm8 */, 126 0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */), 127 ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0, 128 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */, 129 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */, 130 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */, 131 0x80, 0x5 /* RegMem8/imm8 */, 132 0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */), 133 ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0, 134 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */, 135 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */, 136 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */, 137 0x80, 0x6 /* RegMem8/imm8 */, 138 0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */), 139 ENCODING_MAP(Cmp, IS_LOAD, 0, 0, 140 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */, 141 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */, 142 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */, 143 0x80, 0x7 /* RegMem8/imm8 */, 144 0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */), 145 #undef ENCODING_MAP 146 147 { kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RRI", "!0r,!1r,!2d" }, 148 { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RMI", "!0r,[!1r+!2d],!3d" }, 149 { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 150 151 { kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RRI", "!0r,!1r,!2d" }, 152 { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RMI", "!0r,[!1r+!2d],!3d" }, 153 { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 154 { kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RRI8", "!0r,!1r,!2d" }, 155 { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" }, 156 { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 157 158 { kX86Imul64RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RRI", "!0r,!1r,!2d" }, 159 { kX86Imul64RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RMI", "!0r,[!1r+!2d],!3d" }, 160 { kX86Imul64RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 161 { kX86Imul64RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RRI8", "!0r,!1r,!2d" }, 162 { kX86Imul64RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RMI8", "!0r,[!1r+!2d],!3d" }, 163 { kX86Imul64RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 164 165 { kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8MR", "[!0r+!1d],!2r" }, 166 { kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" }, 167 { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8TR", "fs:[!0d],!1r" }, 168 { kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RR", "!0r,!1r" }, 169 { kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RM", "!0r,[!1r+!2d]" }, 170 { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 171 { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RT", "!0r,fs:[!1d]" }, 172 { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1, true }, "Mov8RI", "!0r,!1d" }, 173 { kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1, false}, "Mov8MI", "[!0r+!1d],!2d" }, 174 { kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1, false}, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" }, 175 { kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1, false}, "Mov8TI", "fs:[!0d],!1d" }, 176 177 { kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16MR", "[!0r+!1d],!2r" }, 178 { kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" }, 179 { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0, false }, "Mov16TR", "fs:[!0d],!1r" }, 180 { kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RR", "!0r,!1r" }, 181 { kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RM", "!0r,[!1r+!2d]" }, 182 { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 183 { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RT", "!0r,fs:[!1d]" }, 184 { kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2, false }, "Mov16RI", "!0r,!1d" }, 185 { kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16MI", "[!0r+!1d],!2d" }, 186 { kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" }, 187 { kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16TI", "fs:[!0d],!1d" }, 188 189 { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32MR", "[!0r+!1d],!2r" }, 190 { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" }, 191 { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32TR", "fs:[!0d],!1r" }, 192 { kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RR", "!0r,!1r" }, 193 { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RM", "!0r,[!1r+!2d]" }, 194 { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 195 { kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RT", "!0r,fs:[!1d]" }, 196 { kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "Mov32RI", "!0r,!1d" }, 197 { kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32MI", "[!0r+!1d],!2d" }, 198 { kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" }, 199 { kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32TI", "fs:[!0d],!1d" }, 200 201 { kX86Lea32RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RM", "!0r,[!1r+!2d]" }, 202 { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 203 204 { kX86Mov64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64MR", "[!0r+!1d],!2r" }, 205 { kX86Mov64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64AR", "[!0r+!1r<<!2d+!3d],!4r" }, 206 { kX86Mov64TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, REX_W, 0x89, 0, 0, 0, 0, 0, false }, "Mov64TR", "fs:[!0d],!1r" }, 207 { kX86Mov64RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RR", "!0r,!1r" }, 208 { kX86Mov64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RM", "!0r,[!1r+!2d]" }, 209 { kX86Mov64RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 210 { kX86Mov64RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, REX_W, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RT", "!0r,fs:[!1d]" }, 211 { kX86Mov64RI32, kRegImm, IS_BINARY_OP | REG_DEF0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64RI32", "!0r,!1d" }, 212 { kX86Mov64RI64, kMovRegQuadImm, IS_TERTIARY_OP | REG_DEF0, { REX_W, 0, 0xB8, 0, 0, 0, 0, 8, false }, "Mov64RI64", "!0r,!1q" }, 213 { kX86Mov64MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64MI", "[!0r+!1d],!2d" }, 214 { kX86Mov64AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64AI", "[!0r+!1r<<!2d+!3d],!4d" }, 215 { kX86Mov64TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, REX_W, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64TI", "fs:[!0d],!1d" }, 216 217 { kX86Lea64RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RM", "!0r,[!1r+!2d]" }, 218 { kX86Lea64RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 219 220 { kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RR", "!2c !0r,!1r" }, 221 { kX86Cmov64RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RR", "!2c !0r,!1r" }, 222 223 { kX86Cmov32RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RM", "!3c !0r,[!1r+!2d]" }, 224 { kX86Cmov64RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RM", "!3c !0r,[!1r+!2d]" }, 225 226 #define SHIFT_ENCODING_MAP(opname, modrm_opcode) \ 227 { kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8RI", "!0r,!1d" }, \ 228 { kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8MI", "[!0r+!1d],!2d" }, \ 229 { kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 230 { kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8RC", "!0r,cl" }, \ 231 { kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8MC", "[!0r+!1d],cl" }, \ 232 { kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 233 \ 234 { kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16RI", "!0r,!1d" }, \ 235 { kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16MI", "[!0r+!1d],!2d" }, \ 236 { kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 237 { kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16RC", "!0r,cl" }, \ 238 { kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16MC", "[!0r+!1d],cl" }, \ 239 { kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 240 \ 241 { kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32RI", "!0r,!1d" }, \ 242 { kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32MI", "[!0r+!1d],!2d" }, \ 243 { kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 244 { kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32RC", "!0r,cl" }, \ 245 { kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32MC", "[!0r+!1d],cl" }, \ 246 { kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 247 \ 248 { kX86 ## opname ## 64RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64RI", "!0r,!1d" }, \ 249 { kX86 ## opname ## 64MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64MI", "[!0r+!1d],!2d" }, \ 250 { kX86 ## opname ## 64AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 251 { kX86 ## opname ## 64RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64RC", "!0r,cl" }, \ 252 { kX86 ## opname ## 64MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64MC", "[!0r+!1d],cl" }, \ 253 { kX86 ## opname ## 64AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64AC", "[!0r+!1r<<!2d+!3d],cl" } 254 255 SHIFT_ENCODING_MAP(Rol, 0x0), 256 SHIFT_ENCODING_MAP(Ror, 0x1), 257 SHIFT_ENCODING_MAP(Rcl, 0x2), 258 SHIFT_ENCODING_MAP(Rcr, 0x3), 259 SHIFT_ENCODING_MAP(Sal, 0x4), 260 SHIFT_ENCODING_MAP(Shr, 0x5), 261 SHIFT_ENCODING_MAP(Sar, 0x7), 262 #undef SHIFT_ENCODING_MAP 263 264 { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0, false }, "Cmc", "" }, 265 { kX86Shld32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32RRI", "!0r,!1r,!2d" }, 266 { kX86Shld32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32MRI", "[!0r+!1d],!2r,!3d" }, 267 { kX86Shrd32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32RRI", "!0r,!1r,!2d" }, 268 { kX86Shrd32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32MRI", "[!0r+!1d],!2r,!3d" }, 269 { kX86Shld64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64RRI", "!0r,!1r,!2d" }, 270 { kX86Shld64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64MRI", "[!0r+!1d],!2r,!3d" }, 271 { kX86Shrd64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64RRI", "!0r,!1r,!2d" }, 272 { kX86Shrd64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64MRI", "[!0r+!1d],!2r,!3d" }, 273 274 { kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8RI", "!0r,!1d" }, 275 { kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8MI", "[!0r+!1d],!2d" }, 276 { kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" }, 277 { kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16RI", "!0r,!1d" }, 278 { kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16MI", "[!0r+!1d],!2d" }, 279 { kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" }, 280 { kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32RI", "!0r,!1d" }, 281 { kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32MI", "[!0r+!1d],!2d" }, 282 { kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" }, 283 { kX86Test64RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64RI", "!0r,!1d" }, 284 { kX86Test64MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64MI", "[!0r+!1d],!2d" }, 285 { kX86Test64AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64AI", "[!0r+!1r<<!2d+!3d],!4d" }, 286 287 { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test32RR", "!0r,!1r" }, 288 { kX86Test64RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test64RR", "!0r,!1r" }, 289 { kX86Test32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test32RM", "!0r,[!1r+!2d]" }, 290 291 #define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \ 292 reg, reg_kind, reg_flags, \ 293 mem, mem_kind, mem_flags, \ 294 arr, arr_kind, arr_flags, imm, \ 295 b_flags, hw_flags, w_flags, \ 296 b_format, hw_format, w_format) \ 297 { kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #reg, b_format "!0r" }, \ 298 { kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #mem, b_format "[!0r+!1d]" }, \ 299 { kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #arr, b_format "[!0r+!1r<<!2d+!3d]" }, \ 300 { kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #reg, hw_format "!0r" }, \ 301 { kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #mem, hw_format "[!0r+!1d]" }, \ 302 { kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #arr, hw_format "[!0r+!1r<<!2d+!3d]" }, \ 303 { kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #reg, w_format "!0r" }, \ 304 { kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #mem, w_format "[!0r+!1d]" }, \ 305 { kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #arr, w_format "[!0r+!1r<<!2d+!3d]" }, \ 306 { kX86 ## opname ## 64 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #reg, w_format "!0r" }, \ 307 { kX86 ## opname ## 64 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #mem, w_format "[!0r+!1d]" }, \ 308 { kX86 ## opname ## 64 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #arr, w_format "[!0r+!1r<<!2d+!3d]" } 309 310 UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), 311 UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), 312 313 UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), 314 UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), 315 UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), 316 UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), 317 #undef UNARY_ENCODING_MAP 318 319 { kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cdq", "" }, 320 { kx86Cqo64Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { REX_W, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cqo", "" }, 321 { kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0, false }, "Bswap32R", "!0r" }, 322 { kX86Bswap64R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { REX_W, 0, 0x0F, 0xC8, 0, 0, 0, 0, false }, "Bswap64R", "!0r" }, 323 { kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0, false }, "Push32R", "!0r" }, 324 { kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0, false }, "Pop32R", "!0r" }, 325 326 #define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \ 327 { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ 328 { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 329 { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 330 331 // This is a special encoding with r8_form on the second register only 332 // for Movzx8 and Movsx8. 333 #define EXT_0F_R8_FORM_ENCODING_MAP(opname, prefix, opcode, reg_def) \ 334 { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, true }, #opname "RR", "!0r,!1r" }, \ 335 { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 336 { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 337 338 #define EXT_0F_REX_W_ENCODING_MAP(opname, prefix, opcode, reg_def) \ 339 { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ 340 { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 341 { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 342 343 #define EXT_0F_ENCODING2_MAP(opname, prefix, opcode, opcode2, reg_def) \ 344 { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ 345 { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 346 { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 347 348 EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0), 349 { kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdMR", "[!0r+!1d],!2r" }, 350 { kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" }, 351 352 EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0), 353 { kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssMR", "[!0r+!1d],!2r" }, 354 { kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" }, 355 356 EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0), 357 EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0), 358 EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2sd, 0xF2, 0x2A, REG_DEF0), 359 EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2ss, 0xF3, 0x2A, REG_DEF0), 360 EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0), 361 EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0), 362 EXT_0F_REX_W_ENCODING_MAP(Cvttsd2sqi, 0xF2, 0x2C, REG_DEF0), 363 EXT_0F_REX_W_ENCODING_MAP(Cvttss2sqi, 0xF3, 0x2C, REG_DEF0), 364 EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0), 365 EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0), 366 EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES|REG_USE0), 367 EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES|REG_USE0), 368 EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES|REG_USE0), 369 EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES|REG_USE0), 370 EXT_0F_ENCODING_MAP(Orpd, 0x66, 0x56, REG_DEF0_USE0), 371 EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0_USE0), 372 EXT_0F_ENCODING_MAP(Andpd, 0x66, 0x54, REG_DEF0_USE0), 373 EXT_0F_ENCODING_MAP(Andps, 0x00, 0x54, REG_DEF0_USE0), 374 EXT_0F_ENCODING_MAP(Xorpd, 0x66, 0x57, REG_DEF0_USE0), 375 EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0_USE0), 376 EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0_USE0), 377 EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0_USE0), 378 EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0_USE0), 379 EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0_USE0), 380 EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0), 381 EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0), 382 EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0_USE0), 383 EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0_USE0), 384 EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0_USE0), 385 EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0_USE0), 386 EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0_USE0), 387 EXT_0F_ENCODING_MAP(Sqrtsd, 0xF2, 0x51, REG_DEF0_USE0), 388 EXT_0F_ENCODING2_MAP(Pmulld, 0x66, 0x38, 0x40, REG_DEF0_USE0), 389 EXT_0F_ENCODING_MAP(Pmullw, 0x66, 0xD5, REG_DEF0_USE0), 390 EXT_0F_ENCODING_MAP(Mulps, 0x00, 0x59, REG_DEF0_USE0), 391 EXT_0F_ENCODING_MAP(Mulpd, 0x66, 0x59, REG_DEF0_USE0), 392 EXT_0F_ENCODING_MAP(Paddb, 0x66, 0xFC, REG_DEF0_USE0), 393 EXT_0F_ENCODING_MAP(Paddw, 0x66, 0xFD, REG_DEF0_USE0), 394 EXT_0F_ENCODING_MAP(Paddd, 0x66, 0xFE, REG_DEF0_USE0), 395 EXT_0F_ENCODING_MAP(Addps, 0x00, 0x58, REG_DEF0_USE0), 396 EXT_0F_ENCODING_MAP(Addpd, 0xF2, 0x58, REG_DEF0_USE0), 397 EXT_0F_ENCODING_MAP(Psubb, 0x66, 0xF8, REG_DEF0_USE0), 398 EXT_0F_ENCODING_MAP(Psubw, 0x66, 0xF9, REG_DEF0_USE0), 399 EXT_0F_ENCODING_MAP(Psubd, 0x66, 0xFA, REG_DEF0_USE0), 400 EXT_0F_ENCODING_MAP(Subps, 0x00, 0x5C, REG_DEF0_USE0), 401 EXT_0F_ENCODING_MAP(Subpd, 0x66, 0x5C, REG_DEF0_USE0), 402 EXT_0F_ENCODING_MAP(Pand, 0x66, 0xDB, REG_DEF0_USE0), 403 EXT_0F_ENCODING_MAP(Por, 0x66, 0xEB, REG_DEF0_USE0), 404 EXT_0F_ENCODING_MAP(Pxor, 0x66, 0xEF, REG_DEF0_USE0), 405 EXT_0F_ENCODING2_MAP(Phaddw, 0x66, 0x38, 0x01, REG_DEF0_USE0), 406 EXT_0F_ENCODING2_MAP(Phaddd, 0x66, 0x38, 0x02, REG_DEF0_USE0), 407 EXT_0F_ENCODING_MAP(Haddpd, 0x66, 0x7C, REG_DEF0_USE0), 408 EXT_0F_ENCODING_MAP(Haddps, 0xF2, 0x7C, REG_DEF0_USE0), 409 410 { kX86PextrbRRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x14, 0, 0, 1, false }, "PextbRRI", "!0r,!1r,!2d" }, 411 { kX86PextrwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0xC5, 0x00, 0, 0, 1, false }, "PextwRRI", "!0r,!1r,!2d" }, 412 { kX86PextrdRRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "PextdRRI", "!0r,!1r,!2d" }, 413 { kX86PextrbMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "kX86PextrbMRI", "[!0r+!1d],!2r,!3d" }, 414 { kX86PextrwMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "kX86PextrwMRI", "[!0r+!1d],!2r,!3d" }, 415 { kX86PextrdMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "kX86PextrdMRI", "[!0r+!1d],!2r,!3d" }, 416 417 { kX86PshuflwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0xF2, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuflwRRI", "!0r,!1r,!2d" }, 418 { kX86PshufdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuffRRI", "!0r,!1r,!2d" }, 419 420 { kX86ShufpsRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x00, 0, 0x0F, 0xC6, 0, 0, 0, 1, false }, "kX86ShufpsRRI", "!0r,!1r,!2d" }, 421 { kX86ShufpdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0xC6, 0, 0, 0, 1, false }, "kX86ShufpdRRI", "!0r,!1r,!2d" }, 422 423 { kX86PsrawRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 4, 0, 1, false }, "PsrawRI", "!0r,!1d" }, 424 { kX86PsradRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 4, 0, 1, false }, "PsradRI", "!0r,!1d" }, 425 { kX86PsrlwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 2, 0, 1, false }, "PsrlwRI", "!0r,!1d" }, 426 { kX86PsrldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 2, 0, 1, false }, "PsrldRI", "!0r,!1d" }, 427 { kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1, false }, "PsrlqRI", "!0r,!1d" }, 428 { kX86PsllwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 6, 0, 1, false }, "PsllwRI", "!0r,!1d" }, 429 { kX86PslldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 6, 0, 1, false }, "PslldRI", "!0r,!1d" }, 430 { kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1, false }, "PsllqRI", "!0r,!1d" }, 431 432 { kX86Fild32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDB, 0x00, 0, 0, 0, 0, false }, "Fild32M", "[!0r,!1d]" }, 433 { kX86Fild64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDF, 0x00, 0, 5, 0, 0, false }, "Fild64M", "[!0r,!1d]" }, 434 { kX86Fld32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 0, 0, 0, false }, "Fld32M", "[!0r,!1d]" }, 435 { kX86Fld64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 0, 0, 0, false }, "Fld64M", "[!0r,!1d]" }, 436 { kX86Fstp32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 3, 0, 0, false }, "Fstps32M", "[!0r,!1d]" }, 437 { kX86Fstp64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0, false }, "Fstpd64M", "[!0r,!1d]" }, 438 { kX86Fst32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 2, 0, 0, false }, "Fsts32M", "[!0r,!1d]" }, 439 { kX86Fst64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 2, 0, 0, false }, "Fstd64M", "[!0r,!1d]" }, 440 { kX86Fprem, kNullary, NO_OPERAND | USE_FP_STACK, { 0xD9, 0, 0xF8, 0, 0, 0, 0, 0, false }, "Fprem64", "" }, 441 { kX86Fucompp, kNullary, NO_OPERAND | USE_FP_STACK, { 0xDA, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Fucompp", "" }, 442 { kX86Fstsw16R, kNullary, NO_OPERAND | REG_DEFA | USE_FP_STACK, { 0x9B, 0xDF, 0xE0, 0, 0, 0, 0, 0, false }, "Fstsw16R", "ax" }, 443 444 EXT_0F_ENCODING_MAP(Mova128, 0x66, 0x6F, REG_DEF0), 445 { kX86Mova128MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "Mova128MR", "[!0r+!1d],!2r" }, 446 { kX86Mova128AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "Mova128AR", "[!0r+!1r<<!2d+!3d],!4r" }, 447 448 449 EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0), 450 { kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsMR", "[!0r+!1d],!2r" }, 451 { kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 452 453 EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0), 454 { kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsMR", "[!0r+!1d],!2r" }, 455 { kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 456 457 { kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRM", "!0r,[!1r+!2d]" }, 458 { kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, 459 { kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsMR", "[!0r+!1d],!2r" }, 460 { kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 461 462 { kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRM", "!0r,[!1r+!2d]" }, 463 { kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, 464 { kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsMR", "[!0r+!1d],!2r" }, 465 { kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 466 467 EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0), 468 EXT_0F_REX_W_ENCODING_MAP(Movqxr, 0x66, 0x6E, REG_DEF0), 469 { kX86MovqrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxRR", "!0r,!1r" }, 470 { kX86MovqrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxMR", "[!0r+!1d],!2r" }, 471 { kX86MovqrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, 472 473 { kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxRR", "!0r,!1r" }, 474 { kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxMR", "[!0r+!1d],!2r" }, 475 { kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, 476 477 { kX86MovsxdRR, kRegReg, IS_BINARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRR", "!0r,!1r" }, 478 { kX86MovsxdRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRM", "!0r,[!1r+!2d]" }, 479 { kX86MovsxdRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE12, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRA", "!0r,[!1r+!2r<<!3d+!4d]" }, 480 481 { kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, true }, "Set8R", "!1c !0r" }, 482 { kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8M", "!2c [!0r+!1d]" }, 483 { kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" }, 484 485 // TODO: load/store? 486 // Encode the modrm opcode as an extra opcode byte to avoid computation during assembly. 487 { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0, false }, "Mfence", "" }, 488 489 EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), 490 EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), 491 EXT_0F_ENCODING_MAP(Imul64, REX_W, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), 492 493 { kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "!0r,!1r" }, 494 { kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1d],!2r" }, 495 { kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 496 { kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1d],!2r" }, 497 { kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 498 { kX86LockCmpxchg64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, REX_W, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 499 { kX86LockCmpxchg64M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1d]" }, 500 { kX86LockCmpxchg64A, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" }, 501 { kX86XchgMR, kMemReg, IS_STORE | IS_LOAD | IS_TERTIARY_OP | REG_DEF2 | REG_USE02, { 0, 0, 0x87, 0, 0, 0, 0, 0, false }, "Xchg", "[!0r+!1d],!2r" }, 502 503 EXT_0F_R8_FORM_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0), 504 EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0), 505 EXT_0F_R8_FORM_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0), 506 EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0), 507 EXT_0F_ENCODING_MAP(Movzx8q, REX_W, 0xB6, REG_DEF0), 508 EXT_0F_ENCODING_MAP(Movzx16q, REX_W, 0xB7, REG_DEF0), 509 EXT_0F_ENCODING_MAP(Movsx8q, REX, 0xBE, REG_DEF0), 510 EXT_0F_ENCODING_MAP(Movsx16q, REX_W, 0xBF, REG_DEF0), 511 #undef EXT_0F_ENCODING_MAP 512 513 { kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0, false }, "Jcc8", "!1c !0t" }, 514 { kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0, false }, "Jcc32", "!1c !0t" }, 515 { kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0, false }, "Jmp8", "!0t" }, 516 { kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Jmp32", "!0t" }, 517 { kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpR", "!0r" }, 518 { kX86Jecxz8, kJmp, NO_OPERAND | IS_BRANCH | NEEDS_FIXUP | REG_USEC, { 0, 0, 0xE3, 0, 0, 0, 0, 0, false }, "Jecxz", "!0t" }, 519 { kX86JmpT, kJmp, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpT", "fs:[!0d]" }, 520 { kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0, false }, "CallR", "!0r" }, 521 { kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallM", "[!0r+!1d]" }, 522 { kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallA", "[!0r+!1r<<!2d+!3d]" }, 523 { kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallT", "fs:[!0d]" }, 524 { kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4, false }, "CallI", "!0d" }, 525 { kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Ret", "" }, 526 527 { kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0, false }, "StartOfMethod", "!0r" }, 528 { kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" }, 529 { kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "PcRelAdr", "!0r,!1d" }, 530 { kX86RepneScasw, kNullary, NO_OPERAND | REG_USEA | REG_USEC | SETS_CCODES, { 0x66, 0xF2, 0xAF, 0, 0, 0, 0, 0, false }, "RepNE ScasW", "" }, 531 }; 532 533 static bool NeedsRex(int32_t raw_reg) { 534 return RegStorage::RegNum(raw_reg) > 7; 535 } 536 537 static uint8_t LowRegisterBits(int32_t raw_reg) { 538 uint8_t low_reg = RegStorage::RegNum(raw_reg) & kRegNumMask32; // 3 bits 539 DCHECK_LT(low_reg, 8); 540 return low_reg; 541 } 542 543 static bool HasModrm(const X86EncodingMap* entry) { 544 switch (entry->kind) { 545 case kNullary: return false; 546 case kRegOpcode: return false; 547 default: return true; 548 } 549 } 550 551 static bool HasSib(const X86EncodingMap* entry) { 552 switch (entry->kind) { 553 case kArray: return true; 554 case kArrayReg: return true; 555 case kRegArray: return true; 556 case kArrayImm: return true; 557 case kRegArrayImm: return true; 558 case kShiftArrayImm: return true; 559 case kShiftArrayCl: return true; 560 case kArrayCond: return true; 561 case kCall: 562 switch (entry->opcode) { 563 case kX86CallA: return true; 564 default: return false; 565 } 566 case kPcRel: return true; 567 switch (entry->opcode) { 568 case kX86PcRelLoadRA: return true; 569 default: return false; 570 } 571 default: return false; 572 } 573 } 574 575 static bool ModrmIsRegReg(const X86EncodingMap* entry) { 576 switch (entry->kind) { 577 // There is no modrm for this kind of instruction, therefore the reg doesn't form part of the 578 // modrm: 579 case kNullary: return true; 580 case kRegOpcode: return true; 581 case kMovRegImm: return true; 582 // Regular modrm value of 3 cases, when there is one register the other register holds an 583 // opcode so the base register is special. 584 case kReg: return true; 585 case kRegReg: return true; 586 case kRegRegStore: return true; 587 case kRegImm: return true; 588 case kRegRegImm: return true; 589 case kRegRegImmStore: return true; 590 case kShiftRegImm: return true; 591 case kShiftRegCl: return true; 592 case kRegCond: return true; 593 case kRegRegCond: return true; 594 case kJmp: 595 switch (entry->opcode) { 596 case kX86JmpR: return true; 597 default: return false; 598 } 599 case kCall: 600 switch (entry->opcode) { 601 case kX86CallR: return true; 602 default: return false; 603 } 604 default: return false; 605 } 606 } 607 608 static bool IsByteSecondOperand(const X86EncodingMap* entry) { 609 return StartsWith(entry->name, "Movzx8") || StartsWith(entry->name, "Movsx8"); 610 } 611 612 size_t X86Mir2Lir::ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, 613 int32_t raw_base, int32_t displacement) { 614 bool has_modrm = HasModrm(entry); 615 bool has_sib = HasSib(entry); 616 bool r8_form = entry->skeleton.r8_form; 617 bool modrm_is_reg_reg = ModrmIsRegReg(entry); 618 if (has_sib) { 619 DCHECK(!modrm_is_reg_reg); 620 } 621 size_t size = 0; 622 if (entry->skeleton.prefix1 > 0) { 623 ++size; 624 if (entry->skeleton.prefix2 > 0) { 625 ++size; 626 } 627 } 628 if (cu_->target64 || kIsDebugBuild) { 629 bool registers_need_rex_prefix = NeedsRex(raw_reg) || NeedsRex(raw_index) || NeedsRex(raw_base); 630 if (r8_form) { 631 // Do we need an empty REX prefix to normalize byte registers? 632 registers_need_rex_prefix = registers_need_rex_prefix || 633 (RegStorage::RegNum(raw_reg) >= 4 && !IsByteSecondOperand(entry)); 634 registers_need_rex_prefix = registers_need_rex_prefix || 635 (modrm_is_reg_reg && (RegStorage::RegNum(raw_base) >= 4)); 636 } 637 if (registers_need_rex_prefix) { 638 DCHECK(cu_->target64) << "Attempt to use a 64-bit only addressable register " 639 << RegStorage::RegNum(raw_reg) << " with instruction " << entry->name; 640 if (entry->skeleton.prefix1 != REX_W && entry->skeleton.prefix2 != REX_W 641 && entry->skeleton.prefix1 != REX && entry->skeleton.prefix2 != REX) { 642 ++size; // rex 643 } 644 } 645 } 646 ++size; // opcode 647 if (entry->skeleton.opcode == 0x0F) { 648 ++size; 649 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 650 ++size; 651 } 652 } 653 if (has_modrm) { 654 ++size; // modrm 655 } 656 if (!modrm_is_reg_reg) { 657 if (has_sib || LowRegisterBits(raw_base) == rs_rX86_SP.GetRegNum() 658 || (cu_->target64 && entry->skeleton.prefix1 == THREAD_PREFIX)) { 659 // SP requires a SIB byte. 660 // GS access also needs a SIB byte for absolute adressing in 64-bit mode. 661 ++size; 662 } 663 if (displacement != 0 || LowRegisterBits(raw_base) == rs_rBP.GetRegNum()) { 664 // BP requires an explicit displacement, even when it's 0. 665 if (entry->opcode != kX86Lea32RA && entry->opcode != kX86Lea64RA) { 666 DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), UINT64_C(0)) << entry->name; 667 } 668 size += IS_SIMM8(displacement) ? 1 : 4; 669 } 670 } 671 size += entry->skeleton.immediate_bytes; 672 return size; 673 } 674 675 size_t X86Mir2Lir::GetInsnSize(LIR* lir) { 676 DCHECK(!IsPseudoLirOp(lir->opcode)); 677 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 678 DCHECK_EQ(entry->opcode, lir->opcode) << entry->name; 679 680 switch (entry->kind) { 681 case kData: 682 return 4; // 4 bytes of data. 683 case kNop: 684 return lir->operands[0]; // Length of nop is sole operand. 685 case kNullary: 686 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0); 687 case kRegOpcode: // lir operands - 0: reg 688 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); 689 case kReg: // lir operands - 0: reg 690 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); 691 case kMem: // lir operands - 0: base, 1: disp 692 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 693 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp 694 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); 695 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg 696 return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]); 697 case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate 698 return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]); 699 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 700 return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0], 701 lir->operands[3]); 702 case kThreadReg: // lir operands - 0: disp, 1: reg 703 // Thread displacement size is always 32bit. 704 return ComputeSize(entry, lir->operands[1], NO_REG, NO_REG, 0x12345678); 705 case kRegReg: // lir operands - 0: reg1, 1: reg2 706 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0); 707 case kRegRegStore: // lir operands - 0: reg2, 1: reg1 708 return ComputeSize(entry, lir->operands[1], NO_REG, lir->operands[0], 0); 709 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp 710 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]); 711 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 712 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], 713 lir->operands[4]); 714 case kRegThread: // lir operands - 0: reg, 1: disp 715 // Thread displacement size is always 32bit. 716 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0x12345678); 717 case kRegImm: { // lir operands - 0: reg, 1: immediate 718 size_t size = ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0); 719 // AX opcodes don't require the modrm byte. 720 if (entry->skeleton.ax_opcode == 0) { 721 return size; 722 } else { 723 return size - (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); 724 } 725 } 726 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate 727 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 728 case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 729 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); 730 case kThreadImm: // lir operands - 0: disp, 1: imm 731 // Thread displacement size is always 32bit. 732 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678); 733 case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm 734 // Note: RegRegImm form passes reg2 as index but encodes it using base. 735 return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, 0); 736 case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm 737 // Note: RegRegImmStore form passes reg1 as index but encodes it using base. 738 return ComputeSize(entry, lir->operands[1], lir->operands[0], NO_REG, 0); 739 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm 740 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]); 741 case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm 742 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], 743 lir->operands[4]); 744 case kMovRegImm: // lir operands - 0: reg, 1: immediate 745 case kMovRegQuadImm: 746 return ((entry->skeleton.prefix1 != 0 || NeedsRex(lir->operands[0])) ? 1 : 0) + 1 + 747 entry->skeleton.immediate_bytes; 748 case kShiftRegImm: // lir operands - 0: reg, 1: immediate 749 // Shift by immediate one has a shorter opcode. 750 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0) - 751 (lir->operands[1] == 1 ? 1 : 0); 752 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate 753 // Shift by immediate one has a shorter opcode. 754 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]) - 755 (lir->operands[2] == 1 ? 1 : 0); 756 case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 757 // Shift by immediate one has a shorter opcode. 758 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]) - 759 (lir->operands[4] == 1 ? 1 : 0); 760 case kShiftRegCl: // lir operands - 0: reg, 1: cl 761 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[1])); 762 // Note: ShiftRegCl form passes reg as reg but encodes it using base. 763 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0); 764 case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl 765 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[2])); 766 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 767 case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cl 768 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[4])); 769 return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0], 770 lir->operands[3]); 771 case kRegCond: // lir operands - 0: reg, 1: cond 772 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); 773 case kMemCond: // lir operands - 0: base, 1: disp, 2: cond 774 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 775 case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond 776 DCHECK_EQ(false, entry->skeleton.r8_form); 777 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); 778 case kRegRegCond: // lir operands - 0: reg1, 1: reg2, 2: cond 779 DCHECK_EQ(false, entry->skeleton.r8_form); 780 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0); 781 case kRegMemCond: // lir operands - 0: reg, 1: base, 2: disp, 3:cond 782 DCHECK_EQ(false, entry->skeleton.r8_form); 783 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]); 784 case kJcc: 785 if (lir->opcode == kX86Jcc8) { 786 return 2; // opcode + rel8 787 } else { 788 DCHECK(lir->opcode == kX86Jcc32); 789 return 6; // 2 byte opcode + rel32 790 } 791 case kJmp: 792 if (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jecxz8) { 793 return 2; // opcode + rel8 794 } else if (lir->opcode == kX86Jmp32) { 795 return 5; // opcode + rel32 796 } else if (lir->opcode == kX86JmpT) { 797 // Thread displacement size is always 32bit. 798 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678); 799 } else { 800 DCHECK(lir->opcode == kX86JmpR); 801 if (NeedsRex(lir->operands[0])) { 802 return 3; // REX.B + opcode + modrm 803 } else { 804 return 2; // opcode + modrm 805 } 806 } 807 case kCall: 808 switch (lir->opcode) { 809 case kX86CallI: return 5; // opcode 0:disp 810 case kX86CallR: return 2; // opcode modrm 811 case kX86CallM: // lir operands - 0: base, 1: disp 812 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 813 case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp 814 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); 815 case kX86CallT: // lir operands - 0: disp 816 // Thread displacement size is always 32bit. 817 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678); 818 default: 819 break; 820 } 821 break; 822 case kPcRel: 823 if (entry->opcode == kX86PcRelLoadRA) { 824 // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table 825 // Force the displacement size to 32bit, it will hold a computed offset later. 826 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], 827 0x12345678); 828 } else { 829 DCHECK_EQ(entry->opcode, kX86PcRelAdr); 830 return 5; // opcode with reg + 4 byte immediate 831 } 832 case kMacro: // lir operands - 0: reg 833 DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod)); 834 return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ + 835 ComputeSize(&X86Mir2Lir::EncodingMap[cu_->target64 ? kX86Sub64RI : kX86Sub32RI], 836 lir->operands[0], NO_REG, NO_REG, 0) - 837 // Shorter ax encoding. 838 (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); 839 case kUnimplemented: 840 break; 841 } 842 UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name; 843 return 0; 844 } 845 846 static uint8_t ModrmForDisp(int base, int disp) { 847 // BP requires an explicit disp, so do not omit it in the 0 case 848 if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) { 849 return 0; 850 } else if (IS_SIMM8(disp)) { 851 return 1; 852 } else { 853 return 2; 854 } 855 } 856 857 void X86Mir2Lir::CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg) { 858 if (kIsDebugBuild) { 859 // Sanity check r8_form is correctly specified. 860 if (entry->skeleton.r8_form) { 861 CHECK(strchr(entry->name, '8') != nullptr) << entry->name; 862 } else { 863 if (entry->skeleton.immediate_bytes != 1) { // Ignore ...I8 instructions. 864 if (!StartsWith(entry->name, "Movzx8") && !StartsWith(entry->name, "Movsx8") 865 && !StartsWith(entry->name, "Movzx8q") && !StartsWith(entry->name, "Movsx8q")) { 866 CHECK(strchr(entry->name, '8') == nullptr) << entry->name; 867 } 868 } 869 } 870 if (RegStorage::RegNum(raw_reg) >= 4) { 871 // ah, bh, ch and dh are not valid registers in 32-bit. 872 CHECK(cu_->target64 || !entry->skeleton.r8_form) 873 << "Invalid register " << static_cast<int>(RegStorage::RegNum(raw_reg)) 874 << " for instruction " << entry->name << " in " 875 << PrettyMethod(cu_->method_idx, *cu_->dex_file); 876 } 877 } 878 } 879 880 void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry, 881 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b) { 882 // REX.WRXB 883 // W - 64-bit operand 884 // R - MODRM.reg 885 // X - SIB.index 886 // B - MODRM.rm/SIB.base 887 bool w = (entry->skeleton.prefix1 == REX_W) || (entry->skeleton.prefix2 == REX_W); 888 bool r = NeedsRex(raw_reg_r); 889 bool x = NeedsRex(raw_reg_x); 890 bool b = NeedsRex(raw_reg_b); 891 bool r8_form = entry->skeleton.r8_form; 892 bool modrm_is_reg_reg = ModrmIsRegReg(entry); 893 894 uint8_t rex = 0; 895 if (r8_form) { 896 // Do we need an empty REX prefix to normalize byte register addressing? 897 if (RegStorage::RegNum(raw_reg_r) >= 4 && !IsByteSecondOperand(entry)) { 898 rex |= 0x40; // REX.0000 899 } else if (modrm_is_reg_reg && RegStorage::RegNum(raw_reg_b) >= 4) { 900 rex |= 0x40; // REX.0000 901 } 902 } 903 if (w) { 904 rex |= 0x48; // REX.W000 905 } 906 if (r) { 907 rex |= 0x44; // REX.0R00 908 } 909 if (x) { 910 rex |= 0x42; // REX.00X0 911 } 912 if (b) { 913 rex |= 0x41; // REX.000B 914 } 915 if (entry->skeleton.prefix1 != 0) { 916 if (cu_->target64 && entry->skeleton.prefix1 == THREAD_PREFIX) { 917 // 64 bit addresses by GS, not FS. 918 code_buffer_.push_back(THREAD_PREFIX_GS); 919 } else { 920 if (entry->skeleton.prefix1 == REX_W || entry->skeleton.prefix1 == REX) { 921 DCHECK(cu_->target64); 922 rex |= entry->skeleton.prefix1; 923 code_buffer_.push_back(rex); 924 rex = 0; 925 } else { 926 code_buffer_.push_back(entry->skeleton.prefix1); 927 } 928 } 929 if (entry->skeleton.prefix2 != 0) { 930 if (entry->skeleton.prefix2 == REX_W || entry->skeleton.prefix1 == REX) { 931 DCHECK(cu_->target64); 932 rex |= entry->skeleton.prefix2; 933 code_buffer_.push_back(rex); 934 rex = 0; 935 } else { 936 code_buffer_.push_back(entry->skeleton.prefix2); 937 } 938 } 939 } else { 940 DCHECK_EQ(0, entry->skeleton.prefix2); 941 } 942 if (rex != 0) { 943 DCHECK(cu_->target64); 944 code_buffer_.push_back(rex); 945 } 946 } 947 948 void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) { 949 code_buffer_.push_back(entry->skeleton.opcode); 950 if (entry->skeleton.opcode == 0x0F) { 951 code_buffer_.push_back(entry->skeleton.extra_opcode1); 952 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 953 code_buffer_.push_back(entry->skeleton.extra_opcode2); 954 } else { 955 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 956 } 957 } else { 958 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 959 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 960 } 961 } 962 963 void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry, 964 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b) { 965 EmitPrefix(entry, raw_reg_r, raw_reg_x, raw_reg_b); 966 EmitOpcode(entry); 967 } 968 969 void X86Mir2Lir::EmitDisp(uint8_t base, int32_t disp) { 970 // BP requires an explicit disp, so do not omit it in the 0 case 971 if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) { 972 return; 973 } else if (IS_SIMM8(disp)) { 974 code_buffer_.push_back(disp & 0xFF); 975 } else { 976 code_buffer_.push_back(disp & 0xFF); 977 code_buffer_.push_back((disp >> 8) & 0xFF); 978 code_buffer_.push_back((disp >> 16) & 0xFF); 979 code_buffer_.push_back((disp >> 24) & 0xFF); 980 } 981 } 982 983 void X86Mir2Lir::EmitModrmThread(uint8_t reg_or_opcode) { 984 if (cu_->target64) { 985 // Absolute adressing for GS access. 986 uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rX86_SP.GetRegNum(); 987 code_buffer_.push_back(modrm); 988 uint8_t sib = (0/*TIMES_1*/ << 6) | (rs_rX86_SP.GetRegNum() << 3) | rs_rBP.GetRegNum(); 989 code_buffer_.push_back(sib); 990 } else { 991 uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rBP.GetRegNum(); 992 code_buffer_.push_back(modrm); 993 } 994 } 995 996 void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp) { 997 DCHECK_LT(reg_or_opcode, 8); 998 DCHECK_LT(base, 8); 999 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base; 1000 code_buffer_.push_back(modrm); 1001 if (base == rs_rX86_SP.GetRegNum()) { 1002 // Special SIB for SP base 1003 code_buffer_.push_back(0 << 6 | rs_rX86_SP.GetRegNum() << 3 | rs_rX86_SP.GetRegNum()); 1004 } 1005 EmitDisp(base, disp); 1006 } 1007 1008 void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, 1009 int scale, int32_t disp) { 1010 DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8); 1011 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | RegStorage::RegNum(reg_or_opcode) << 3 | 1012 rs_rX86_SP.GetRegNum(); 1013 code_buffer_.push_back(modrm); 1014 DCHECK_LT(scale, 4); 1015 DCHECK_LT(RegStorage::RegNum(index), 8); 1016 DCHECK_LT(RegStorage::RegNum(base), 8); 1017 uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base); 1018 code_buffer_.push_back(sib); 1019 EmitDisp(base, disp); 1020 } 1021 1022 void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int64_t imm) { 1023 switch (entry->skeleton.immediate_bytes) { 1024 case 1: 1025 DCHECK(IS_SIMM8(imm)); 1026 code_buffer_.push_back(imm & 0xFF); 1027 break; 1028 case 2: 1029 DCHECK(IS_SIMM16(imm)); 1030 code_buffer_.push_back(imm & 0xFF); 1031 code_buffer_.push_back((imm >> 8) & 0xFF); 1032 break; 1033 case 4: 1034 DCHECK(IS_SIMM32(imm)); 1035 code_buffer_.push_back(imm & 0xFF); 1036 code_buffer_.push_back((imm >> 8) & 0xFF); 1037 code_buffer_.push_back((imm >> 16) & 0xFF); 1038 code_buffer_.push_back((imm >> 24) & 0xFF); 1039 break; 1040 case 8: 1041 code_buffer_.push_back(imm & 0xFF); 1042 code_buffer_.push_back((imm >> 8) & 0xFF); 1043 code_buffer_.push_back((imm >> 16) & 0xFF); 1044 code_buffer_.push_back((imm >> 24) & 0xFF); 1045 code_buffer_.push_back((imm >> 32) & 0xFF); 1046 code_buffer_.push_back((imm >> 40) & 0xFF); 1047 code_buffer_.push_back((imm >> 48) & 0xFF); 1048 code_buffer_.push_back((imm >> 56) & 0xFF); 1049 break; 1050 default: 1051 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes 1052 << ") for instruction: " << entry->name; 1053 break; 1054 } 1055 } 1056 1057 void X86Mir2Lir::EmitNullary(const X86EncodingMap* entry) { 1058 DCHECK_EQ(false, entry->skeleton.r8_form); 1059 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); 1060 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1061 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1062 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1063 } 1064 1065 void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg) { 1066 DCHECK_EQ(false, entry->skeleton.r8_form); 1067 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg); 1068 // There's no 3-byte instruction with +rd 1069 DCHECK(entry->skeleton.opcode != 0x0F || 1070 (entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A)); 1071 DCHECK(!RegStorage::IsFloat(raw_reg)); 1072 uint8_t low_reg = LowRegisterBits(raw_reg); 1073 code_buffer_.back() += low_reg; 1074 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1075 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1076 } 1077 1078 void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg) { 1079 CheckValidByteRegister(entry, raw_reg); 1080 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg); 1081 uint8_t low_reg = LowRegisterBits(raw_reg); 1082 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1083 code_buffer_.push_back(modrm); 1084 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1085 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1086 } 1087 1088 void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) { 1089 DCHECK_EQ(false, entry->skeleton.r8_form); 1090 EmitPrefix(entry, NO_REG, NO_REG, raw_base); 1091 code_buffer_.push_back(entry->skeleton.opcode); 1092 DCHECK_NE(0x0F, entry->skeleton.opcode); 1093 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1094 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1095 uint8_t low_base = LowRegisterBits(raw_base); 1096 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1097 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1098 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1099 } 1100 1101 void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, 1102 int scale, int32_t disp) { 1103 DCHECK_EQ(false, entry->skeleton.r8_form); 1104 EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base); 1105 uint8_t low_index = LowRegisterBits(raw_index); 1106 uint8_t low_base = LowRegisterBits(raw_base); 1107 EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp); 1108 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1109 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1110 } 1111 1112 void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, 1113 int32_t raw_reg) { 1114 CheckValidByteRegister(entry, raw_reg); 1115 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base); 1116 uint8_t low_reg = LowRegisterBits(raw_reg); 1117 uint8_t low_base = LowRegisterBits(raw_base); 1118 EmitModrmDisp(low_reg, low_base, disp); 1119 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1120 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1121 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1122 } 1123 1124 void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 1125 int32_t disp) { 1126 // Opcode will flip operands. 1127 EmitMemReg(entry, raw_base, disp, raw_reg); 1128 } 1129 1130 void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 1131 int32_t raw_index, int scale, int32_t disp) { 1132 CheckValidByteRegister(entry, raw_reg); 1133 EmitPrefixAndOpcode(entry, raw_reg, raw_index, raw_base); 1134 uint8_t low_reg = LowRegisterBits(raw_reg); 1135 uint8_t low_index = LowRegisterBits(raw_index); 1136 uint8_t low_base = LowRegisterBits(raw_base); 1137 EmitModrmSibDisp(low_reg, low_base, low_index, scale, disp); 1138 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1139 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1140 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1141 } 1142 1143 void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, 1144 int scale, int32_t disp, int32_t raw_reg) { 1145 // Opcode will flip operands. 1146 EmitRegArray(entry, raw_reg, raw_base, raw_index, scale, disp); 1147 } 1148 1149 void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, 1150 int32_t imm) { 1151 DCHECK_EQ(false, entry->skeleton.r8_form); 1152 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base); 1153 uint8_t low_base = LowRegisterBits(raw_base); 1154 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1155 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1156 EmitImm(entry, imm); 1157 } 1158 1159 void X86Mir2Lir::EmitArrayImm(const X86EncodingMap* entry, 1160 int32_t raw_base, int32_t raw_index, int scale, int32_t disp, 1161 int32_t imm) { 1162 DCHECK_EQ(false, entry->skeleton.r8_form); 1163 EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base); 1164 uint8_t low_index = LowRegisterBits(raw_index); 1165 uint8_t low_base = LowRegisterBits(raw_base); 1166 EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp); 1167 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1168 EmitImm(entry, imm); 1169 } 1170 1171 void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp) { 1172 DCHECK_EQ(false, entry->skeleton.r8_form); 1173 DCHECK_NE(entry->skeleton.prefix1, 0); 1174 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, NO_REG); 1175 uint8_t low_reg = LowRegisterBits(raw_reg); 1176 EmitModrmThread(low_reg); 1177 code_buffer_.push_back(disp & 0xFF); 1178 code_buffer_.push_back((disp >> 8) & 0xFF); 1179 code_buffer_.push_back((disp >> 16) & 0xFF); 1180 code_buffer_.push_back((disp >> 24) & 0xFF); 1181 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1182 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1183 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1184 } 1185 1186 void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2) { 1187 if (!IsByteSecondOperand(entry)) { 1188 CheckValidByteRegister(entry, raw_reg1); 1189 } 1190 CheckValidByteRegister(entry, raw_reg2); 1191 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); 1192 uint8_t low_reg1 = LowRegisterBits(raw_reg1); 1193 uint8_t low_reg2 = LowRegisterBits(raw_reg2); 1194 uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2; 1195 code_buffer_.push_back(modrm); 1196 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1197 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1198 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1199 } 1200 1201 void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, 1202 int32_t imm) { 1203 DCHECK_EQ(false, entry->skeleton.r8_form); 1204 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); 1205 uint8_t low_reg1 = LowRegisterBits(raw_reg1); 1206 uint8_t low_reg2 = LowRegisterBits(raw_reg2); 1207 uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2; 1208 code_buffer_.push_back(modrm); 1209 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1210 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1211 EmitImm(entry, imm); 1212 } 1213 1214 void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry, 1215 int32_t raw_reg, int32_t raw_base, int disp, int32_t imm) { 1216 DCHECK(!RegStorage::IsFloat(raw_reg)); 1217 CheckValidByteRegister(entry, raw_reg); 1218 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base); 1219 uint8_t low_reg = LowRegisterBits(raw_reg); 1220 uint8_t low_base = LowRegisterBits(raw_base); 1221 EmitModrmDisp(low_reg, low_base, disp); 1222 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1223 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1224 EmitImm(entry, imm); 1225 } 1226 1227 void X86Mir2Lir::EmitMemRegImm(const X86EncodingMap* entry, 1228 int32_t raw_base, int32_t disp, int32_t raw_reg, int32_t imm) { 1229 // Opcode will flip operands. 1230 EmitRegMemImm(entry, raw_reg, raw_base, disp, imm); 1231 } 1232 1233 void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) { 1234 CheckValidByteRegister(entry, raw_reg); 1235 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1236 if (RegStorage::RegNum(raw_reg) == rs_rAX.GetRegNum() && entry->skeleton.ax_opcode != 0) { 1237 code_buffer_.push_back(entry->skeleton.ax_opcode); 1238 } else { 1239 uint8_t low_reg = LowRegisterBits(raw_reg); 1240 EmitOpcode(entry); 1241 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1242 code_buffer_.push_back(modrm); 1243 } 1244 EmitImm(entry, imm); 1245 } 1246 1247 void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm) { 1248 DCHECK_EQ(false, entry->skeleton.r8_form); 1249 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); 1250 EmitModrmThread(entry->skeleton.modrm_opcode); 1251 code_buffer_.push_back(disp & 0xFF); 1252 code_buffer_.push_back((disp >> 8) & 0xFF); 1253 code_buffer_.push_back((disp >> 16) & 0xFF); 1254 code_buffer_.push_back((disp >> 24) & 0xFF); 1255 EmitImm(entry, imm); 1256 DCHECK_EQ(entry->skeleton.ax_opcode, 0); 1257 } 1258 1259 void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm) { 1260 DCHECK_EQ(false, entry->skeleton.r8_form); 1261 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1262 uint8_t low_reg = LowRegisterBits(raw_reg); 1263 code_buffer_.push_back(0xB8 + low_reg); 1264 switch (entry->skeleton.immediate_bytes) { 1265 case 4: 1266 code_buffer_.push_back(imm & 0xFF); 1267 code_buffer_.push_back((imm >> 8) & 0xFF); 1268 code_buffer_.push_back((imm >> 16) & 0xFF); 1269 code_buffer_.push_back((imm >> 24) & 0xFF); 1270 break; 1271 case 8: 1272 code_buffer_.push_back(imm & 0xFF); 1273 code_buffer_.push_back((imm >> 8) & 0xFF); 1274 code_buffer_.push_back((imm >> 16) & 0xFF); 1275 code_buffer_.push_back((imm >> 24) & 0xFF); 1276 code_buffer_.push_back((imm >> 32) & 0xFF); 1277 code_buffer_.push_back((imm >> 40) & 0xFF); 1278 code_buffer_.push_back((imm >> 48) & 0xFF); 1279 code_buffer_.push_back((imm >> 56) & 0xFF); 1280 break; 1281 default: 1282 LOG(FATAL) << "Unsupported immediate size for EmitMovRegImm: " 1283 << static_cast<uint32_t>(entry->skeleton.immediate_bytes); 1284 } 1285 } 1286 1287 void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) { 1288 CheckValidByteRegister(entry, raw_reg); 1289 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1290 if (imm != 1) { 1291 code_buffer_.push_back(entry->skeleton.opcode); 1292 } else { 1293 // Shorter encoding for 1 bit shift 1294 code_buffer_.push_back(entry->skeleton.ax_opcode); 1295 } 1296 DCHECK_NE(0x0F, entry->skeleton.opcode); 1297 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1298 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1299 uint8_t low_reg = LowRegisterBits(raw_reg); 1300 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1301 code_buffer_.push_back(modrm); 1302 if (imm != 1) { 1303 DCHECK_EQ(entry->skeleton.immediate_bytes, 1); 1304 DCHECK(IS_SIMM8(imm)); 1305 code_buffer_.push_back(imm & 0xFF); 1306 } 1307 } 1308 1309 void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl) { 1310 CheckValidByteRegister(entry, raw_reg); 1311 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl)); 1312 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1313 code_buffer_.push_back(entry->skeleton.opcode); 1314 DCHECK_NE(0x0F, entry->skeleton.opcode); 1315 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1316 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1317 uint8_t low_reg = LowRegisterBits(raw_reg); 1318 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1319 code_buffer_.push_back(modrm); 1320 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1321 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1322 } 1323 1324 void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, 1325 int32_t displacement, int32_t raw_cl) { 1326 DCHECK_EQ(false, entry->skeleton.r8_form); 1327 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl)); 1328 EmitPrefix(entry, NO_REG, NO_REG, raw_base); 1329 code_buffer_.push_back(entry->skeleton.opcode); 1330 DCHECK_NE(0x0F, entry->skeleton.opcode); 1331 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1332 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1333 uint8_t low_base = LowRegisterBits(raw_base); 1334 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, displacement); 1335 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1336 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1337 } 1338 1339 void X86Mir2Lir::EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, 1340 int32_t imm) { 1341 DCHECK_EQ(false, entry->skeleton.r8_form); 1342 EmitPrefix(entry, NO_REG, NO_REG, raw_base); 1343 if (imm != 1) { 1344 code_buffer_.push_back(entry->skeleton.opcode); 1345 } else { 1346 // Shorter encoding for 1 bit shift 1347 code_buffer_.push_back(entry->skeleton.ax_opcode); 1348 } 1349 DCHECK_NE(0x0F, entry->skeleton.opcode); 1350 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1351 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1352 uint8_t low_base = LowRegisterBits(raw_base); 1353 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1354 if (imm != 1) { 1355 DCHECK_EQ(entry->skeleton.immediate_bytes, 1); 1356 DCHECK(IS_SIMM8(imm)); 1357 code_buffer_.push_back(imm & 0xFF); 1358 } 1359 } 1360 1361 void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc) { 1362 CheckValidByteRegister(entry, raw_reg); 1363 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1364 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1365 DCHECK_EQ(0x0F, entry->skeleton.opcode); 1366 code_buffer_.push_back(0x0F); 1367 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); 1368 DCHECK_GE(cc, 0); 1369 DCHECK_LT(cc, 16); 1370 code_buffer_.push_back(0x90 | cc); 1371 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1372 uint8_t low_reg = LowRegisterBits(raw_reg); 1373 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1374 code_buffer_.push_back(modrm); 1375 DCHECK_EQ(entry->skeleton.immediate_bytes, 0); 1376 } 1377 1378 void X86Mir2Lir::EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, 1379 int32_t cc) { 1380 DCHECK_EQ(false, entry->skeleton.r8_form); 1381 if (entry->skeleton.prefix1 != 0) { 1382 code_buffer_.push_back(entry->skeleton.prefix1); 1383 if (entry->skeleton.prefix2 != 0) { 1384 code_buffer_.push_back(entry->skeleton.prefix2); 1385 } 1386 } else { 1387 DCHECK_EQ(0, entry->skeleton.prefix2); 1388 } 1389 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1390 DCHECK_EQ(0x0F, entry->skeleton.opcode); 1391 code_buffer_.push_back(0x0F); 1392 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); 1393 DCHECK_GE(cc, 0); 1394 DCHECK_LT(cc, 16); 1395 code_buffer_.push_back(0x90 | cc); 1396 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1397 uint8_t low_base = LowRegisterBits(raw_base); 1398 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1399 DCHECK_EQ(entry->skeleton.immediate_bytes, 0); 1400 } 1401 1402 void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, 1403 int32_t cc) { 1404 // Generate prefix and opcode without the condition. 1405 DCHECK_EQ(false, entry->skeleton.r8_form); 1406 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); 1407 1408 // Now add the condition. The last byte of opcode is the one that receives it. 1409 DCHECK_GE(cc, 0); 1410 DCHECK_LT(cc, 16); 1411 code_buffer_.back() += cc; 1412 1413 // Not expecting to have to encode immediate or do anything special for ModR/M since there are 1414 // two registers. 1415 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1416 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1417 1418 // For register to register encoding, the mod is 3. 1419 const uint8_t mod = (3 << 6); 1420 1421 // Encode the ModR/M byte now. 1422 uint8_t low_reg1 = LowRegisterBits(raw_reg1); 1423 uint8_t low_reg2 = LowRegisterBits(raw_reg2); 1424 const uint8_t modrm = mod | (low_reg1 << 3) | low_reg2; 1425 code_buffer_.push_back(modrm); 1426 } 1427 1428 void X86Mir2Lir::EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, 1429 int32_t disp, int32_t cc) { 1430 // Generate prefix and opcode without the condition. 1431 DCHECK_EQ(false, entry->skeleton.r8_form); 1432 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_base); 1433 1434 // Now add the condition. The last byte of opcode is the one that receives it. 1435 DCHECK_GE(cc, 0); 1436 DCHECK_LT(cc, 16); 1437 code_buffer_.back() += cc; 1438 1439 // Not expecting to have to encode immediate or do anything special for ModR/M since there are 1440 // two registers. 1441 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1442 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1443 1444 uint8_t low_reg1 = LowRegisterBits(raw_reg1); 1445 uint8_t low_base = LowRegisterBits(raw_base); 1446 EmitModrmDisp(low_reg1, low_base, disp); 1447 } 1448 1449 void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int32_t rel) { 1450 if (entry->opcode == kX86Jmp8) { 1451 DCHECK(IS_SIMM8(rel)); 1452 code_buffer_.push_back(0xEB); 1453 code_buffer_.push_back(rel & 0xFF); 1454 } else if (entry->opcode == kX86Jmp32) { 1455 code_buffer_.push_back(0xE9); 1456 code_buffer_.push_back(rel & 0xFF); 1457 code_buffer_.push_back((rel >> 8) & 0xFF); 1458 code_buffer_.push_back((rel >> 16) & 0xFF); 1459 code_buffer_.push_back((rel >> 24) & 0xFF); 1460 } else if (entry->opcode == kX86Jecxz8) { 1461 DCHECK(IS_SIMM8(rel)); 1462 code_buffer_.push_back(0xE3); 1463 code_buffer_.push_back(rel & 0xFF); 1464 } else { 1465 DCHECK(entry->opcode == kX86JmpR); 1466 DCHECK_EQ(false, entry->skeleton.r8_form); 1467 EmitPrefix(entry, NO_REG, NO_REG, rel); 1468 code_buffer_.push_back(entry->skeleton.opcode); 1469 uint8_t low_reg = LowRegisterBits(rel); 1470 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1471 code_buffer_.push_back(modrm); 1472 } 1473 } 1474 1475 void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc) { 1476 DCHECK_GE(cc, 0); 1477 DCHECK_LT(cc, 16); 1478 if (entry->opcode == kX86Jcc8) { 1479 DCHECK(IS_SIMM8(rel)); 1480 code_buffer_.push_back(0x70 | cc); 1481 code_buffer_.push_back(rel & 0xFF); 1482 } else { 1483 DCHECK(entry->opcode == kX86Jcc32); 1484 code_buffer_.push_back(0x0F); 1485 code_buffer_.push_back(0x80 | cc); 1486 code_buffer_.push_back(rel & 0xFF); 1487 code_buffer_.push_back((rel >> 8) & 0xFF); 1488 code_buffer_.push_back((rel >> 16) & 0xFF); 1489 code_buffer_.push_back((rel >> 24) & 0xFF); 1490 } 1491 } 1492 1493 void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) { 1494 DCHECK_EQ(false, entry->skeleton.r8_form); 1495 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base); 1496 uint8_t low_base = LowRegisterBits(raw_base); 1497 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1498 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1499 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1500 } 1501 1502 void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int32_t disp) { 1503 DCHECK_EQ(false, entry->skeleton.r8_form); 1504 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); 1505 DCHECK_EQ(4, entry->skeleton.immediate_bytes); 1506 code_buffer_.push_back(disp & 0xFF); 1507 code_buffer_.push_back((disp >> 8) & 0xFF); 1508 code_buffer_.push_back((disp >> 16) & 0xFF); 1509 code_buffer_.push_back((disp >> 24) & 0xFF); 1510 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1511 } 1512 1513 void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int32_t disp) { 1514 DCHECK_EQ(false, entry->skeleton.r8_form); 1515 DCHECK_NE(entry->skeleton.prefix1, 0); 1516 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); 1517 EmitModrmThread(entry->skeleton.modrm_opcode); 1518 code_buffer_.push_back(disp & 0xFF); 1519 code_buffer_.push_back((disp >> 8) & 0xFF); 1520 code_buffer_.push_back((disp >> 16) & 0xFF); 1521 code_buffer_.push_back((disp >> 24) & 0xFF); 1522 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1523 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1524 } 1525 1526 void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, 1527 int32_t raw_index, int scale, int32_t table_or_disp) { 1528 int disp; 1529 if (entry->opcode == kX86PcRelLoadRA) { 1530 Mir2Lir::EmbeddedData *tab_rec = 1531 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp)); 1532 disp = tab_rec->offset; 1533 } else { 1534 DCHECK(entry->opcode == kX86PcRelAdr); 1535 Mir2Lir::EmbeddedData *tab_rec = 1536 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(raw_base_or_table)); 1537 disp = tab_rec->offset; 1538 } 1539 if (entry->opcode == kX86PcRelLoadRA) { 1540 DCHECK_EQ(false, entry->skeleton.r8_form); 1541 EmitPrefix(entry, raw_reg, raw_index, raw_base_or_table); 1542 code_buffer_.push_back(entry->skeleton.opcode); 1543 DCHECK_NE(0x0F, entry->skeleton.opcode); 1544 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1545 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1546 uint8_t low_reg = LowRegisterBits(raw_reg); 1547 uint8_t modrm = (2 << 6) | (low_reg << 3) | rs_rX86_SP.GetRegNum(); 1548 code_buffer_.push_back(modrm); 1549 DCHECK_LT(scale, 4); 1550 uint8_t low_base_or_table = LowRegisterBits(raw_base_or_table); 1551 uint8_t low_index = LowRegisterBits(raw_index); 1552 uint8_t sib = (scale << 6) | (low_index << 3) | low_base_or_table; 1553 code_buffer_.push_back(sib); 1554 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1555 } else { 1556 uint8_t low_reg = LowRegisterBits(raw_reg); 1557 code_buffer_.push_back(entry->skeleton.opcode + low_reg); 1558 } 1559 code_buffer_.push_back(disp & 0xFF); 1560 code_buffer_.push_back((disp >> 8) & 0xFF); 1561 code_buffer_.push_back((disp >> 16) & 0xFF); 1562 code_buffer_.push_back((disp >> 24) & 0xFF); 1563 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1564 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1565 } 1566 1567 void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset) { 1568 DCHECK_EQ(entry->opcode, kX86StartOfMethod) << entry->name; 1569 DCHECK_EQ(false, entry->skeleton.r8_form); 1570 EmitPrefix(entry, raw_reg, NO_REG, NO_REG); 1571 code_buffer_.push_back(0xE8); // call +0 1572 code_buffer_.push_back(0); 1573 code_buffer_.push_back(0); 1574 code_buffer_.push_back(0); 1575 code_buffer_.push_back(0); 1576 1577 uint8_t low_reg = LowRegisterBits(raw_reg); 1578 code_buffer_.push_back(0x58 + low_reg); // pop reg 1579 1580 EmitRegImm(&X86Mir2Lir::EncodingMap[cu_->target64 ? kX86Sub64RI : kX86Sub32RI], 1581 raw_reg, offset + 5 /* size of call +0 */); 1582 } 1583 1584 void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) { 1585 UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " 1586 << BuildInsnString(entry->fmt, lir, 0); 1587 for (size_t i = 0; i < GetInsnSize(lir); ++i) { 1588 code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3 1589 } 1590 } 1591 1592 /* 1593 * Assemble the LIR into binary instruction format. Note that we may 1594 * discover that pc-relative displacements may not fit the selected 1595 * instruction. In those cases we will try to substitute a new code 1596 * sequence or request that the trace be shortened and retried. 1597 */ 1598 AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) { 1599 LIR *lir; 1600 AssemblerStatus res = kSuccess; // Assume success 1601 1602 const bool kVerbosePcFixup = false; 1603 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { 1604 if (IsPseudoLirOp(lir->opcode)) { 1605 continue; 1606 } 1607 1608 if (lir->flags.is_nop) { 1609 continue; 1610 } 1611 1612 if (lir->flags.fixup != kFixupNone) { 1613 switch (lir->opcode) { 1614 case kX86Jcc8: { 1615 LIR *target_lir = lir->target; 1616 DCHECK(target_lir != NULL); 1617 int delta = 0; 1618 CodeOffset pc; 1619 if (IS_SIMM8(lir->operands[0])) { 1620 pc = lir->offset + 2 /* opcode + rel8 */; 1621 } else { 1622 pc = lir->offset + 6 /* 2 byte opcode + rel32 */; 1623 } 1624 CodeOffset target = target_lir->offset; 1625 delta = target - pc; 1626 if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { 1627 if (kVerbosePcFixup) { 1628 LOG(INFO) << "Retry for JCC growth at " << lir->offset 1629 << " delta: " << delta << " old delta: " << lir->operands[0]; 1630 } 1631 lir->opcode = kX86Jcc32; 1632 lir->flags.size = GetInsnSize(lir); 1633 DCHECK(lir->u.m.def_mask->Equals(kEncodeAll)); 1634 DCHECK(lir->u.m.use_mask->Equals(kEncodeAll)); 1635 res = kRetryAll; 1636 } 1637 if (kVerbosePcFixup) { 1638 LOG(INFO) << "Source:"; 1639 DumpLIRInsn(lir, 0); 1640 LOG(INFO) << "Target:"; 1641 DumpLIRInsn(target_lir, 0); 1642 LOG(INFO) << "Delta " << delta; 1643 } 1644 lir->operands[0] = delta; 1645 break; 1646 } 1647 case kX86Jcc32: { 1648 LIR *target_lir = lir->target; 1649 DCHECK(target_lir != NULL); 1650 CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */; 1651 CodeOffset target = target_lir->offset; 1652 int delta = target - pc; 1653 if (kVerbosePcFixup) { 1654 LOG(INFO) << "Source:"; 1655 DumpLIRInsn(lir, 0); 1656 LOG(INFO) << "Target:"; 1657 DumpLIRInsn(target_lir, 0); 1658 LOG(INFO) << "Delta " << delta; 1659 } 1660 lir->operands[0] = delta; 1661 break; 1662 } 1663 case kX86Jecxz8: { 1664 LIR *target_lir = lir->target; 1665 DCHECK(target_lir != NULL); 1666 CodeOffset pc; 1667 pc = lir->offset + 2; // opcode + rel8 1668 CodeOffset target = target_lir->offset; 1669 int delta = target - pc; 1670 lir->operands[0] = delta; 1671 DCHECK(IS_SIMM8(delta)); 1672 break; 1673 } 1674 case kX86Jmp8: { 1675 LIR *target_lir = lir->target; 1676 DCHECK(target_lir != NULL); 1677 int delta = 0; 1678 CodeOffset pc; 1679 if (IS_SIMM8(lir->operands[0])) { 1680 pc = lir->offset + 2 /* opcode + rel8 */; 1681 } else { 1682 pc = lir->offset + 5 /* opcode + rel32 */; 1683 } 1684 CodeOffset target = target_lir->offset; 1685 delta = target - pc; 1686 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) { 1687 // Useless branch 1688 NopLIR(lir); 1689 if (kVerbosePcFixup) { 1690 LOG(INFO) << "Retry for useless branch at " << lir->offset; 1691 } 1692 res = kRetryAll; 1693 } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { 1694 if (kVerbosePcFixup) { 1695 LOG(INFO) << "Retry for JMP growth at " << lir->offset; 1696 } 1697 lir->opcode = kX86Jmp32; 1698 lir->flags.size = GetInsnSize(lir); 1699 DCHECK(lir->u.m.def_mask->Equals(kEncodeAll)); 1700 DCHECK(lir->u.m.use_mask->Equals(kEncodeAll)); 1701 res = kRetryAll; 1702 } 1703 lir->operands[0] = delta; 1704 break; 1705 } 1706 case kX86Jmp32: { 1707 LIR *target_lir = lir->target; 1708 DCHECK(target_lir != NULL); 1709 CodeOffset pc = lir->offset + 5 /* opcode + rel32 */; 1710 CodeOffset target = target_lir->offset; 1711 int delta = target - pc; 1712 lir->operands[0] = delta; 1713 break; 1714 } 1715 default: 1716 if (lir->flags.fixup == kFixupLoad) { 1717 LIR *target_lir = lir->target; 1718 DCHECK(target_lir != NULL); 1719 CodeOffset target = target_lir->offset; 1720 lir->operands[2] = target; 1721 int newSize = GetInsnSize(lir); 1722 if (newSize != lir->flags.size) { 1723 lir->flags.size = newSize; 1724 res = kRetryAll; 1725 } 1726 } 1727 break; 1728 } 1729 } 1730 1731 /* 1732 * If one of the pc-relative instructions expanded we'll have 1733 * to make another pass. Don't bother to fully assemble the 1734 * instruction. 1735 */ 1736 if (res != kSuccess) { 1737 continue; 1738 } 1739 CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size()); 1740 const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 1741 size_t starting_cbuf_size = code_buffer_.size(); 1742 switch (entry->kind) { 1743 case kData: // 4 bytes of data 1744 code_buffer_.push_back(lir->operands[0]); 1745 break; 1746 case kNullary: // 1 byte of opcode and possible prefixes. 1747 EmitNullary(entry); 1748 break; 1749 case kRegOpcode: // lir operands - 0: reg 1750 EmitOpRegOpcode(entry, lir->operands[0]); 1751 break; 1752 case kReg: // lir operands - 0: reg 1753 EmitOpReg(entry, lir->operands[0]); 1754 break; 1755 case kMem: // lir operands - 0: base, 1: disp 1756 EmitOpMem(entry, lir->operands[0], lir->operands[1]); 1757 break; 1758 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp 1759 EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]); 1760 break; 1761 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg 1762 EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1763 break; 1764 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate 1765 EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1766 break; 1767 case kArrayImm: // lir operands - 0: base, 1: index, 2: disp, 3:scale, 4:immediate 1768 EmitArrayImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1769 lir->operands[3], lir->operands[4]); 1770 break; 1771 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 1772 EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1773 lir->operands[3], lir->operands[4]); 1774 break; 1775 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp 1776 EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1777 break; 1778 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 1779 EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1780 lir->operands[3], lir->operands[4]); 1781 break; 1782 case kRegThread: // lir operands - 0: reg, 1: disp 1783 EmitRegThread(entry, lir->operands[0], lir->operands[1]); 1784 break; 1785 case kRegReg: // lir operands - 0: reg1, 1: reg2 1786 EmitRegReg(entry, lir->operands[0], lir->operands[1]); 1787 break; 1788 case kRegRegStore: // lir operands - 0: reg2, 1: reg1 1789 EmitRegReg(entry, lir->operands[1], lir->operands[0]); 1790 break; 1791 case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate 1792 EmitMemRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1793 lir->operands[3]); 1794 break; 1795 case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm 1796 EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1797 break; 1798 case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm 1799 EmitRegRegImm(entry, lir->operands[1], lir->operands[0], lir->operands[2]); 1800 break; 1801 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm 1802 EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1803 lir->operands[3]); 1804 break; 1805 case kRegImm: // lir operands - 0: reg, 1: immediate 1806 EmitRegImm(entry, lir->operands[0], lir->operands[1]); 1807 break; 1808 case kThreadImm: // lir operands - 0: disp, 1: immediate 1809 EmitThreadImm(entry, lir->operands[0], lir->operands[1]); 1810 break; 1811 case kMovRegImm: // lir operands - 0: reg, 1: immediate 1812 EmitMovRegImm(entry, lir->operands[0], lir->operands[1]); 1813 break; 1814 case kMovRegQuadImm: { 1815 int64_t value = static_cast<int64_t>(static_cast<int64_t>(lir->operands[1]) << 32 | 1816 static_cast<uint32_t>(lir->operands[2])); 1817 EmitMovRegImm(entry, lir->operands[0], value); 1818 } 1819 break; 1820 case kShiftRegImm: // lir operands - 0: reg, 1: immediate 1821 EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]); 1822 break; 1823 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2:immediate 1824 EmitShiftMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1825 break; 1826 case kShiftRegCl: // lir operands - 0: reg, 1: cl 1827 EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]); 1828 break; 1829 case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl 1830 EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1831 break; 1832 case kRegCond: // lir operands - 0: reg, 1: condition 1833 EmitRegCond(entry, lir->operands[0], lir->operands[1]); 1834 break; 1835 case kMemCond: // lir operands - 0: base, 1: displacement, 2: condition 1836 EmitMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1837 break; 1838 case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition 1839 EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1840 break; 1841 case kRegMemCond: // lir operands - 0: reg, 1: reg, displacement, 3: condition 1842 EmitRegMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1843 lir->operands[3]); 1844 break; 1845 case kJmp: // lir operands - 0: rel 1846 if (entry->opcode == kX86JmpT) { 1847 // This works since the instruction format for jmp and call is basically the same and 1848 // EmitCallThread loads opcode info. 1849 EmitCallThread(entry, lir->operands[0]); 1850 } else { 1851 EmitJmp(entry, lir->operands[0]); 1852 } 1853 break; 1854 case kJcc: // lir operands - 0: rel, 1: CC, target assigned 1855 EmitJcc(entry, lir->operands[0], lir->operands[1]); 1856 break; 1857 case kCall: 1858 switch (entry->opcode) { 1859 case kX86CallI: // lir operands - 0: disp 1860 EmitCallImmediate(entry, lir->operands[0]); 1861 break; 1862 case kX86CallM: // lir operands - 0: base, 1: disp 1863 EmitCallMem(entry, lir->operands[0], lir->operands[1]); 1864 break; 1865 case kX86CallT: // lir operands - 0: disp 1866 EmitCallThread(entry, lir->operands[0]); 1867 break; 1868 default: 1869 EmitUnimplemented(entry, lir); 1870 break; 1871 } 1872 break; 1873 case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table 1874 EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1875 lir->operands[3], lir->operands[4]); 1876 break; 1877 case kMacro: // lir operands - 0: reg 1878 EmitMacro(entry, lir->operands[0], lir->offset); 1879 break; 1880 case kNop: // TODO: these instruction kinds are missing implementations. 1881 case kThreadReg: 1882 case kRegArrayImm: 1883 case kShiftArrayImm: 1884 case kShiftArrayCl: 1885 case kArrayCond: 1886 case kUnimplemented: 1887 EmitUnimplemented(entry, lir); 1888 break; 1889 } 1890 DCHECK_EQ(lir->flags.size, GetInsnSize(lir)); 1891 CHECK_EQ(lir->flags.size, code_buffer_.size() - starting_cbuf_size) 1892 << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name; 1893 } 1894 return res; 1895 } 1896 1897 // LIR offset assignment. 1898 // TODO: consolidate w/ Arm assembly mechanism. 1899 int X86Mir2Lir::AssignInsnOffsets() { 1900 LIR* lir; 1901 int offset = 0; 1902 1903 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { 1904 lir->offset = offset; 1905 if (LIKELY(!IsPseudoLirOp(lir->opcode))) { 1906 if (!lir->flags.is_nop) { 1907 offset += lir->flags.size; 1908 } 1909 } else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) { 1910 if (offset & 0x2) { 1911 offset += 2; 1912 lir->operands[0] = 1; 1913 } else { 1914 lir->operands[0] = 0; 1915 } 1916 } 1917 /* Pseudo opcodes don't consume space */ 1918 } 1919 return offset; 1920 } 1921 1922 /* 1923 * Walk the compilation unit and assign offsets to instructions 1924 * and literals and compute the total size of the compiled unit. 1925 * TODO: consolidate w/ Arm assembly mechanism. 1926 */ 1927 void X86Mir2Lir::AssignOffsets() { 1928 int offset = AssignInsnOffsets(); 1929 1930 if (const_vectors_ != nullptr) { 1931 /* assign offsets to vector literals */ 1932 1933 // First, get offset to 12 mod 16 to align to 16 byte boundary. 1934 // This will ensure that the vector is 16 byte aligned, as the procedure is 1935 // always aligned at at 4 mod 16. 1936 int align_size = (16-4) - (offset & 0xF); 1937 if (align_size < 0) { 1938 align_size += 16; 1939 } 1940 1941 offset += align_size; 1942 1943 // Now assign each literal the right offset. 1944 for (LIR *p = const_vectors_; p != nullptr; p = p->next) { 1945 p->offset = offset; 1946 offset += 16; 1947 } 1948 } 1949 1950 /* Const values have to be word aligned */ 1951 offset = RoundUp(offset, 4); 1952 1953 /* Set up offsets for literals */ 1954 data_offset_ = offset; 1955 1956 offset = AssignLiteralOffset(offset); 1957 1958 offset = AssignSwitchTablesOffset(offset); 1959 1960 offset = AssignFillArrayDataOffset(offset); 1961 1962 total_size_ = offset; 1963 } 1964 1965 /* 1966 * Go over each instruction in the list and calculate the offset from the top 1967 * before sending them off to the assembler. If out-of-range branch distance is 1968 * seen rearrange the instructions a bit to correct it. 1969 * TODO: consolidate w/ Arm assembly mechanism. 1970 */ 1971 void X86Mir2Lir::AssembleLIR() { 1972 cu_->NewTimingSplit("Assemble"); 1973 1974 // We will remove the method address if we never ended up using it 1975 if (store_method_addr_ && !store_method_addr_used_) { 1976 setup_method_address_[0]->flags.is_nop = true; 1977 setup_method_address_[1]->flags.is_nop = true; 1978 } 1979 1980 AssignOffsets(); 1981 int assembler_retries = 0; 1982 /* 1983 * Assemble here. Note that we generate code with optimistic assumptions 1984 * and if found now to work, we'll have to redo the sequence and retry. 1985 */ 1986 1987 while (true) { 1988 AssemblerStatus res = AssembleInstructions(0); 1989 if (res == kSuccess) { 1990 break; 1991 } else { 1992 assembler_retries++; 1993 if (assembler_retries > MAX_ASSEMBLER_RETRIES) { 1994 CodegenDump(); 1995 LOG(FATAL) << "Assembler error - too many retries"; 1996 } 1997 // Redo offsets and try again 1998 AssignOffsets(); 1999 code_buffer_.clear(); 2000 } 2001 } 2002 2003 // Install literals 2004 InstallLiteralPools(); 2005 2006 // Install switch tables 2007 InstallSwitchTables(); 2008 2009 // Install fill array data 2010 InstallFillArrayData(); 2011 2012 // Create the mapping table and native offset to reference map. 2013 cu_->NewTimingSplit("PcMappingTable"); 2014 CreateMappingTables(); 2015 2016 cu_->NewTimingSplit("GcMap"); 2017 CreateNativeGcMap(); 2018 } 2019 2020 } // namespace art 2021
