| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 77 /* NOTE: must be kept in sync with enum MipsOpcode from LIR.h */
460 void MipsMir2Lir::ConvertShortToLongBranch(LIR* lir) {
463 int opcode = lir->opcode;
464 int dalvik_offset = lir->dalvik_offset;
482 LIR* hop_target = NULL;
485 LIR* hop_branch = RawLIR(dalvik_offset, opcode, lir->operands[0],
486 lir->operands[1], 0, 0, 0, hop_target);
487 InsertLIRBefore(lir, hop_branch)
516 LIR *lir; local
720 LIR* lir; local
[all...] |
| target_mips.cc | 146 void MipsMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags,
149 DCHECK(!lir->flags.use_def_invalid);
194 std::string MipsMir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) {
211 operand = lir->operands[nc-'0'];
245 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4 + (operand << 1),
246 lir->target);
252 int offset_1 = lir->operands[0];
253 int offset_2 = NEXT_LIR(lir)->operands[0]
[all...] |
| codegen_mips.h | 33 LIR* CheckSuspendUsingLoad() OVERRIDE;
35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
39 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
40 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
45 LIR* GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest);
46 LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src);
72 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE
[all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 78 /* NOTE: must be kept in sync with enum ArmOpcode from LIR.h */
1211 LIR* lir; local
[all...] |
| target_arm.cc | 162 void ArmMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags,
165 DCHECK(!lir->flags.use_def_invalid);
167 int opcode = lir->opcode;
182 def_mask->SetBits(EncodeArmRegList(lir->operands[0]));
186 def_mask->SetBits(EncodeArmRegList(lir->operands[1]));
190 def_mask->SetBits(EncodeArmRegList(lir->operands[0]));
194 for (int i = 0; i < lir->operands[2]; i++) {
195 SetupRegMask(def_mask, lir->operands[1] + i);
209 use_mask->SetBits(EncodeArmRegList(lir->operands[0]))
[all...] |
| codegen_arm.h | 33 LIR* CheckSuspendUsingLoad() OVERRIDE;
35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
39 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
40 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
68 uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset);
71 static uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir)
[all...] |
| utility_arm.cc | 72 LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) {
87 LIR* data_target = ScanLiteralPool(literal_list_, value, 0);
92 LIR* load_pc_rel = RawLIR(current_dalvik_offset_, kThumb2Vldrs,
173 LIR* ArmMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
174 LIR* res;
207 LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target) {
208 LIR* res = NewLIR1(kThumbBUncond, 0 /* offset to be patched during assembly */);
213 LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target)
836 LIR* lir = nullptr; local
[all...] |
| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | 1599 LIR *lir; local
1900 LIR* lir; local
[all...] |
| codegen_x86.h | 70 LIR* CheckSuspendUsingLoad() OVERRIDE;
72 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
74 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
76 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
77 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
78 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
80 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
131 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
132 void SetupTargetResourceMasks(LIR* lir, uint64_t flags
[all...] |
| fp_x86.cc | 153 LIR *fild64 = NewLIR2NoDest(kX86Fild64M, rs_rX86_SP.GetReg(),
161 LIR *fstp = NewLIR2NoDest(opcode, rs_rX86_SP.GetReg(), displacement);
225 LIR* branch_pos_overflow = NewLIR2(kX86Jcc8, 0, kX86CondAe);
226 LIR* branch_na_n = NewLIR2(kX86Jcc8, 0, kX86CondP);
228 LIR* branch_normal = NewLIR1(kX86Jmp8, 0);
246 LIR* branch_pos_overflow = NewLIR2(kX86Jcc8, 0, kX86CondAe);
247 LIR* branch_na_n = NewLIR2(kX86Jcc8, 0, kX86CondP);
249 LIR* branch_normal = NewLIR1(kX86Jmp8, 0);
285 LIR* branch_pos_overflow = NewLIR2(kX86Jcc8, 0, kX86CondAe);
286 LIR* branch_na_n = NewLIR2(kX86Jcc8, 0, kX86CondP)
630 LIR *lir = NewLIR3(kX86And32MI, rs_rX86_SP.GetReg(), displacement, 0x7fffffff); local
694 LIR *lir = NewLIR3(kX86And32MI, rs_rX86_SP.GetReg(), displacement + HIWORD_OFFSET, 0x7fffffff); local
[all...] |
| int_x86.cc | 96 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
99 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ ,
105 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg,
106 int check_value, LIR* target) {
118 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc);
123 LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) {
133 LIR* res = RawLIR(current_dalvik_offset_, r_dest.Is64Bit() ? kX86Mov64RR : kX86Mov32RR
1615 LIR *lir = NewLIR3(x86op, cu_->target64 ? rl_dest.reg.GetReg() : rl_dest.reg.GetLowReg(), local
1650 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, local
2488 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val); local
2520 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo); local
2528 LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi); local
[all...] |
| target_x86.cc | 253 void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags,
256 DCHECK(!lir->flags.use_def_invalid);
291 if (lir->opcode == kX86RepneScasw) {
333 std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) {
350 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands.
352 int operand = lir->operands[operand_number];
363 static_cast<uint32_t>(lir->operands[operand_number+1]));
383 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir-inl.h | 44 inline LIR* Mir2Lir::RawLIR(DexOffset dalvik_offset, int opcode, int op0,
45 int op1, int op2, int op3, int op4, LIR* target) {
46 LIR* insn = static_cast<LIR*>(arena_->Alloc(sizeof(LIR), kArenaAllocLIR));
69 inline LIR* Mir2Lir::NewLIR0(int opcode) {
74 LIR* insn = RawLIR(current_dalvik_offset_, opcode);
79 inline LIR* Mir2Lir::NewLIR1(int opcode, int dest) {
84 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest);
89 inline LIR* Mir2Lir::NewLIR2(int opcode, int dest, int src1)
[all...] |
| codegen_util.cc | 82 void Mir2Lir::MarkSafepointPC(LIR* inst) {
85 LIR* safepoint_pc = NewLIR0(kPseudoSafepointPC);
89 void Mir2Lir::MarkSafepointPCAfter(LIR* after) {
92 // As NewLIR0 uses Append, we need to create the LIR by hand.
93 LIR* safepoint_pc = RawLIR(current_dalvik_offset_, kPseudoSafepointPC);
103 /* Remove a LIR from the list. */
104 void Mir2Lir::UnlinkLIR(LIR* lir) {
105 if (UNLIKELY(lir == first_lir_insn_)) {
106 first_lir_insn_ = lir->next
[all...] |
| local_optimizations.cc | 60 static bool IsDalvikRegisterClobbered(LIR* lir1, LIR* lir2) {
70 void Mir2Lir::ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src) {
72 LIR* move_lir;
84 void Mir2Lir::DumpDependentInsnPair(LIR* check_lir, LIR* this_lir, const char* type) {
86 LOG(INFO) << "Check LIR:";
88 LOG(INFO) << "This LIR:";
92 inline void Mir2Lir::EliminateLoad(LIR* lir, int reg_id)
[all...] |
| mir_to_lir.h | 146 struct LIR;
165 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups.
168 struct LIR {
172 LIR* next;
173 LIR* prev;
174 LIR* target;
177 bool is_nop:1; // LIR is optimized away.
200 // Utility macros to traverse the LIR list.
201 #define NEXT_LIR(lir) (lir->next
[all...] |
| mir_to_lir.cc | 389 void Mir2Lir::CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list) {
628 LIR* taken = &label_list[bb->taken];
629 LIR* fall_through = &label_list[bb->fall_through];
657 LIR* taken = &label_list[bb->taken];
658 LIR* fall_through = &label_list[bb->fall_through];
[all...] |
| /art/compiler/dex/quick/arm64/ |
| assemble_arm64.cc | 815 LIR* lir; local
[all...] |
| codegen_arm64.h | 73 LIR* CheckSuspendUsingLoad() OVERRIDE;
75 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
77 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest,
79 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
81 LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale)
83 LIR* LoadConstantNoClobber(RegStorage r_dest, int value) OVERRIDE;
84 LIR* LoadConstantWide(RegStorage r_dest, int64_t value) OVERRIDE;
85 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
87 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, VolatileKind is_volatile)
89 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale
[all...] |
| target_arm64.cc | 166 void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags,
169 DCHECK(!lir->flags.use_def_invalid);
335 std::string Arm64Mir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) {
352 operand = lir->operands[nc-'0'];
357 int omittable = ((IS_WIDE(lir->opcode)) ? EncodeExtend(kA64Uxtw, 0) :
407 snprintf(tbuf, arraysize(tbuf), "%c%d", (IS_FWIDE(lir->opcode)) ? 'd' : 's',
411 bool is_wide = IS_WIDE(lir->opcode);
453 snprintf(tbuf, arraysize(tbuf), "%d", operand*((IS_WIDE(lir->opcode)) ? 8 : 4))
[all...] |
| utility_arm64.cc | 90 size_t Arm64Mir2Lir::GetLoadStoreSize(LIR* lir) {
91 bool opcode_is_wide = IS_WIDE(lir->opcode);
92 ArmOpcode opcode = UNWIDE(lir->opcode);
99 size_t Arm64Mir2Lir::GetInstructionOffset(LIR* lir) {
100 size_t offset = lir->operands[2];
101 uint64_t check_flags = GetTargetInstFlags(lir->opcode);
105 offset = offset * (1 << GetLoadStoreSize(lir));
110 LIR* Arm64Mir2Lir::LoadFPConstantValue(RegStorage r_dest, int32_t value)
[all...] |
| /external/qemu/android/skin/ |
| trackball.c | 344 double lir = 1/sqrt(lx*lx + ly*ly + lz*lz); local
345 double cosphi = lir*(lx*rx + ly*ry + lz*rz);
|
