| /external/linux-tools-perf/perf-3.12.0/arch/metag/lib/ |
| memcpy.S | 33 ANDS D1Ar5, D1Ar1, #7 ! test destination alignment
54 ANDS D0Ar4, D0Ar4, #7 ! test source alignment
75 ANDS D1Ar3, D1Ar3, #0x1f
176 ANDS D1Ar3, D1Ar3, #7
|
| memset.S | 13 ANDS D0Ar4,D1Ar1,#7 ! Extract bottom LSBs of dst
|
| /external/chromium_org/v8/src/arm64/ |
| constants-arm64.h | 506 ANDS = 0x60000000,
507 BICS = ANDS | NOT
521 ANDS_w_imm = LogicalImmediateFixed | ANDS,
522 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
548 ANDS_w = LogicalShiftedFixed | ANDS,
549 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
[all...] |
| instructions-arm64.h | 234 // Of the logical (immediate) instructions, only ANDS (and its aliases)
238 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) {
|
| macro-assembler-arm64-inl.h | 55 void MacroAssembler::Ands(const Register& rd,
60 LogicalMacro(rd, rn, operand, ANDS);
67 LogicalMacro(AppropriateZeroRegFor(rn), rn, operand, ANDS);
[all...] |
| assembler-arm64.cc | 1185 void Assembler::ands(const Register& rd, function in class:v8::internal::Assembler
[all...] |
| macro-assembler-arm64.cc | 96 case ANDS: // Fall through.
114 case ANDS: // Fall through.
[all...] |
| simulator-arm64.cc | [all...] |
| /external/vixl/src/a64/ |
| constants-a64.h | 396 ANDS = 0x60000000,
397 BICS = ANDS | NOT
411 ANDS_w_imm = LogicalImmediateFixed | ANDS,
412 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
438 ANDS_w = LogicalShiftedFixed | ANDS,
439 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
[all...] |
| instructions-a64.h | 261 // Of the logical (immediate) instructions, only ANDS (and its aliases)
265 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) {
|
| macro-assembler-a64.cc | 57 void MacroAssembler::Ands(const Register& rd,
61 LogicalMacro(rd, rn, operand, ANDS);
68 Ands(AppropriateZeroRegFor(rn), rn, operand);
150 case ANDS: // Fall through.
168 case ANDS: // Fall through.
[all...] |
| assembler-a64.cc | 645 void Assembler::ands(const Register& rd, function in class:vixl::Assembler
648 Logical(rd, rn, operand, ANDS);
654 ands(AppropriateZeroRegFor(rn), rn, operand);
[all...] |
| simulator-a64.cc | 691 case ANDS: update_flags = true; // Fall through.
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_DecodeCoeffsToPair_s.s | 152 ANDS TrailingOnes, Symbol, #3
|
| armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 188 ANDS Temp3, Counter, #1
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_DecodeCoeffsToPair_s.s | 152 ANDS TrailingOnes, Symbol, #3
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 58 ANDS,
|
| AArch64ISelLowering.cpp | 668 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
[all...] |
| /frameworks/av/media/libstagefright/codecs/avc/enc/src/ |
| sad_inline.h | 214 ANDS x7, mask, x7, rrx;
383 "ANDS %1, %3, %1, rrx\n\t"
|
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| sad_inline.h | 217 ANDS x7, mask, x7, rrx;
401 "ands %1, %4, %1,rrx\n\t"
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_DecodeCoeffsToPair_s.S | 91 ANDS r1,r7,#3
|
| /external/pcre/dist/sljit/ |
| sljitNativeARM_T2_32.c | 100 #define ANDS 0x4000
757 return push_inst16(compiler, ANDS | RD3(dst) | RN3(arg2));
[all...] |
| /external/srec/config/en.us/dictionary/ |
| c0.6 | [all...] |
| /external/valgrind/main/none/tests/arm/ |
| v6intThumb.stdout.exp | 169 ANDS-16 0x100
170 ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 0, cpsr 0x00000000
171 ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
172 ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
173 ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z
174 ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
175 ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
176 ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
177 ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 1, cpsr 0x10000000 V
178 ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z
[all...] |
