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      1 /*
      2  * Copyright (C) 2007-2008 ARM Limited
      3  *
      4  * Licensed under the Apache License, Version 2.0 (the "License");
      5  * you may not use this file except in compliance with the License.
      6  * You may obtain a copy of the License at
      7  *
      8  *      http://www.apache.org/licenses/LICENSE-2.0
      9  *
     10  * Unless required by applicable law or agreed to in writing, software
     11  * distributed under the License is distributed on an "AS IS" BASIS,
     12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     13  * See the License for the specific language governing permissions and
     14  * limitations under the License.
     15  *
     16  */
     17 /*
     18  *
     19  */
     20 
     21     .eabi_attribute 24, 1
     22     .eabi_attribute 25, 1
     23 
     24     .arm
     25     .fpu neon
     26     .text
     27 
     28     .extern   armVCM4P10_CAVLCCoeffTokenTables
     29     .extern   armVCM4P10_SuffixToLevel
     30     .extern   armVCM4P10_CAVLCTotalZeros2x2Tables
     31     .extern   armVCM4P10_CAVLCTotalZeroTables
     32     .extern   armVCM4P10_CAVLCRunBeforeTables
     33     .extern   armVCM4P10_ZigZag_2x2
     34     .extern   armVCM4P10_ZigZag_4x4
     35 
     36     .hidden   armVCM4P10_CAVLCCoeffTokenTables
     37     .hidden   armVCM4P10_SuffixToLevel
     38     .hidden   armVCM4P10_CAVLCTotalZeros2x2Tables
     39     .hidden   armVCM4P10_CAVLCTotalZeroTables
     40     .hidden   armVCM4P10_CAVLCRunBeforeTables
     41     .hidden   armVCM4P10_ZigZag_2x2
     42     .hidden   armVCM4P10_ZigZag_4x4
     43 
     44     .global armVCM4P10_DecodeCoeffsToPair
     45     .func   armVCM4P10_DecodeCoeffsToPair
     46 armVCM4P10_DecodeCoeffsToPair:
     47     PUSH     {r4-r12,lr}
     48     SUB      sp,sp,#0x40
     49     LDR      r10,[r0,#0]
     50     LDR      r12,[r1,#0]
     51     LDR      r6, .LarmVCM4P10_CAVLCCoeffTokenTables
     52 P0: ADD      r6, pc
     53     LDR      r4,[sp,#0x68]
     54     LDRB     r9,[r10,#2]
     55     LDRB     r8,[r10,#1]
     56     LDRB     r11,[r10],#3
     57     ADD      r12,r12,#8
     58     LDR      r6,[r6,r4,LSL #2]
     59     ORR      r9,r9,r8,LSL #8
     60     ORR      r11,r9,r11,LSL #16
     61     LSLS     r8,r11,r12
     62     MOVS     r7,#0x1e
     63     AND      r7,r7,r8,LSR #27
     64     SUBS     r12,r12,#8
     65 L0x44:
     66     BCC      L1
     67     LDRB     r8,[r10],#1
     68 L1:
     69     LDRH     r7,[r6,r7]
     70     ADDCC    r12,r12,#8
     71     ADD      r12,r12,#4
     72     ORRCS    r11,r8,r11,LSL #8
     73     LSRS     r8,r7,#1
     74     BCS      L0x74
     75     LSLS     r8,r11,r12
     76     SUBS     r12,r12,#0xa
     77     ADD      r7,r7,r8,LSR #29
     78     BIC      r7,r7,#1
     79     B        L0x44
     80 L0x74:
     81     SUB      r12,r12,r7,LSR #13
     82     BIC      r7,r8,#0xf000
     83     LSRS     r5,r7,#2
     84     STRB     r5,[r2,#0]
     85     BEQ      L0x344
     86     CMP      r7,#0x44
     87     BGE      L0x33c
     88     STR      r0,[sp,#0]
     89     STR      r1,[sp,#4]
     90     STR      r3,[sp,#8]
     91     ANDS     r1,r7,#3
     92     ADD      r2,sp,#0xc
     93     BEQ      L0xd8
     94     MOV      r0,r1
     95 L0xac:
     96     LSLS     r7,r11,r12
     97     SUBS     r12,r12,#7
     98     BCC      L2
     99     LDRB     r8,[r10],#1
    100 L2:
    101     ADDCC    r12,r12,#8
    102     LSR      r7,r7,#31
    103     ORRCS    r11,r8,r11,LSL #8
    104     SUBS     r0,r0,#1
    105     MOV      r8,#1
    106     SUB      r8,r8,r7,LSL #1
    107     STRH     r8,[r2],#2
    108     BGT      L0xac
    109 L0xd8:
    110     SUBS     r0,r5,r1
    111     BEQ      L0x1b8
    112     MOV      r4,#1
    113     CMP      r5,#0xa
    114     MOVLE    r4,#0
    115     CMP      r1,#3
    116     MOVLT    r1,#4
    117     MOVGE    r1,#2
    118     MOVGE    r4,#0
    119 L0xfc:
    120     LSLS     r7,r11,r12
    121     CLZ      r7,r7
    122     ADD      r12,r12,r7
    123     SUBS     r12,r12,#7
    124     BCC      L3
    125     LDRB     r8,[r10],#1
    126     ORR      r11,r8,r11,LSL #8
    127     SUBS     r12,r12,#8
    128     BCC      L3
    129     LDRB     r8,[r10],#1
    130 L3:
    131     ADDCC    r12,r12,#8
    132     ORRCS    r11,r8,r11,LSL #8
    133     CMP      r7,#0x10
    134     BGE      L0x33c
    135     MOVS     lr,r4
    136     TEQEQ    r7,#0xe
    137     MOVEQ    lr,#4
    138     TEQ      r7,#0xf
    139     MOVEQ    lr,#0xc
    140     TEQEQ    r4,#0
    141     ADDEQ    r7,r7,#0xf
    142     TEQ      lr,#0
    143     BEQ      L0x184
    144     LSL      r3,r11,r12
    145     ADD      r12,r12,lr
    146     SUBS     r12,r12,#8
    147     RSB      r9,lr,#0x20
    148     BCC      L4
    149     LDRB     r8,[r10],#1
    150     ORR      r11,r8,r11,LSL #8
    151     SUBS     r12,r12,#8
    152     BCC      L4
    153     LDRB     r8,[r10],#1
    154 L4:
    155     ADDCC    r12,r12,#8
    156     LSR      r3,r3,r9
    157     ORRCS    r11,r8,r11,LSL #8
    158     LSL      r7,r7,r4
    159     ADD      r7,r3,r7
    160 L0x184:
    161     ADD      r7,r7,r1
    162     MOV      r1,#2
    163     LSRS     r8,r7,#1
    164     RSBCS    r8,r8,#0
    165     STRH     r8,[r2],#2
    166     LDR      r9, .LarmVCM4P10_SuffixToLevel
    167 P1: ADD      r9, pc
    168     LDRSB    r8,[r9,r4]
    169     TEQ      r4,#0
    170     MOVEQ    r4,#1
    171     CMP      r7,r8
    172     ADDCS    r4,r4,#1
    173     SUBS     r0,r0,#1
    174     BGT      L0xfc
    175 L0x1b8:
    176     LDR      r8,[sp,#0x6c]
    177     SUB      r0,r5,#1
    178     SUBS     r1,r8,r5
    179     ADD      r4,sp,#0x2c
    180     MOV      lr,r5
    181     SUB      lr,lr,#1
    182     BEQ      L0x2b0
    183     TEQ      r8,#4
    184     LDREQ    r6, .LarmVCM4P10_CAVLCTotalZeros2x2Tables
    185     LDRNE    r6, .LarmVCM4P10_CAVLCTotalZeroTables
    186 P2: ADD      r6, pc
    187     LDR      r6,[r6,r5,LSL #2]
    188     LSLS     r8,r11,r12
    189     MOVS     r7,#0x1e
    190     AND      r7,r7,r8,LSR #27
    191     SUBS     r12,r12,#8
    192 L0x1f4:
    193     BCC      L5
    194     LDRB     r8,[r10],#1
    195 L5:
    196     LDRH     r7,[r6,r7]
    197     ADDCC    r12,r12,#8
    198     ADD      r12,r12,#4
    199     ORRCS    r11,r8,r11,LSL #8
    200     LSRS     r8,r7,#1
    201     BCS      L0x224
    202     LSLS     r8,r11,r12
    203     SUBS     r12,r12,#0xa
    204     ADD      r7,r7,r8,LSR #29
    205     BIC      r7,r7,#1
    206     B        L0x1f4
    207 L0x224:
    208     SUB      r12,r12,r7,LSR #13
    209     BIC      r7,r8,#0xf000
    210     CMP      r7,#0x10
    211     BGE      L0x33c
    212     LDR      r3, .LarmVCM4P10_CAVLCRunBeforeTables
    213 P3: ADD      r3, pc
    214     ADD      r4,sp,#0x2c
    215     MOVS     r1,r7
    216     ADD      lr,lr,r1
    217     BEQ      L0x2b0
    218 L0x248:
    219     SUBS     r0,r0,#1
    220     LDR      r6,[r3,r1,LSL #2]
    221     BLT      L0x2bc
    222     LSLS     r8,r11,r12
    223     MOVS     r7,#0xe
    224     AND      r7,r7,r8,LSR #28
    225     SUBS     r12,r12,#8
    226 L0x264:
    227     BCC      L6
    228     LDRB     r8,[r10],#1
    229 L6:
    230     LDRH     r7,[r6,r7]
    231     ADDCC    r12,r12,#8
    232     ADD      r12,r12,#3
    233     ORRCS    r11,r8,r11,LSL #8
    234     LSRS     r8,r7,#1
    235     BCS      L0x294
    236     LSLS     r8,r11,r12
    237     SUBS     r12,r12,#9
    238     ADD      r7,r7,r8,LSR #29
    239     BIC      r7,r7,#1
    240     B        L0x264
    241 L0x294:
    242     SUB      r12,r12,r7,LSR #13
    243     BIC      r7,r8,#0xf000
    244     CMP      r7,#0xf
    245     BGE      L0x33c
    246     SUBS     r1,r1,r7
    247     STRB     r7,[r4],#1
    248     BGT      L0x248
    249 L0x2b0:
    250     SUBS     r0,r0,#1
    251     BLT      L7
    252     STRB     r1,[r4],#1
    253 L7:
    254     BGT      L0x2b0
    255 L0x2bc:
    256     STRB     r1,[r4],#1
    257     LDR      r8,[sp,#0x6c]
    258     TEQ      r8,#0xf
    259     ADDEQ    lr,lr,#1
    260     SUB      r4,r4,r5
    261     SUB      r2,r2,r5
    262     SUB      r2,r2,r5
    263     LDR      r3,[sp,#8]
    264     LDR      r0,[r3,#0]
    265     TEQ      r8,#4
    266     LDREQ    r6, .LarmVCM4P10_ZigZag_2x2
    267     LDRNE    r6, .LarmVCM4P10_ZigZag_4x4
    268 P4: ADD      r6, pc
    269 L0x2ec:
    270     LDRB     r9,[r4],#1
    271     LDRB     r8,[r6,lr]
    272     SUB      lr,lr,#1
    273     SUB      lr,lr,r9
    274     LDRSH    r9,[r2],#2
    275     SUBS     r5,r5,#1
    276     ORREQ    r8,r8,#0x20
    277     ADD      r1,r9,#0x80
    278     CMP      r1,#0x100
    279     ORRCS    r8,r8,#0x10
    280     TEQ      r5,#0
    281     STRB     r8,[r0],#1
    282     STRB     r9,[r0],#1
    283     LSR      r9,r9,#8
    284     BCC      L8
    285     STRB     r9,[r0],#1
    286 L8:
    287     BNE      L0x2ec
    288     STR      r0,[r3,#0]
    289     LDR      r0,[sp,#0]
    290     LDR      r1,[sp,#4]
    291     B        L0x344
    292 L0x33c:
    293     MVN      r0,#1
    294     B        L0x35c
    295 L0x344:
    296     ADD      r10,r10,r12,LSR #3
    297     AND      r12,r12,#7
    298     SUB      r10,r10,#4
    299     STR      r12,[r1,#0]
    300     STR      r10,[r0,#0]
    301     MOV      r0,#0
    302 L0x35c:
    303     ADD      sp,sp,#0x40
    304     POP      {r4-r12,pc}
    305     .endfunc
    306 
    307 .LarmVCM4P10_CAVLCCoeffTokenTables:
    308     .word   armVCM4P10_CAVLCCoeffTokenTables-(P0+8)
    309 .LarmVCM4P10_SuffixToLevel:
    310     .word   armVCM4P10_SuffixToLevel-(P1+8)
    311 .LarmVCM4P10_CAVLCTotalZeros2x2Tables:
    312     .word   (armVCM4P10_CAVLCTotalZeros2x2Tables - 4)-(P2+8)
    313 .LarmVCM4P10_CAVLCTotalZeroTables:
    314     .word   (armVCM4P10_CAVLCTotalZeroTables - 4)-(P2+8)
    315 .LarmVCM4P10_CAVLCRunBeforeTables:
    316     .word   (armVCM4P10_CAVLCRunBeforeTables - 4)-(P3+8)
    317 .LarmVCM4P10_ZigZag_2x2:
    318     .word   armVCM4P10_ZigZag_2x2-(P4+8)
    319 .LarmVCM4P10_ZigZag_4x4:
    320     .word   armVCM4P10_ZigZag_4x4-(P4+8)
    321 
    322     .end
    323