/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeTypesGeneric.cpp | 56 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 57 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 66 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 67 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 73 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 74 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 79 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 80 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 83 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); 90 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo) [all...] |
LegalizeVectorOps.cpp | 368 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); 375 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 412 // PromoteVector which uses bitcast to promote thus assumning that the 704 // Bitcast the operands to be the same type as the mask. 707 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); 708 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); 717 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); 761 ISD::BITCAST, DL, VT, 788 // and a bitcast to the wider element type. 815 return DAG.getNode(ISD::BITCAST, DL, VT [all...] |
LegalizeVectorTypes.cpp | 52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 158 return DAG.getNode(ISD::BITCAST, SDLoc(N), 404 case ISD::BITCAST: 450 return DAG.getNode(ISD::BITCAST, SDLoc(N), 564 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 711 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 712 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 720 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 721 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 735 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo) [all...] |
LegalizeDAG.cpp | 325 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); 446 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); 753 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); [all...] |
SelectionDAGBuilder.cpp | 137 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 138 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 170 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 171 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 213 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 303 // Vector/Vector bitcast. 305 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 316 // Trivial bitcast if the types are the same size and the destination 320 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 384 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val) [all...] |
DAGCombiner.cpp | [all...] |
LegalizeFloatTypes.cpp | 63 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; 626 case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break; 653 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), [all...] |
FastISel.cpp | 137 !(I->getOpcode() == Instruction::BitCast || 874 // If the bitcast doesn't change the type, just use the operand value. [all...] |
SelectionDAGDumper.cpp | 237 case ISD::BITCAST: return "bitcast";
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LegalizeTypes.cpp | [all...] |
LegalizeIntegerTypes.cpp | 55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; 249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); 264 // For example, i32 = BITCAST v2i16 on alpha. Convert the split 278 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); 283 // make us bitcast between two vectors which are legalized in different ways. 285 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); [all...] |
SelectionDAG.cpp | 98 if (N->getOpcode() == ISD::BITCAST) 146 if (N->getOpcode() == ISD::BITCAST) [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | 414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); [all...] |
/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 449 /// BITCAST - This operator converts between integer, vector and FP 456 BITCAST, [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | 356 setTargetDAGCombine(ISD::BITCAST); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEISelDAGToDAG.cpp | 441 // This function looks through ISD::BITCAST nodes. 442 // TODO: This might not be appropriate for big-endian MSA since BITCAST is 455 if (N->getOpcode() == ISD::BITCAST) 523 // This function looks through ISD::BITCAST nodes. 524 // TODO: This might not be appropriate for big-endian MSA since BITCAST is 530 if (N->getOpcode() == ISD::BITCAST) 554 // This function looks through ISD::BITCAST nodes. 555 // TODO: This might not be appropriate for big-endian MSA since BITCAST is 561 if (N->getOpcode() == ISD::BITCAST) 587 // This function looks through ISD::BITCAST nodes [all...] |
MipsISelLowering.cpp | [all...] |
MipsSEISelLowering.cpp | 75 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 250 setOperationAction(ISD::BITCAST, Ty, Legal); 301 setOperationAction(ISD::BITCAST, Ty, Legal); 620 if (N->getOpcode() == ISD::BITCAST) [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | 400 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 408 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 455 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 770 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | 259 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 260 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 261 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 262 setOperationAction(ISD::BITCAST, MVT::f64, Expand); [all...] |
/external/llvm/lib/CodeGen/ |
TargetLoweringBase.cpp | [all...] |
/external/llvm/lib/Target/R600/ |
SIISelLowering.cpp | 188 case ISD::BITCAST: [all...] |
R600ISelLowering.cpp | [all...] |
AMDGPUISelLowering.cpp | [all...] |