| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 92 BuildMI (*MBB, MII, MI->getDebugLoc(),
94 BuildMI (*MBB, MII, MI->getDebugLoc(),
105 BuildMI (*MBB, MII, MI->getDebugLoc(),
107 BuildMI (*MBB, MII, MI->getDebugLoc(),
118 BuildMI (*MBB, MII, MI->getDebugLoc(),
120 BuildMI (*MBB, MII, MI->getDebugLoc(),
131 BuildMI (*MBB, MII, MI->getDebugLoc(),
133 BuildMI (*MBB, MII, MI->getDebugLoc(),
150 BuildMI (*MBB, MII, MI->getDebugLoc(),
153 BuildMI (*MBB, MII, MI->getDebugLoc()
[all...] |
| HexagonExpandPredSpillCode.cpp | 98 BuildMI(*MBB, MII, MI->getDebugLoc(),
101 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
106 BuildMI(*MBB, MII, MI->getDebugLoc(),
111 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
113 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
115 BuildMI(*MBB, MII, MI->getDebugLoc(),
122 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
124 BuildMI(*MBB, MII, MI->getDebugLoc(),
142 BuildMI(*MBB, MII, MI->getDebugLoc()
[all...] |
| HexagonSplitTFRCondSets.cpp | 115 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1),
119 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2),
134 BuildMI(*MBB, MII, MI->getDebugLoc(),
139 BuildMI(*MBB, MII, MI->getDebugLoc(),
144 BuildMI(*MBB, MII, MI->getDebugLoc(),
160 BuildMI(*MBB, MII, MI->getDebugLoc(),
165 BuildMI(*MBB, MII, MI->getDebugLoc(),
174 BuildMI(*MBB, MII, MI->getDebugLoc(),
190 BuildMI(*MBB, MII, MI->getDebugLoc(),
193 BuildMI(*MBB, MII, MI->getDebugLoc()
[all...] |
| HexagonRegisterInfo.cpp | 176 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
178 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
182 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
205 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
207 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
211 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
237 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
239 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
246 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
256 BuildMI(*MI.getParent(), II, MI.getDebugLoc()
[all...] |
| HexagonFixupHwLoops.cpp | 171 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
175 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFRI), Scratch)
177 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
181 BuildMI(*MBB, MII, DL, TII->get(Hexagon::CONST32_Label), Scratch)
183 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::SA0)
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXFrameLowering.cpp | 51 BuildMI(MBB, MBBI, dl,
54 BuildMI(MBB, MI, dl,
60 BuildMI(MBB, MBBI, dl,
63 BuildMI(MBB, MI, dl,
|
| NVPTXInstrInfo.cpp | 46 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg)
49 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg)
52 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg)
55 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg)
58 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg)
61 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg)
262 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
264 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
270 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
271 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 10 // This file exposes a function named BuildMI, which is useful for dramatically
13 // M = BuildMI(X86::ADDrr8, 2).addReg(argVal1).addReg(argVal2);
225 /// BuildMI - Builder interface. Specify how to create the initial instruction
228 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
234 /// BuildMI - This version of the builder sets up the first operand as a
237 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
245 /// BuildMI - This version of the builder inserts the newly-built
249 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
260 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
271 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB
[all...] |
| /external/llvm/lib/Target/R600/ |
| SILowerControlFlow.cpp | 140 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
159 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
164 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
176 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
185 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
188 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
203 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
207 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
223 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
238 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsLongBranch.cpp | 224 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
293 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
314 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
317 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB))
318 .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
325 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
327 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
332 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
333 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
156 BuildMI(MBB, MBBI, DL,
160 BuildMI(MBB, MBBI, DL,
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
199 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
220 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
247 New = BuildMI(MF, Old->getDebugLoc()
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
312 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
316 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
321 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
325 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
620 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
627 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
634 BuildMI(MBB, MBBI, dl, StoreInst
[all...] |
| PPCBranchSelector.cpp | 171 BuildMI(MBB, I, dl, TII->get(PPC::BCC))
175 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2);
178 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2);
180 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
182 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
184 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
186 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
192 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
|
| PPCRegisterInfo.cpp | 308 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
312 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
316 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
333 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
338 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
344 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
348 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
358 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
363 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
369 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 177 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
189 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
192 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
333 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
509 BuildMI(MBB, MBBI, DL,
553 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
563 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
571 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
576 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
582 BuildMI(MBB, MBBI, DL
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 206 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
208 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
241 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
249 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
251 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
255 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
296 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
299 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
303 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
314 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg
[all...] |
| SparcFrameLowering.cpp | 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
118 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
123 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
131 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)
[all...] |
| SparcRegisterInfo.cpp | 120 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
125 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
138 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
140 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
143 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
182 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
194 BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 199 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
211 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
305 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
309 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
318 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
326 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
330 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
338 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr),
376 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
401 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)
[all...] |
| Thumb1InstrInfo.cpp | 44 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
72 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
100 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
146 BuildMI(MBB, II, dl, TII.get(NewOpcode))
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
176 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0)
[all...] |
| XCoreInstrInfo.cpp | 294 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
298 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
307 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
309 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
349 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
356 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
361 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
385 BuildMI(MBB, I, DL, get(XCore::STWFI))
408 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
449 return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg).addImm(N)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 65 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
76 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
88 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
101 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::COPY))
129 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV_IMM_I32),
134 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::LSHR_eg), NewAddr)
138 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
160 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), t0)
164 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), t1)
168 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 65 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
76 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
88 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
101 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::COPY))
129 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV_IMM_I32),
134 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::LSHR_eg), NewAddr)
138 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
160 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), t0)
164 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), t1)
168 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
645 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
649 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
656 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
680 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
751 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
755 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
775 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
780 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
784 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II
[all...] |
