1 //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Thumb1InstrInfo.h" 15 #include "llvm/CodeGen/MachineFrameInfo.h" 16 #include "llvm/CodeGen/MachineInstrBuilder.h" 17 #include "llvm/CodeGen/MachineMemOperand.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/MC/MCInst.h" 20 21 using namespace llvm; 22 23 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) 24 : ARMBaseInstrInfo(STI), RI(STI) { 25 } 26 27 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 28 void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 29 NopInst.setOpcode(ARM::tMOVr); 30 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); 31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); 32 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 33 NopInst.addOperand(MCOperand::CreateReg(0)); 34 } 35 36 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { 37 return 0; 38 } 39 40 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 41 MachineBasicBlock::iterator I, DebugLoc DL, 42 unsigned DestReg, unsigned SrcReg, 43 bool KillSrc) const { 44 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 45 .addReg(SrcReg, getKillRegState(KillSrc))); 46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && 47 "Thumb1 can only copy GPR registers"); 48 } 49 50 void Thumb1InstrInfo:: 51 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 52 unsigned SrcReg, bool isKill, int FI, 53 const TargetRegisterClass *RC, 54 const TargetRegisterInfo *TRI) const { 55 assert((RC == &ARM::tGPRRegClass || 56 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 57 isARMLowRegister(SrcReg))) && "Unknown regclass!"); 58 59 if (RC == &ARM::tGPRRegClass || 60 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 61 isARMLowRegister(SrcReg))) { 62 DebugLoc DL; 63 if (I != MBB.end()) DL = I->getDebugLoc(); 64 65 MachineFunction &MF = *MBB.getParent(); 66 MachineFrameInfo &MFI = *MF.getFrameInfo(); 67 MachineMemOperand *MMO = 68 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 69 MachineMemOperand::MOStore, 70 MFI.getObjectSize(FI), 71 MFI.getObjectAlignment(FI)); 72 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi)) 73 .addReg(SrcReg, getKillRegState(isKill)) 74 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 75 } 76 } 77 78 void Thumb1InstrInfo:: 79 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 80 unsigned DestReg, int FI, 81 const TargetRegisterClass *RC, 82 const TargetRegisterInfo *TRI) const { 83 assert((RC == &ARM::tGPRRegClass || 84 (TargetRegisterInfo::isPhysicalRegister(DestReg) && 85 isARMLowRegister(DestReg))) && "Unknown regclass!"); 86 87 if (RC == &ARM::tGPRRegClass || 88 (TargetRegisterInfo::isPhysicalRegister(DestReg) && 89 isARMLowRegister(DestReg))) { 90 DebugLoc DL; 91 if (I != MBB.end()) DL = I->getDebugLoc(); 92 93 MachineFunction &MF = *MBB.getParent(); 94 MachineFrameInfo &MFI = *MF.getFrameInfo(); 95 MachineMemOperand *MMO = 96 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 97 MachineMemOperand::MOLoad, 98 MFI.getObjectSize(FI), 99 MFI.getObjectAlignment(FI)); 100 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) 101 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 102 } 103 } 104
