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    Searched refs:CONCAT_VECTORS (Results 1 - 16 of 16) sorted by null

  /external/llvm/include/llvm/CodeGen/
ISDOpcodes.h 258 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
262 CONCAT_VECTORS,
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorTypes.cpp 413 case ISD::CONCAT_VECTORS:
566 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
754 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
767 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
770 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
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SelectionDAGDumper.cpp 199 case ISD::CONCAT_VECTORS: return "concat_vectors";
DAGCombiner.cpp     [all...]
LegalizeIntegerTypes.cpp 92 case ISD::CONCAT_VECTORS:
643 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
    [all...]
SelectionDAGBuilder.cpp 278 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
280 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
504 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
    [all...]
SelectionDAG.cpp     [all...]
LegalizeDAG.cpp     [all...]
  /external/llvm/lib/Target/R600/
AMDGPUISelLowering.cpp 206 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
207 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
530 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
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SIISelLowering.cpp 191 case ISD::CONCAT_VECTORS:
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  /external/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 357 setTargetDAGCombine(ISD::CONCAT_VECTORS);
520 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
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  /external/llvm/lib/Target/X86/
X86ISelLowering.cpp     [all...]
  /external/llvm/lib/CodeGen/
TargetLoweringBase.cpp 740 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
    [all...]
  /external/llvm/lib/Target/ARM/
ARMISelLowering.cpp 117 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
    [all...]
ARMISelDAGToDAG.cpp     [all...]
  /external/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp     [all...]

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