| /art/compiler/dex/quick/arm/ |
| codegen_arm.h | 123 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
139 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
140 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
141 LIR* OpCondBranch(ConditionCode cc, LIR* target);
142 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
144 LIR* OpIT(ConditionCode cond, const char* guide);
156 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
172 ArmConditionCode ArmConditionEncoding(ConditionCode code);
195 ConditionCode ccode);
|
| int_arm.cc | 28 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
43 LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) {
156 int64_t val, ConditionCode ccode) {
206 void ArmMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
238 ConditionCode ccode = mir->meta.ccode;
309 ConditionCode ccode = mir->meta.ccode;
367 LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) {
[all...] |
| fp_arm.cc | 233 ConditionCode ccode = mir->meta.ccode;
|
| utility_arm.cc | 213 LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
385 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
[all...] |
| target_arm.cc | 242 ArmConditionCode ArmMir2Lir::ArmConditionEncoding(ConditionCode ccode) {
|
| /art/compiler/dex/quick/mips/ |
| codegen_mips.h | 122 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
137 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
138 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
139 LIR* OpCondBranch(ConditionCode cc, LIR* target);
140 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
142 LIR* OpIT(ConditionCode cond, const char* guide);
153 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
|
| int_mips.cc | 65 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
112 LOG(FATAL) << "No support for ConditionCode: " << cond;
131 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) {
218 void MipsMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
369 LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) {
385 LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide) {
|
| utility_mips.cc | 339 LIR* MipsMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
688 LIR* MipsMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
|
| /art/compiler/dex/quick/arm64/ |
| codegen_arm64.h | 93 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
188 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
205 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
206 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE;
207 LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE;
208 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
210 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE;
221 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
384 ArmConditionCode ArmConditionEncoding(ConditionCode code);
387 void GenSelect(int32_t left, int32_t right, ConditionCode code, RegStorage rs_dest
[all...] |
| int_arm64.cc | 29 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
34 LIR* Arm64Mir2Lir::OpIT(ConditionCode ccode, const char* guide) {
91 void Arm64Mir2Lir::GenSelect(int32_t true_val, int32_t false_val, ConditionCode ccode,
175 void Arm64Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
220 ConditionCode ccode = mir->meta.ccode;
259 LIR* Arm64Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value,
287 LIR* Arm64Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg,
[all...] |
| fp_arm64.cc | 219 ConditionCode ccode = mir->meta.ccode;
|
| utility_arm64.cc | 543 LIR* Arm64Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
690 LIR* Arm64Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
[all...] |
| /art/compiler/dex/portable/ |
| mir_to_gbc.h | 115 ::llvm::Value* ConvertCompare(ConditionCode cc,
117 void ConvertCompareAndBranch(BasicBlock* bb, MIR* mir, ConditionCode cc,
119 void ConvertCompareZeroAndBranch(BasicBlock* bb, MIR* mir, ConditionCode cc,
|
| mir_to_gbc.cc | 313 ::llvm::Value* MirConverter::ConvertCompare(ConditionCode cc,
330 ConditionCode cc, RegLocation rl_src1, RegLocation rl_src2) {
345 MIR* mir, ConditionCode cc, RegLocation rl_src1) {
[all...] |
| /art/compiler/dex/quick/x86/ |
| codegen_x86.h | 240 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
264 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
265 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE;
266 LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE;
267 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
269 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE;
280 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
480 int64_t val, ConditionCode ccode);
[all...] |
| int_x86.cc | 72 X86ConditionCode X86ConditionEncoding(ConditionCode cond) {
96 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
105 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg,
209 void X86Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
277 ConditionCode ccode = mir->meta.ccode;
335 ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode;
388 ConditionCode ccode = mir->meta.ccode;
448 int64_t val, ConditionCode ccode) {
837 ConditionCode condition_code = is_min ? kCondGt : kCondLt;
[all...] |
| utility_x86.cc | 113 LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
356 LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
[all...] |
| fp_x86.cc | 513 ConditionCode ccode = mir->meta.ccode;
|
| x86_lir.h | 453 // RRC - Register Register ConditionCode - cond_opcode reg1, reg2
457 // RMC - Register Memory ConditionCode - cond_opcode reg1, [base + disp]
[all...] |
| /art/compiler/dex/ |
| compiler_enums.h | 335 enum ConditionCode {
356 std::ostream& operator<<(std::ostream& os, const ConditionCode& kind);
|
| mir_optimization.cc | 208 static constexpr ConditionCode kIfCcZConditionCodes[] = {
219 static constexpr ConditionCode ConditionCodeForIfCcZ(Instruction::Code opcode) {
[all...] |
| mir_graph.h | 360 ConditionCode ccode;
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 698 ConditionCode FlipComparisonOrder(ConditionCode before);
699 ConditionCode NegateComparison(ConditionCode before);
[all...] |
| codegen_util.cc | [all...] |
| gen_common.cc | 56 void Mir2Lir::GenDivZeroCheck(ConditionCode c_code) {
223 ConditionCode cond;
244 cond = static_cast<ConditionCode>(0);
286 ConditionCode cond;
309 cond = static_cast<ConditionCode>(0);
[all...] |
