| /external/libhevc/decoder/arm/ |
| ihevcd_fmt_conv_420sp_to_rgba8888.s | 228 VQMOVUN.S16 D16,Q8
232 VZIP.8 D16,D17
252 VST1.32 D16,[R2]!
279 VQMOVUN.S16 D16,Q8
283 VZIP.8 D16,D17
303 VST1.32 D16,[R8]!
359 VQMOVUN.S16 D16,Q8
363 VZIP.8 D16,D17
383 VST1.32 D16,[R2]!
401 VQMOVUN.S16 D16,Q
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| scale_sig_neon.s | 60 VADDHN.S32 D16, Q10, Q15
80 VADDHN.S32 D16, Q8, Q15
95 VADDHN.S32 D16, Q12, Q15
109 VADDHN.S32 D16, Q10, Q15
123 VADDHN.S32 D16, Q10, Q15
|
| Filt_6k_7k_neon.s | 120 VMLAL.S16 Q12,D16,D7[0]
142 VMLAL.S16 Q12,D16,D7[1]
164 VMLAL.S16 Q12,D16,D7[2]
186 VMLAL.S16 Q12,D16,D7[3]
201 VMOV.S16 D15,D16
|
| Dot_p_neon.s | 47 VMULL.S16 Q15, D16, D0
|
| /external/llvm/test/MC/MachO/ |
| x86_32-symbols.s | 53 D16:
829 // CHECK: ('_string', 'D16')
|
| x86_64-symbols.s | 53 D16:
762 // CHECK: ('_string', 'D16')
|
| /art/compiler/utils/arm/ |
| managed_register_arm_test.cc | 187 reg = ArmManagedRegister::FromDRegister(D16);
194 EXPECT_EQ(D16, reg.AsDRegister());
378 ArmManagedRegister reg_D16 = ArmManagedRegister::FromDRegister(D16);
387 EXPECT_TRUE(reg_D16.Equals(ArmManagedRegister::FromDRegister(D16)));
399 EXPECT_TRUE(!reg_D30.Equals(ArmManagedRegister::FromDRegister(D16)));
412 EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::FromDRegister(D16)));
475 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
497 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
519 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
541 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
[all...] |
| constants_arm.h | 42 // We support both VFPv3-D16 and VFPv3-D32 profiles, but currently only one at
79 D16 = 16,
|
| /external/libhevc/common/arm/ |
| ihevc_sao_band_offset_chroma.s | 186 VCLE.U8 D16,D1,D30 @vcle_u8(band_table.val[0], vdup_n_u8(16))
187 VORR.U8 D1,D1,D16 @band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
196 VCLE.U8 D16,D1,D30 @vcle_u8(band_table.val[0], vdup_n_u8(16))
197 VAND.U8 D1,D1,D16 @band_table.val[0] = vand_u8(band_table.val[0], au1_cmp)
213 VADD.I8 D16,D12,D30 @band_table_v.val[3] = vadd_u8(band_table_v.val[3], band_pos_v)
225 VADD.I8 D12,D16,D26 @band_table_v.val[3] = vadd_u8(band_table_v.val[3], vdup_n_u8(pi1_sao_offset_v[4]))
299 VSUB.I8 D16,D14,D30 @vsub_u8(au1_cur_row_deint.val[1], band_pos_v)
307 VTBX.8 D14,{D9-D12},D16 @vtbx4_u8(au1_cur_row_deint.val[1], band_table_v, vsub_u8(au1_cur_row_deint.val[1], band_pos_v))
353 VSUB.I8 D16,D14,D30 @vsub_u8(au1_cur_row_deint.val[1], band_pos_v)
361 VTBX.8 D14,{D9-D12},D16 @vtbx4_u8(au1_cur_row_deint.val[1], band_table_v, vsub_u8(au1_cur_row_deint.val[1], ban (…)
[all...] |
| ihevc_sao_edge_offset_class0_chroma.s | 214 VTBL.8 D16,{D11},D14 @offset = vtbl1_s8(offset_tbl_u, vget_low_s8(edge_idx))
221 VZIP.S8 D16,D17
225 VADDW.S8 Q9,Q9,D16 @pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[0], offset)
379 VTBL.8 D16,{D11},D14 @offset = vtbl1_s8(offset_tbl_u, vget_low_s8(edge_idx))
386 VZIP.S8 D16,D17
388 VADDW.S8 Q9,Q9,D16 @pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[0], offset)
|
| ihevc_sao_band_offset_luma.s | 203 VSUB.I8 D16,D15,D31 @vsub_u8(au1_cur_row, band_pos)
205 VTBX.8 D15,{D1-D4},D16 @vtbx4_u8(au1_cur_row, band_table, vsub_u8(au1_cur_row, band_pos))
|
| /art/runtime/arch/arm64/ |
| registers_arm64.h | 131 D16 = 16,
|
| context_arm64.cc | 117 // d0-d7, d16-d31 are caller-saved; d8-d15 are callee-saved.
128 fprs_[D16] = nullptr;
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S | 96 #define dUr0 D16.F32
131 #define dVr1 D16.F32
148 #define dYr0 D16.F32
|
| armSP_FFT_CToC_SC16_Radix8_fs_unsafe_s.S | 107 #define dUr0 D16.S16
143 #define dVr1 D16.S16
164 #define dYr0 D16.S16
|
| armSP_FFT_CToC_SC32_Radix8_fs_unsafe_s.S | 106 #define dUr0 D16.S32
142 #define dVr1 D16.S32
161 #define dYr0 D16.S32
|
| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 107 #define qT2 D16.F32
|
| armSP_FFT_CToC_FC32_Radix4_fs_unsafe_s.S | 95 #define dZr0 D16.F32
|
| armSP_FFT_CToC_SC16_Radix4_fs_unsafe_s.S | 95 #define dZr0 D16.S16
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_DeblockingChroma_unsafe_s.s | 57 dFilt DN D16.U8
105 ;// - Filter masks - filt: D16, aqflg: D12, apflg: D17
181 ;// - Filter masks - filt: D16, aqflg: D12, apflg: D17
|
| omxVCM4P10_FilterDeblockingChroma_HorEdge_I_s.s | 69 dFilt DN D16.U8
|
| /frameworks/av/media/libstagefright/codecs/aacenc/src/asm/ARMV7/ |
| Radix4FFT_v7.s | 111 VST2.I32 {D16, D17, D18, D19}, [r8]
121 VST2.I32 {D16, D17, D18, D19}, [r8]
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 81 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
|
| /bionic/libm/upstream-freebsd/lib/msun/ld128/ |
| s_expl.c | 365 D16 = 4.7628892832607741e-14, /* 0x1.ad00Dfe41feccp-45 */
422 dx * (D14 + dx * (D15 + dx * (D16 +
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 139 // Reserve D16-D31 if the subtarget doesn't support them.
141 assert(ARM::D31 == ARM::D16 + 15);
143 Reserved.set(ARM::D16 + i);
|
