| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 68 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
69 DBG_VALUE = 11,
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 185 if (MInst->getOpcode() == TargetOpcode::DBG_VALUE ||
|
| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 216 case TargetOpcode::DBG_VALUE:
|
| LiveDebugVariables.cpp | 12 // Remove all DBG_VALUE instructions referencing virtual registers and replace
17 // are moved between registers and stack slots. Finally emit new DBG_VALUE
102 /// A DBG_VALUE instruction notes that (a sub-register of) a virtual register
131 /// insertDebugValue - Insert a DBG_VALUE into MBB at Idx for LocNo.
216 // A later DBG_VALUE at the same SlotIndex overrides the old location.
265 /// emitDebugValues - Recreate DBG_VALUE instruction from data structures.
269 /// findDebugLoc - Return DebugLoc used for this DBG_VALUE instruction. A
270 /// variable may have more than one corresponding DBG_VALUE instructions.
315 /// handleDebugValue - Add DBG_VALUE instruction to our maps.
316 /// @param MI DBG_VALUE instructio
[all...] |
| RegAllocFast.cpp | 294 // If this register is used by DBG_VALUE then insert new DBG_VALUE to
313 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE))
318 // Now this register is spilled there is should not be any DBG_VALUE
858 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
862 // Modify DBG_VALUE now that the value is in a spill slot.
870 TII->get(TargetOpcode::DBG_VALUE)
[all...] |
| InlineSpiller.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 248 /// this DBG_VALUE instruction.
250 assert(isDebugValue() && "not a DBG_VALUE");
693 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
694 /// A DBG_VALUE is indirect iff the first operand is a register and
764 case TargetOpcode::DBG_VALUE:
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 306 case TargetOpcode::DBG_VALUE:
|
| /external/llvm/lib/Target/XCore/ |
| XCoreAsmPrinter.cpp | 274 case XCore::DBG_VALUE:
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 169 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
453 case AArch64::DBG_VALUE: {
|
| AArch64InstrInfo.cpp | 50 case TargetOpcode::DBG_VALUE:
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 752 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0,
756 TII.get(TargetOpcode::DBG_VALUE))
767 case Intrinsic::dbg_value: {
768 // This form of DBG_VALUE is target-independent.
770 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
[all...] |
| InstrEmitter.cpp | 640 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
652 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
656 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
[all...] |
| SelectionDAGISel.cpp | 466 // Insert DBG_VALUE instructions for function arguments to the entry block.
498 TII.get(TargetOpcode::DBG_VALUE),
503 // that COPY instructions also need DBG_VALUE, if it is the only
520 TII.get(TargetOpcode::DBG_VALUE),
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcAsmPrinter.cpp | 263 case TargetOpcode::DBG_VALUE:
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 786 assert(OpC != PPC::DBG_VALUE &&
[all...] |
| PPCAsmPrinter.cpp | 313 case TargetOpcode::DBG_VALUE:
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 787 case TargetOpcode::DBG_VALUE:
[all...] |
| X86CodeEmitter.cpp | [all...] |
| X86FrameLowering.cpp | [all...] |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | [all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | 627 /// of DBG_VALUE, returning true if it was able to do so. A false return
782 case TargetOpcode::DBG_VALUE:
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXAsmPrinter.cpp | [all...] |
