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    Searched refs:MipsMir2Lir (Results 1 - 7 of 7) sorted by null

  /art/compiler/dex/quick/mips/
target_mips.cc 58 RegLocation MipsMir2Lir::LocCReturn() {
62 RegLocation MipsMir2Lir::LocCReturnRef() {
66 RegLocation MipsMir2Lir::LocCReturnWide() {
70 RegLocation MipsMir2Lir::LocCReturnFloat() {
74 RegLocation MipsMir2Lir::LocCReturnDouble() {
79 RegStorage MipsMir2Lir::Solo64ToPair64(RegStorage reg) {
86 RegStorage MipsMir2Lir::TargetReg(SpecialTargetRegister reg) {
113 RegStorage MipsMir2Lir::GetArgMappingToPhysicalReg(int arg_num) {
130 ResourceMask MipsMir2Lir::GetRegMaskCommon(const RegStorage& reg) const {
141 ResourceMask MipsMir2Lir::GetPCUseDefEncoding() const
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utility_mips.cc 25 LIR* MipsMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
54 bool MipsMir2Lir::InexpensiveConstantInt(int32_t value) {
58 bool MipsMir2Lir::InexpensiveConstantFloat(int32_t value) {
62 bool MipsMir2Lir::InexpensiveConstantLong(int64_t value) {
66 bool MipsMir2Lir::InexpensiveConstantDouble(int64_t value) {
79 LIR* MipsMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
110 LIR* MipsMir2Lir::OpUnconditionalBranch(LIR* target) {
116 LIR* MipsMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
131 LIR* MipsMir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) {
161 LIR* MipsMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2)
    [all...]
int_mips.cc 44 void MipsMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,
65 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
131 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) {
163 LIR* MipsMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) {
181 void MipsMir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) {
188 void MipsMir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) {
218 void MipsMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
230 void MipsMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
234 void MipsMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) {
238 RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2
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fp_mips.cc 24 void MipsMir2Lir::GenArithOpFloat(Instruction::Code opcode,
70 void MipsMir2Lir::GenArithOpDouble(Instruction::Code opcode,
116 void MipsMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest,
168 void MipsMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest,
210 void MipsMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir,
215 void MipsMir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) {
223 void MipsMir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) {
232 bool MipsMir2Lir::GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) {
call_mips.cc 27 bool MipsMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir,
64 void MipsMir2Lir::GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
141 void MipsMir2Lir::GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
223 void MipsMir2Lir::GenFillArrayData(DexOffset table_offset, RegLocation rl_src) {
261 void MipsMir2Lir::GenMoveException(RegLocation rl_dest) {
275 void MipsMir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) {
289 void MipsMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) {
358 void MipsMir2Lir::GenExitSequence() {
371 void MipsMir2Lir::GenSpecialExitSequence() {
assemble_mips.cc 84 const MipsEncodingMap MipsMir2Lir::EncodingMap[kMipsLast] = {
460 void MipsMir2Lir::ConvertShortToLongBranch(LIR* lir) {
515 AssemblerStatus MipsMir2Lir::AssembleInstructions(CodeOffset start_addr) {
    [all...]
codegen_mips.h 25 class MipsMir2Lir FINAL : public Mir2Lir {
27 MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);

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