| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 66 /// OpKind - Specify what kind of operand this is. This discriminates the
68 MachineOperandType OpKind;
184 : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {}
188 MachineOperandType getType() const { return (MachineOperandType)OpKind; }
227 bool isReg() const { return OpKind == MO_Register; }
229 bool isImm() const { return OpKind == MO_Immediate; }
231 bool isCImm() const { return OpKind == MO_CImmediate; }
233 bool isFPImm() const { return OpKind == MO_FPImmediate; }
235 bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
237 bool isFI() const { return OpKind == MO_FrameIndex;
[all...] |
| /art/compiler/dex/quick/arm/ |
| codegen_arm.h | 147 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
149 LIR* OpReg(OpKind op, RegStorage r_dest_src);
152 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
153 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
156 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
157 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
158 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
166 LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2,
168 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
187 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE
[all...] |
| utility_arm.cc | 223 LIR* ArmMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
238 LIR* ArmMir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2,
371 LIR* ArmMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {
385 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
390 LIR* ArmMir2Lir::OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1,
459 LIR* ArmMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) {
463 LIR* ArmMir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) {
600 LIR* ArmMir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) {
[all...] |
| /art/compiler/dex/quick/arm64/ |
| codegen_arm64.h | 212 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
214 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE;
217 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE;
218 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE;
221 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
222 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE;
223 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
260 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
362 void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
364 LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value)
[all...] |
| utility_arm64.cc | 550 LIR* Arm64Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
566 LIR* Arm64Mir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) {
634 LIR* Arm64Mir2Lir::OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2,
669 LIR* Arm64Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {
690 LIR* Arm64Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
695 LIR* Arm64Mir2Lir::OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1,
763 LIR* Arm64Mir2Lir::OpRegRegRegExtend(OpKind op, RegStorage r_dest, RegStorage r_src1,
801 LIR* Arm64Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) {
805 LIR* Arm64Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) {
809 LIR* Arm64Mir2Lir::OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value)
[all...] |
| int_arm64.cc | 65 OpKind op = kOpBkpt;
[all...] |
| /art/compiler/dex/quick/mips/ |
| codegen_mips.h | 144 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
146 LIR* OpReg(OpKind op, RegStorage r_dest_src);
149 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
150 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
153 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
154 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
155 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
182 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
|
| utility_mips.cc | 116 LIR* MipsMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
131 LIR* MipsMir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) {
161 LIR* MipsMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) {
202 LIR* MipsMir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) {
285 LIR* MipsMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {
339 LIR* MipsMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
683 LIR* MipsMir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) {
693 LIR* MipsMir2Lir::InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) {
|
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 76 class OpKind {
81 OpKind() : Repr(OK_Invalid) {}
83 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
84 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
86 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; }
87 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; }
88 static OpKind getImm(unsigned V) {
91 OpKind K; K.Repr = OK_Imm+V; return K
[all...] |
| /art/compiler/dex/quick/x86/ |
| codegen_x86.h | 271 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
273 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE;
276 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE;
277 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE;
280 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
281 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE;
282 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
369 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
[all...] |
| utility_x86.cc | 120 LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
133 LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) {
195 LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {
356 LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
364 LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) {
392 LIR* X86Mir2Lir::OpMemReg(OpKind op, RegLocation rl_dest, int r_value) {
420 LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegLocation rl_value) {
445 LIR* X86Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1,
497 LIR* X86Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src, int value) {
523 LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset)
[all...] |
| int_x86.cc | [all...] |
| /art/compiler/dex/portable/ |
| mir_to_gbc.h | 123 ::llvm::Value* GenArithOp(OpKind op, bool is_long, ::llvm::Value* src1,
125 void ConvertFPArithOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1,
131 void ConvertArithOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1,
133 void ConvertArithOpLit(OpKind op, RegLocation rl_dest, RegLocation rl_src1,
|
| mir_to_gbc.cc | 386 ::llvm::Value* MirConverter::GenArithOp(OpKind op, bool is_long,
408 void MirConverter::ConvertFPArithOp(OpKind op, RegLocation rl_dest,
445 void MirConverter::ConvertArithOp(OpKind op, RegLocation rl_dest,
454 void MirConverter::ConvertArithOpLit(OpKind op, RegLocation rl_dest,
[all...] |
| /art/compiler/dex/ |
| compiler_enums.h | 277 enum OpKind {
333 std::ostream& operator<<(std::ostream& os, const OpKind& kind);
|
| /art/compiler/dex/quick/ |
| mir_to_lir.h | [all...] |
| gen_common.cc | 330 OpKind op = kOpInvalid;
[all...] |
| /external/clang/lib/Parse/ |
| ParseExpr.cpp | [all...] |
| ParseExprCXX.cpp | [all...] |
| /external/clang/lib/Sema/ |
| SemaExprCXX.cpp | [all...] |
| SemaExprMember.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 663 std::unique_ptr<X86Operand> ParseIntelOperator(unsigned OpKind);
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineInstr.cpp | 121 OpKind = MO_Immediate;
143 OpKind = MO_Register;
[all...] |
| /external/clang/include/clang/Sema/ |
| Sema.h | [all...] |
| /external/clang/include/clang/Parse/ |
| Parser.h | [all...] |
